WO1996025802A3 - System, transmitting and receiving circuitry for serially transmitting and serially receiving encoded information and method of operation - Google Patents

System, transmitting and receiving circuitry for serially transmitting and serially receiving encoded information and method of operation Download PDF

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Publication number
WO1996025802A3
WO1996025802A3 PCT/IB1996/000220 IB9600220W WO9625802A3 WO 1996025802 A3 WO1996025802 A3 WO 1996025802A3 IB 9600220 W IB9600220 W IB 9600220W WO 9625802 A3 WO9625802 A3 WO 9625802A3
Authority
WO
WIPO (PCT)
Prior art keywords
frames
transmitting
erroneous uncorrectable
serially
frame
Prior art date
Application number
PCT/IB1996/000220
Other languages
French (fr)
Other versions
WO1996025802A2 (en
Inventor
Thomas J Campana Jr
Original Assignee
Ntp Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/386,060 external-priority patent/US5751773A/en
Priority claimed from US08/385,143 external-priority patent/US5694428A/en
Application filed by Ntp Inc filed Critical Ntp Inc
Priority to AU47308/96A priority Critical patent/AU4730896A/en
Publication of WO1996025802A2 publication Critical patent/WO1996025802A2/en
Publication of WO1996025802A3 publication Critical patent/WO1996025802A3/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L27/00—Modulated-carrier systems
    • H04L27/18—Phase-modulated carrier systems, i.e. using phase-shift keying
    • H04L27/22—Demodulator circuits; Receiver circuits
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0045—Arrangements at the receiver end
    • H04L1/0047—Decoding adapted to other signal detection operation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/0079—Receiver details
    • H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L7/00—Arrangements for synchronising receiver with transmitter
    • H04L7/04—Speed or phase control by synchronisation signals
    • H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L1/00—Arrangements for detecting or preventing errors in the information received
    • H04L1/004—Arrangements for detecting or preventing errors in the information received by using forward error control
    • H04L1/0056—Systems characterized by the type of code used
    • H04L1/0057—Block codes

Abstract

The present invention provides reconstruction and resynchronization of wireless serial transmissions causing erroneous uncorrectable bit errors exceeding the error correction code (C figs. 5A, 5B and 5C) capacity of frames (fig. 5B) of digitally encoded data. Valid data is reconstructed in frames which have all erroneous uncorrectable bits within the error correction code bit held (862). A synchronization marker (S' Figs. 5A and 5B)) is transmitted with each frame group which does not represent any valid data in a frame. Detection of the synchronization marker (882 fig. 26C) by the digital signal processor (726 fig. 21) after at least one frame is determined to contain at least one erroneous uncorrectable bit. Resynchronizes the clock of a processor of the receiving circuitry. After resynchronization of the clock (B fig. 26B), frames beginning with at least one frame containing at least one erroneous uncorrectable bit are reconstructed to recover a data in frames which do not contain at least one erroneous uncorrectable bit and to recover valid data bits in frames containing at least one erroneous uncorrectable bit (864, 868).
PCT/IB1996/000220 1995-02-07 1996-02-05 System, transmitting and receiving circuitry for serially transmitting and serially receiving encoded information and method of operation WO1996025802A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU47308/96A AU4730896A (en) 1995-02-07 1996-02-05 System, transmitting and receiving circuitry for serially transmitting and serially receiving encoded information and method of operation

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US08/385,143 1995-02-07
US08/386,060 1995-02-07
US08/386,060 US5751773A (en) 1992-03-12 1995-02-07 System for wireless serial transmission of encoded information
US08/385,143 US5694428A (en) 1992-03-12 1995-02-07 Transmitting circuitry for serial transmission of encoded information
US08/385,312 1995-02-07

Publications (2)

Publication Number Publication Date
WO1996025802A2 WO1996025802A2 (en) 1996-08-22
WO1996025802A3 true WO1996025802A3 (en) 1996-10-10

Family

ID=27010903

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB1996/000220 WO1996025802A2 (en) 1995-02-07 1996-02-05 System, transmitting and receiving circuitry for serially transmitting and serially receiving encoded information and method of operation

Country Status (1)

Country Link
WO (1) WO1996025802A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB201806129D0 (en) 2018-04-13 2018-05-30 Nordic Semiconductor Asa Radio communications

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5142582A (en) * 1989-04-28 1992-08-25 Hitachi, Ltd. Speech coding and decoding system with background sound reproducing function
US5446759A (en) * 1992-03-12 1995-08-29 Ntp Incorporated Information transmission system and method of operation
US5517511A (en) * 1992-11-30 1996-05-14 Digital Voice Systems, Inc. Digital transmission of acoustic signals over a noisy communication channel

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5142582A (en) * 1989-04-28 1992-08-25 Hitachi, Ltd. Speech coding and decoding system with background sound reproducing function
US5446759A (en) * 1992-03-12 1995-08-29 Ntp Incorporated Information transmission system and method of operation
US5517511A (en) * 1992-11-30 1996-05-14 Digital Voice Systems, Inc. Digital transmission of acoustic signals over a noisy communication channel

Also Published As

Publication number Publication date
WO1996025802A2 (en) 1996-08-22

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