WO1996026522A1 - Flash programming of flash eeprom array - Google Patents

Flash programming of flash eeprom array Download PDF

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Publication number
WO1996026522A1
WO1996026522A1 PCT/US1995/016805 US9516805W WO9626522A1 WO 1996026522 A1 WO1996026522 A1 WO 1996026522A1 US 9516805 W US9516805 W US 9516805W WO 9626522 A1 WO9626522 A1 WO 9626522A1
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WO
WIPO (PCT)
Prior art keywords
memory cells
array
substrate
applying
voltage
Prior art date
Application number
PCT/US1995/016805
Other languages
French (fr)
Inventor
Sameer Haddad
Hao Fang
Original Assignee
Advanced Micro Devices, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Priority to EP95943963A priority Critical patent/EP0819308B1/en
Priority to DE69510237T priority patent/DE69510237T2/en
Publication of WO1996026522A1 publication Critical patent/WO1996026522A1/en

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Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3477—Circuits or methods to prevent overerasing of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate erasing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3436—Arrangements for verifying correct programming or erasure
    • G11C16/3468—Prevention of overerasure or overprogramming, e.g. by verifying whilst erasing or writing
    • G11C16/3486—Circuits or methods to prevent overprogramming of nonvolatile memory cells, e.g. by detecting onset or cessation of current flow in cells and using the detector output to terminate programming
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/16—Flash programming of all the cells in an array, sector or block simultaneously
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2216/00—Indexing scheme relating to G11C16/00 and subgroups, for features not directly covered by these groups
    • G11C2216/12—Reading and writing aspects of erasable programmable read-only memories
    • G11C2216/18—Flash erasure of all the cells in an array, sector or block simultaneously

Definitions

  • This invention relates generally to floating gate memory devices such as an array of flash electrically erasable and programmable read-only memory devices (EEPROMs) . More particularly, the present invention relates to an improved method for bulk (or byte) programming a flash EEPROM device having a floating gate structure.
  • EEPROMs electrically erasable and programmable read-only memory devices
  • flash EEPROMs As is generally known in the art, there exists a class of non-volatile memory devices referred to as "flash EEPROMs" which has recently emerged as an important memory device by combining the advantages of EPROM density with EEPROM electrical erasability. Such flash EEPROMs provide electrical erasing and a small cell size. The operation and structure of such flash EEPROMs is discussed in U.S. Patent No. 5,077,691 to Sameer S. Haddad et al . issued on December 31, 1991, which is as ⁇ signed to the same assignee as in the present invention and is hereby incorporated by reference in its entirety.
  • the '691 patent discloses a flash EEPROM cell array which is erased by applying a zero reference voltage to the bulk substrate of the cell, a relatively high negative voltage to the control gate of the cell, and a relatively low positive voltage to the source region of the cell.
  • a relatively high positive voltage i.e., +12 V
  • the source regions of all transistors in the selected sectors are connected to a ground potential of zero volts, and the drain regions thereof are raised to an intermediate high positive level of approximately +6.5 volts.
  • Each of the plurality of flash EEPROM cells may be formed on a semiconductor substrate, typically of a p-type conductivity. Drain and source regions are formed in the upper portions of the p-type substrate by using a diffusion method such as ion-implantation technique with an n-type dopant of arsenic or phosphorus. The formation of the n-type drain and source regions define a channel region on the p-type substrate. A tunneling oxide film is formed on the channel region in the p-type substrate. A conductive polysilicon floating gate is formed on the tunneling oxide film. An interpoly dielectric is formed on the floating gate. A polysilicon control gate is insulatively formed on the interpoly dielectric.
  • the flash EEPROM cell is erased by applying a positive voltage to the source region while the control gate is grounded or biased to a negative voltage.
  • all of the cells therein are usually erased in bulk (i.e., either the entire chip or by sectors each having a large number of floating gate transistors) . This is due to the fact that their source regions are all tied to a common source line.
  • the flash EEPROM cell is programmed by applying a relatively high voltage to the control gate and a moderately high voltage to the drain region. The source region is connected to a ground potential.
  • a number of disadvantages may be encountered with the conventional way in which the flash EEPROM cells are programmed.
  • One drawback is because of the different voltages required to be applied to the control gates and source regions (i.e., +12 V and +6 V) during programming. Thus, it is frequently necessary to provide at least two power supplies for generating these voltages. Further, the magnitude of the programming current tends to be relatively high, on the order of approximately 400 ⁇ A per cell. As a consequence, the power requirement of a memory chip having one million or more memory cells (a one megabit chip) can be excessive.
  • the second drawback of the conventional programming technique arises from the fact that a relatively high field is generated between the drain and the substrate during programming (p-type substrate has 0 V applied and the n-type drain region is at +6 V) .
  • high energy holes generated by a so-called “impact ionization”
  • impact ionization high energy holes generated by a so-called “impact ionization”
  • a third drawback associated with the conventional programming technique is that the bulk programming time is relatively long.
  • the byte programming is less than 10 ⁇ S.
  • the total programming time for the whole sector will be in the order of a second. It would therefore be desirable to provide an EEPROM chip which has a relatively fast bulk programming time for the whole sector, on the order of less than 100 ⁇ S.
  • the substrate is typically common for the core devices and the peripheral circuitry.
  • the core array will be located inside a large p-well area.
  • a p-well area is demonstrated in a memory array architecture which is known in the prior art and is sometimes referred to as DINOR (divided bit line NOR) flash memory.
  • the term “charging” refers to placing negative charges on the floating gate and is typically referred to a "programming.”
  • the term “dis ⁇ charging” refers to extracting negative charges from the floating gate and is typically referred to as “erasing.”
  • the term “charging” is used to mean “erasing” since it is a bulk operation and the term “discharging” is used to mean “programming.”
  • Fowler-Norheim tunneling which requires a high field to be applied to the cell.
  • the voltage condition of the DINOR cell in the erase opera ⁇ tion for the selected sector is +10 V on the word lines (control gates) and -8 V on the p-well and the sources.
  • this technique suffers from the disadvantages of high voltages and slow bulk charging.
  • a method for bulk (or byte) programming an array of flash EEPROM memory cells the array being formed on a substrate to define columns and rows, where the substrate includes a common source line extending along at least one of the rows, a common substrate line, and a plurality of bit lines extending along respective columns.
  • Each of the memory cells includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines.
  • the bulk (or byte) programming is achieved by applying a negative voltage to the substrate of the array.
  • a reference voltage of zero volts to the drain regions of the selected memory cells in the array that are to be programmed. Further, there is applied simultaneously the same reference voltage of zero volts to the control gates of the selected memory cells.
  • a method for bulk (or byte) programming and source-side erasing an array of flash EEPROM memory cells there is provided a method for bulk (or byte) programming (charging) and bulk (or byte) erasing (discharging) an array of flash EEPROM memory cells.
  • Figure 1 shows a cross-sectional view of a flash
  • EEPROM cell having a floating gate structure to which the present method of bulk (or byte) programming can be applied;
  • Figure 2 illustrates the APD dependence on the voltage applied to the substrate
  • Figure 3 illustrates the programming dependence on the drain bias under a fixed drain-to-substrate voltage
  • Figure 4 depicts the program and erase character ⁇ istics, with the applied voltages on the inset
  • Figure 5 shows the measured gated diode current and the negative gate current as a function of sweeping the drain voltage positively with the substrate grounded;
  • Figure 6 shows the measured gated diode current and the positive gate current as a function of sweeping the substrate voltage negatively with the drain grounded;
  • Figure 7(a) illustrates the endurance characteriza- tion for flash programming and flash erasing in accord ⁇ ance with the present invention
  • Figure 7(b) illustrates the endurance characteriza ⁇ tion for standard source-side erasing and flash program ⁇ ming in accordance with the present invention
  • Figure 8 is a schematic circuit diagram of a portion of a flash EEPROM array for byte programming in accordance with the invention.
  • Figure 9 shows the disturbance of the threshold voltages of a flash memory cell on the unselected word line during flash erase/byte programming in accordance with the invention
  • Figure 10 shows a cross-sectional view of a flash memory cell in a p-well area having a floating gate structure to which the present method of bulk (or byte) programming can be applied.
  • the present invention provides an improved method for bulk (or byte) programming an array of flash elec- trically erasable and programmable read-only memory
  • FIG. 1 illustrates a conventional flash EEPROM cell or device 10. It is to be understood that a large number, N x M (i.e., 1,000 or more) , of such cells 10 are typically formed as a part of a single integrated circuit chip (not shown) and arranged in an N x M matrix. An external or off-chip single, low voltage power supply, which is typically at +3.0 V, is supplied to the integrated circuit chip.
  • N x M i.e., 1,000 or more
  • An external or off-chip single, low voltage power supply which is typically at +3.0 V, is supplied to the integrated circuit chip.
  • the array of the flash EEPROM memory cells is formed on a substrate to define columns and rows, where the substrate includes a common source line extending along at least one of the rows, a common substrate line, and a plurality of bit lines extending along respective columns.
  • Each of the memory cells include an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines.
  • EEPROM cell 10 is formed of a substrate 12, typically of a p-type conductivity having embedded therein an n * drain region 14 and an n-type double-diffused source region 16.
  • the double-diffused source region 16 is formed of a deeply diffused but lightly doped n-junction 18 (phos ⁇ phorus doped) and a more heavily doped but shallower n + junction 20 (arsenic doped) embedded within the deep n-junction 18.
  • a relatively thin gate dielectric 22 i.e., oxide of approximately 100 A thickness
  • the poly ⁇ silicon control gate 26 is insulatively supported above the floating gate 24 by an interpolydielectric layer 28.
  • a channel region 30 in the substrate 12 separates the drain region 14 and the source region 16.
  • a terminal pin 15 for applying a source voltage V s to the source region 16.
  • a terminal pin 17 is provided for applying a gate voltage V G to the control gate 26.
  • a the terminal pin 19 is provided for a applying drain voltage V D to the drain region 14.
  • a terminal pin 21 is provided for applying a substrate voltage V sub to the substrate 12.
  • the flash EEPROM cell of Figure 1 is programmed by applying a relatively high voltage V G (approximately +9 volts) to the control gate 26 via the terminal pin 17 and a moderately high voltage V D (approximately +5 volts) to the drain region 14 via the terminal pin 19.
  • Figure 10 a cross- sectional view of a flash memory cell 210 formed in a p-well area having a floating gate structure.
  • this architecture permits the application of a substrate voltage to the cells in the core array when it is desired to have the substrate potential kept at an independent potential.
  • the cell 210 is substantially identical to the EEPROM cell 10 of Figure 1, except that the core cell 210 is formed in a large p-well 212 rather than in the p-type substrate 12.
  • the p-well 212 is functionally equivalent to the substrate 12.
  • the p-well 212 is located with an n-well 214 that is disposed in the bulk substrate 216.
  • a terminal pin 213 is provided for applying a p-well voltage V p . well (V sub ) to the p-well 212.
  • a terminal pin 217 is provided for applying a bulk substrate voltage V B to the bulk substrate 216.
  • a terminal pin 215 is provided for applying an n-well voltage V n . well to the n-well 214. Except for these differences, the two cells 10 and 210 are identical in their construction and operation.
  • the inventors conducted an investigation to explain the dependence of the self-convergence point on the voltage applied to the drain voltage during automatic programming disturb (APD) .
  • automatic program disturb refers to soft program ⁇ ming of the unselected cell during programming of the other cells on the same bit line.
  • the gated diode vertical field at the drain side is approximately equal to -8.5 V, which corresponds to the drain junction breakdown voltage. It is also worth noting that for V sub s -3 V, the threshold voltage of the cell converges to essentially the same voltage of +3 volts.
  • the significant enhancement in APD programming suggests that a significant supply of hot electrons could be provided if the cell was operated in the breakdown region. Thus, by controlling the vertical field, the cell could then be programmed or erased.
  • the threshold voltages V t as a function of the APD time of the memory cell is plotted in Figure 3 with the drain voltage and the substrate voltage as defined in the inset.
  • the gated diode field (drain-to- substrate voltage V dsub ) was maintained to be equal to +9 V with the varying drain voltage V d .
  • the value of the convergence threshold voltage is directly determined by the resultant vertical field, which is in turn governed by the drain-to-floating gate coupling ratios and the substrate voltage.
  • the cell can be erased (charged) or programmed (discharged) .
  • the program and erase characteristics of the memory cell is shown in Figure 4. In this case, the programming operation is accomplished by applying +3 V on the drain
  • the inventive method of applying a negative to the substrate during programming will not inject hot-hole carriers to the interface and will reduce significantly the degrada ⁇ tion in programmability.
  • the reasons for the reduction in hot-hole injection are given as follows: (1) the location of the high field is away from the oxide silicon interface, (2) the magnitude of the maximum field is reduced by more than 50%, and (3) the vertical field does not favor hole injection.
  • measurements of the drain current I d and gate current I g were obtained by sweeping the voltage applied to the drain positively with the substrate being grounded, as is illustrated in Figure 5. Also, the measurements of the drain current I d and the gate current I g were obtained by sweeping the voltage applied to the substrate negatively with the drain being grounded as depicted in Figure 6. As can be seen from a comparison of Figures 6 and 5, by sweeping the substrate negatively, the junction breakdown voltage is only in ⁇ creased slightly, and the gate current dominated by electron injection is higher than the gate current dominated by hole injection with the sweeping of the drain voltage.
  • this enhanced electron gate current is the mechanism which enables fast programming (i.e., less than 10 ⁇ S) .
  • fast programming i.e., less than 10 ⁇ S
  • the moderate high voltage applied to the drain during conventional programming hot-carriers are generated close to the top surface of the substrate.
  • the potential of the floating gate is lower than the drain bias so that the vertical field favors hot-hole injection thereby rendering severe degradation thereto.
  • a negative voltage to the substrate during programming in the present method a breakdown will occur away from the top surface and thus the hot-hole induced oxide damage is significantly reduced as shown in Figure 7(b) .
  • the threshold voltage V c was measured as a function of the number of erase/programming cycles as shown in Figure 7(a).
  • the conventional or drain-side erase condition utilizing +8.5 V applied to the drain for 100 ms and zero volts applied to the control gate was used. The source was allowed to float.
  • the flash pro ⁇ gramming condition of the present invention utilizing -8.5 V applied to the substrate for 10 ⁇ S and 0 V applied to the control gate and drain was performed. The source region was again allowed to float. It was observed that after 1,000 cycles the threshold voltage V c after pro ⁇ gramming and erase started to degrade. It should be pointed out that for certain applications, such as programmable logic memories, where endurance is only required up to 100 cycles this present method could be utilized which allows for fast charging (programming) and discharging (erasing) at relatively low operational voltage.
  • the endurance could be improved by optimizing the gate oxide using such as nitrided oxide or re-engineering the peak electric field region (or buried channel doping) .
  • thicker gate oxide greater than 100 A could be used so as to improve endurance because the present method relies upon hot-carrier injection rather than by Fowler-Norheim tunneling.
  • the memory cell was erased each time using the conventional source-side erase (i.e., -9 V on the control gate for 100 ms, and +5 V on the source for 100 ms with the drain floating) .
  • the conventional source-side erase i.e., -9 V on the control gate for 100 ms, and +5 V on the source for 100 ms with the drain floating.
  • different voltages were applied to the drains but yet maintaining the same drain- to-substrate field. It was observed that the endurance of the memory cell was degraded approximately by one order of magnitude when the drain voltage V d was at ⁇ +2 V.
  • This novel programming method according to the present invention is achieved by applying -8.5 V to the substrate for 5 ⁇ S, zero volts applied to the drain and control gate, and the source being allowed to float.
  • the current requirement during programming is relatively small, on the order of 1 ⁇ A per cell, as compared to approximately 400 ⁇ A per cell for channel hot electron programming.
  • a 10 M ⁇ resistor is used in series with the drain. Because of this low current requirement, the high negative voltage applied to the substrate and gate during the respective programming and erase operations, can be generated internally on the same integrated circuit chip by a charge pump circuit that is connected to only a single, low voltage (5 Volt) power supply.
  • the present flash programming and standard source-erase combination has a fast programming speed of less than 10 ⁇ S and a reliability of more than 100,000 cycles as illustrated in Figure 7(b).
  • the novel bulk (or byte) programming (charging) method is equally applicable to the DINOR type cell architecture of Figure 10 in order to achieve both program and erase speed within 100 ⁇ S or less.
  • the bulk charging (referred to as erasing in the DINOR type architecture) will be done on the source side rather than on the drain side.
  • the bulk charging is achieved by applying -8.5 V to the p-well for 5 uS, zero volts applied to the source and the control gate, and the drain being allowed to float.
  • the n-well is also grounded.
  • the inventors have now also determined that this bulk charging can be achieved with positive voltages rather than using negative voltages.
  • the bulk charging is accomplished by applying +8.5 V to the source and to the control gate for 5 ⁇ S, zero volts applied to the p-well (substrate) , and the drain being allowed to float.
  • the n-well is applied with a positive inter ⁇ mediate voltage of approximately +5 V.
  • the bulk charging may be accomplished alternatively by applying zero volts to the p-well (substrate) and +8.5 V to the drain and to the control gate for the 5 ⁇ S, the source being allowed to float.
  • the device structure and the flash programming/ standard source-side erase method discussed above permits the formation of a high density (1 megabit) EEPROM array in which a large section of the array can be programmed simultaneously.
  • an EEPROM array 110 of such devices is illustrated which can provide such high density.
  • the array 110 is formed of a plurality of memory cells MC 11 ...MC HMf with N rows and M columns.
  • the peripheral circuitry on the device includes conventional row address decoder, column address decoder, sense amplifier circuitry, and input/output buffer circuitry which have been purposely omitted for the sake of clarity.
  • drains of the transistors in the same column are connected together and to a shared bit line (i.e., BL1) connectible to the column address decoder (not shown) .
  • the gates of the transistors in the same row i.e., MC 11# MC 12 .
  • a shared wordline i.e., WL1 .
  • sources of the transistors in the same row are connected together by a source line and then all of the source lines are joined together to a common source lead 112.
  • substrates of the transistors in the same row are connected together by a substrate line and then all the substrate lines are joined together to a common substrate lead 114.
  • erasing of the cells can be done on a whole array or a number of sectors (bulk erase) by utilizing the standard source-side erase method as previously described. For example, a negative voltage could be applied to all of the wordlines of the cells desired to be erased from the row address decoder (not shown) . At the same time, a common source lead 112 could be raised to the positive voltage. Further, due to the common substrate lead 114 programming of the cells can be easily performed on a byte-by-byte basis (smaller segments of rows can be selectively programmed as desired) .
  • the flash programming method of the present invention as previously described is used.
  • the negative voltage would be applied to the substrate of the cells desired to be programmed by way of the common substrate lead 114.
  • the wordline containing the selected byte to be programmed would be held to a ground potential.
  • the bit lines containing the selected byte to be programmed would likewise be held to a ground potential.
  • the common source lead 112 is allowed to float.
  • the substrate in the unselected cells are also supplied with the negative voltage and since the drains of the other unselected cells are floating, the contents of these unselected cells may be disturbed if the bit line capacitance is high.
  • all of the unselected wordlines are connected to the same negative voltage supply, V aub , to inhibit program disturb of the unselected bytes.
  • V aub negative voltage supply
  • the byte programming and disturbance character ⁇ istic of the unselected wordlines is illustrated in Figure 9. Further, in order to reduce the field below breakdown on the drain side of the unselected bit lines during programming, it would be preferable to suitably apply a negative voltage of approximately -3 V on the unselected lines and thus eliminate any disturbance.
  • the improved performance of the present invention has been achieved by the combination of employing the standard source-side EEPROM or flash erase method for bulk erasing and employing the improved flash programming method of the instant invention for bulk (or byte) programming of the memory cells in an array.
  • the present invention provides low current, fast programming which requires only a single, low voltage power supply. This is accomplished by applying a negative voltage to the substrate of the selected cells in the array and simultaneously applying zero volts to the drains and control gates thereof.
  • a positive bias configuration as mentioned above can be used to replace the negative bias configuration. This is because it is easier to design with positive voltages which could eliminate the need for a p-well.

Abstract

There is provided an improved method for bulk (or byte) programming an array of flash EEPROM memory cells. A negative voltage is applied to the substrate of the array. A reference voltage of zero volts is applied simultaneously to the drain regions of selected memory cells that are to be programmed. There is also applied simultaneously the same reference voltage of zero volts to the control gates of the selected memory cells. The present invention provides for low current consumption and fast programming of the memory cell, which require only a single, low voltage power supply. The endurance reliability is greater than 100,000 cycles.

Description

Flash programming of flash EEPROM array
BACKGROUND OF THE INVENTION
1. Field of the Invention:
This invention relates generally to floating gate memory devices such as an array of flash electrically erasable and programmable read-only memory devices (EEPROMs) . More particularly, the present invention relates to an improved method for bulk (or byte) programming a flash EEPROM device having a floating gate structure.
2. Description of the Prior Art:
As is generally known in the art, there exists a class of non-volatile memory devices referred to as "flash EEPROMs" which has recently emerged as an important memory device by combining the advantages of EPROM density with EEPROM electrical erasability. Such flash EEPROMs provide electrical erasing and a small cell size. The operation and structure of such flash EEPROMs is discussed in U.S. Patent No. 5,077,691 to Sameer S. Haddad et al . issued on December 31, 1991, which is as¬ signed to the same assignee as in the present invention and is hereby incorporated by reference in its entirety. The '691 patent discloses a flash EEPROM cell array which is erased by applying a zero reference voltage to the bulk substrate of the cell, a relatively high negative voltage to the control gate of the cell, and a relatively low positive voltage to the source region of the cell. During the sector-programming mode of operation, a relatively high positive voltage (i.e., +12 V) is applied to the control gates via wordlines of the selected sectors while zero volts are applied to the control gates of the memory cells in the non-selected sectors. Further, the source regions of all transistors in the selected sectors are connected to a ground potential of zero volts, and the drain regions thereof are raised to an intermediate high positive level of approximately +6.5 volts.
Another discussion regarding the operation and structure of flash EEPROM devices is described in U.S. Patent No. 5,126,808 to Antonio J. Montalvo et al . issued on June 30, 1992, which is assigned to the same assignee as in the present invention and is also hereby incor- porated by reference in its entirety. In the '808 patent, there is disclosed a flash EEPROM array with page erase architecture in which a selected page of the memory array can be erased and replaced with new data without affecting the other pages of the memory array. Erasure of a flash EEPROM cell in the array is accomplished by use of a negative voltage on the control gate of the EEPROM cell.
Each of the plurality of flash EEPROM cells may be formed on a semiconductor substrate, typically of a p-type conductivity. Drain and source regions are formed in the upper portions of the p-type substrate by using a diffusion method such as ion-implantation technique with an n-type dopant of arsenic or phosphorus. The formation of the n-type drain and source regions define a channel region on the p-type substrate. A tunneling oxide film is formed on the channel region in the p-type substrate. A conductive polysilicon floating gate is formed on the tunneling oxide film. An interpoly dielectric is formed on the floating gate. A polysilicon control gate is insulatively formed on the interpoly dielectric.
According to conventional operation, the flash EEPROM cell is erased by applying a positive voltage to the source region while the control gate is grounded or biased to a negative voltage. In flash EEPROM arrays, all of the cells therein are usually erased in bulk (i.e., either the entire chip or by sectors each having a large number of floating gate transistors) . This is due to the fact that their source regions are all tied to a common source line. On the other hand, the flash EEPROM cell is programmed by applying a relatively high voltage to the control gate and a moderately high voltage to the drain region. The source region is connected to a ground potential.
A number of disadvantages may be encountered with the conventional way in which the flash EEPROM cells are programmed. One drawback is because of the different voltages required to be applied to the control gates and source regions (i.e., +12 V and +6 V) during programming. Thus, it is frequently necessary to provide at least two power supplies for generating these voltages. Further, the magnitude of the programming current tends to be relatively high, on the order of approximately 400 μA per cell. As a consequence, the power requirement of a memory chip having one million or more memory cells (a one megabit chip) can be excessive. There has been a long felt need in the industry to develop a flash EEPROM chip which can be operated by only a single, low voltage power supply (i.e., +3 V) that has a low current require¬ ment (i.e., 1 μA per cell) .
The second drawback of the conventional programming technique arises from the fact that a relatively high field is generated between the drain and the substrate during programming (p-type substrate has 0 V applied and the n-type drain region is at +6 V) . As a result, there may be caused high energy holes ("hot" holes generated by a so-called "impact ionization") to be formed at the surface portion of the channel near to the drain-to- substrate junction, thereby producing damage thereto so as to cause severe degradation in its performance and reliability.
A third drawback associated with the conventional programming technique is that the bulk programming time is relatively long. For the conventional method (using hot-carrier injection) , the byte programming is less than 10 μS. However, there is needed to be programmed thousands of bytes (i.e., 64 K bytes for a sector size of 512 K bits) . Further, this is done serially. Thus, the total programming time for the whole sector will be in the order of a second. It would therefore be desirable to provide an EEPROM chip which has a relatively fast bulk programming time for the whole sector, on the order of less than 100 μS.
As is generally known, the substrate is typically common for the core devices and the peripheral circuitry. In order to have the capability of applying a substrate voltage to the cells in the core array but yet maintain the substrate at an independent potential, typically at 0 volts, the core array will be located inside a large p-well area. For example, such use of a p-well area is demonstrated in a memory array architecture which is known in the prior art and is sometimes referred to as DINOR (divided bit line NOR) flash memory. For a more detailed discussion of this DINOR type architecture, reference is made to an IEEE paper entitled "Memory Array Architecture and Decoding Scheme for 3 V Only Sector Erasable DINOR Flash Memory" by Shin-ichi Kobayashi et al., IEEE Journal of Solid-State Circuits, Vol. 29, No. 4, April, 1994, pp. 454-460. This article is incorporated herein by reference.
As defined herein, the term "charging" refers to placing negative charges on the floating gate and is typically referred to a "programming." The term "dis¬ charging" refers to extracting negative charges from the floating gate and is typically referred to as "erasing." However, for the DINOR type architecture the term "charging" is used to mean "erasing" since it is a bulk operation and the term "discharging" is used to mean "programming." In the above-mentioned article, there is described a bulk charging method for the memory array using Fowler-Norheim tunneling which requires a high field to be applied to the cell. In other words, the voltage condition of the DINOR cell in the erase opera¬ tion for the selected sector is +10 V on the word lines (control gates) and -8 V on the p-well and the sources. However, this technique suffers from the disadvantages of high voltages and slow bulk charging.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide an improved method for bulk (or byte) programming a flash EEPROM device having a floating gate structure which overcomes the disadvantages of the prior art programming methods.
It is an object of the present invention to provide an improved method for bulk (or byte) programming an array of flash EEPROM memory cells which requires only a single, low voltage power supply and has a lower power consumption as compared to that of the prior art.
It is another object of the present invention to provide an improved method for bulk (or byte) programming an array of flash EEPROM memory cells which requires a smaller programming current and has a relatively fast programming time than those traditionally available.
It is still another object of the present invention to provide an improved method for bulk (or byte) program¬ ming an array of flash EEPROM memory cells which is realized by applying a negative voltage to the substrate of the array and applying simultaneously zero volts to the drain regions and control gates of selected memory cells in the array that are to be programmed.
In a preferred embodiment of the present invention, there is provided a method for bulk (or byte) programming an array of flash EEPROM memory cells, the array being formed on a substrate to define columns and rows, where the substrate includes a common source line extending along at least one of the rows, a common substrate line, and a plurality of bit lines extending along respective columns. Each of the memory cells includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines. The bulk (or byte) programming is achieved by applying a negative voltage to the substrate of the array. Simultaneously, there is applied a reference voltage of zero volts to the drain regions of the selected memory cells in the array that are to be programmed. Further, there is applied simultaneously the same reference voltage of zero volts to the control gates of the selected memory cells. In another aspect of the present invention, there is provided a method for bulk (or byte) programming and source-side erasing an array of flash EEPROM memory cells. In still another aspect of the present invention, there is provided a method for bulk (or byte) programming (charging) and bulk (or byte) erasing (discharging) an array of flash EEPROM memory cells.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other objects and advantages of the present invention will become more fully apparent from the following detailed description when read in con¬ junction with the accompanying drawings with like reference numerals indicating corresponding parts throughout, wherein:
Figure 1 shows a cross-sectional view of a flash
EEPROM cell having a floating gate structure to which the present method of bulk (or byte) programming can be applied;
Figure 2 illustrates the APD dependence on the voltage applied to the substrate;
Figure 3 illustrates the programming dependence on the drain bias under a fixed drain-to-substrate voltage; Figure 4 depicts the program and erase character¬ istics, with the applied voltages on the inset;
Figure 5 shows the measured gated diode current and the negative gate current as a function of sweeping the drain voltage positively with the substrate grounded;
Figure 6 shows the measured gated diode current and the positive gate current as a function of sweeping the substrate voltage negatively with the drain grounded;
Figure 7(a) illustrates the endurance characteriza- tion for flash programming and flash erasing in accord¬ ance with the present invention;
Figure 7(b) illustrates the endurance characteriza¬ tion for standard source-side erasing and flash program¬ ming in accordance with the present invention;
Figure 8 is a schematic circuit diagram of a portion of a flash EEPROM array for byte programming in accordance with the invention;
Figure 9 shows the disturbance of the threshold voltages of a flash memory cell on the unselected word line during flash erase/byte programming in accordance with the invention; and Figure 10 shows a cross-sectional view of a flash memory cell in a p-well area having a floating gate structure to which the present method of bulk (or byte) programming can be applied.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
It is to be distinctly understood at the outset that the present invention shown and described in association with an EEPROM device is not intended to serve as a limitation upon the scope or teachings thereof, but is merely for the purpose of convenience of illustration of one example of its application. The present invention has also applications for EPROM, DINOR type cell archi¬ tecture, or any device having a control gate capacitively coupled to a floating gate structure with a junction that can be made to break down since the invention pertains to a unique method of charging which is relatively fast and has a relatively low operational voltage.
The present invention provides an improved method for bulk (or byte) programming an array of flash elec- trically erasable and programmable read-only memory
(EEPROM) device having a floating gate structure in which each cell thereof has the same structure as that of the prior art as illustrated in Figure 1. Figure 1 illustrates a conventional flash EEPROM cell or device 10. It is to be understood that a large number, N x M (i.e., 1,000 or more) , of such cells 10 are typically formed as a part of a single integrated circuit chip (not shown) and arranged in an N x M matrix. An external or off-chip single, low voltage power supply, which is typically at +3.0 V, is supplied to the integrated circuit chip.
The array of the flash EEPROM memory cells is formed on a substrate to define columns and rows, where the substrate includes a common source line extending along at least one of the rows, a common substrate line, and a plurality of bit lines extending along respective columns. Each of the memory cells include an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines.
In particular, as can be seen from Figure 1, the
EEPROM cell 10 is formed of a substrate 12, typically of a p-type conductivity having embedded therein an n* drain region 14 and an n-type double-diffused source region 16. The double-diffused source region 16 is formed of a deeply diffused but lightly doped n-junction 18 (phos¬ phorus doped) and a more heavily doped but shallower n+ junction 20 (arsenic doped) embedded within the deep n-junction 18. A relatively thin gate dielectric 22 (i.e., oxide of approximately 100 A thickness) is interposed between the top surface of the substrate 12 and a conductive polysilicon floating gate 24. The poly¬ silicon control gate 26 is insulatively supported above the floating gate 24 by an interpolydielectric layer 28. A channel region 30 in the substrate 12 separates the drain region 14 and the source region 16.
Further, there is provided a terminal pin 15 for applying a source voltage Vs to the source region 16. A terminal pin 17 is provided for applying a gate voltage VG to the control gate 26. A the terminal pin 19 is provided for a applying drain voltage VD to the drain region 14. Finally, a terminal pin 21 is provided for applying a substrate voltage Vsub to the substrate 12.
With reference to the programming inset of Figure 1, there is shown a schematic representation for the conventional programming operation. The flash EEPROM cell of Figure 1 is programmed by applying a relatively high voltage VG (approximately +9 volts) to the control gate 26 via the terminal pin 17 and a moderately high voltage VD (approximately +5 volts) to the drain region 14 via the terminal pin 19. The source region 16 is connected to a ground potential (Vs = 0) via the terminal pin 15. The substrate 12 is also connected to the ground potential (Vsub = 0) via the terminal pin 21.
Alternatively, there is shown in Figure 10 a cross- sectional view of a flash memory cell 210 formed in a p-well area having a floating gate structure. As was previously pointed out, this architecture permits the application of a substrate voltage to the cells in the core array when it is desired to have the substrate potential kept at an independent potential. It will be noted that the cell 210 is substantially identical to the EEPROM cell 10 of Figure 1, except that the core cell 210 is formed in a large p-well 212 rather than in the p-type substrate 12. Thus, the p-well 212 is functionally equivalent to the substrate 12. Further, the p-well 212 is located with an n-well 214 that is disposed in the bulk substrate 216. A terminal pin 213 is provided for applying a p-well voltage Vp.well (Vsub) to the p-well 212. A terminal pin 217 is provided for applying a bulk substrate voltage VB to the bulk substrate 216. Finally, a terminal pin 215 is provided for applying an n-well voltage Vn.well to the n-well 214. Except for these differences, the two cells 10 and 210 are identical in their construction and operation.
Before describing in detail the improved method for flash programming an array of flash EEPROM memory cells according to the present invention, it is believed that it would be helpful in understanding the principles of the instant invention and to serve as a background by first explaining the investigations performed and the results of the experimentation observed by the inventors.
Initially, the inventors conducted an investigation to explain the dependence of the self-convergence point on the voltage applied to the drain voltage during automatic programming disturb (APD) . As used herein, the term "automatic program disturb" refers to soft program¬ ming of the unselected cell during programming of the other cells on the same bit line. To demonstrate the APD dependence on the voltage applied to the substrate, the threshold voltages Vc of a memory cell is plotted as a function of time in Figure 2 with the fixed drain voltage Vd = +5.5 V and with six different substrate voltages Vsub as defined in the inset. It will be noted that at Vsub = -3 V the APD speed is significantly enhanced. Here, the gated diode vertical field at the drain side is approximately equal to -8.5 V, which corresponds to the drain junction breakdown voltage. It is also worth noting that for Vsub s -3 V, the threshold voltage of the cell converges to essentially the same voltage of +3 volts. The significant enhancement in APD programming suggests that a significant supply of hot electrons could be provided if the cell was operated in the breakdown region. Thus, by controlling the vertical field, the cell could then be programmed or erased.
To further demonstrate the programming dependence on the drain bias under a fixed drain-to-substrate voltage, the threshold voltages Vt as a function of the APD time of the memory cell is plotted in Figure 3 with the drain voltage and the substrate voltage as defined in the inset. As can be seen, the gated diode field (drain-to- substrate voltage Vdsub) was maintained to be equal to +9 V with the varying drain voltage Vd. It can thus be seen that the value of the convergence threshold voltage is directly determined by the resultant vertical field, which is in turn governed by the drain-to-floating gate coupling ratios and the substrate voltage. Dependent on the bias condition, the cell can be erased (charged) or programmed (discharged) . The program and erase characteristics of the memory cell is shown in Figure 4. In this case, the programming operation is accomplished by applying +3 V on the drain
(Vd = 3 V) and -6 V on the substrate (Vsub = -6 V) so as to shift upwardly the threshold voltage Vt by 4 volts in approximately .002 seconds. Similarly, the erasing operation is achieved by applying +6.5 V on the drain
(Vd = +6.5 V) and -3 V on the substrate (Vaub = -3 V) so as to shift downwardly the voltage threshold Vt by 3 volts in .002 seconds. While erasing of the cell by only applying a high positive voltage on the drain and grounding the substrate is known in the art, this technique is limited in its application due to hot-hole injection during erase which causes variation in the erased threshold voltage of the cells in the memory array and thus degradation in its programmability.
However, it will be demonstrated presently that the inventive method of applying a negative to the substrate during programming will not inject hot-hole carriers to the interface and will reduce significantly the degrada¬ tion in programmability. The reasons for the reduction in hot-hole injection are given as follows: (1) the location of the high field is away from the oxide silicon interface, (2) the magnitude of the maximum field is reduced by more than 50%, and (3) the vertical field does not favor hole injection.
In order to demonstrate that the threshold voltage Vc distribution of the memory cell is improved significantly after programming and erase by its opera¬ tion at the convergence point, measurements of the drain current Id and gate current Ig were obtained by sweeping the voltage applied to the drain positively with the substrate being grounded, as is illustrated in Figure 5. Also, the measurements of the drain current Id and the gate current Ig were obtained by sweeping the voltage applied to the substrate negatively with the drain being grounded as depicted in Figure 6. As can be seen from a comparison of Figures 6 and 5, by sweeping the substrate negatively, the junction breakdown voltage is only in¬ creased slightly, and the gate current dominated by electron injection is higher than the gate current dominated by hole injection with the sweeping of the drain voltage. Accordingly, it is believed that this enhanced electron gate current is the mechanism which enables fast programming (i.e., less than 10 μS) . With the moderate high voltage applied to the drain during conventional programming, hot-carriers are generated close to the top surface of the substrate. In this case, the potential of the floating gate is lower than the drain bias so that the vertical field favors hot-hole injection thereby rendering severe degradation thereto. On the other hand, by applying a negative voltage to the substrate during programming in the present method, a breakdown will occur away from the top surface and thus the hot-hole induced oxide damage is significantly reduced as shown in Figure 7(b) .
Since endurance of a flash memory cell is one of the major concerns, the threshold voltage Vc was measured as a function of the number of erase/programming cycles as shown in Figure 7(a). The conventional or drain-side erase condition utilizing +8.5 V applied to the drain for 100 ms and zero volts applied to the control gate was used. The source was allowed to float. The flash pro¬ gramming condition of the present invention utilizing -8.5 V applied to the substrate for 10 μS and 0 V applied to the control gate and drain was performed. The source region was again allowed to float. It was observed that after 1,000 cycles the threshold voltage Vc after pro¬ gramming and erase started to degrade. It should be pointed out that for certain applications, such as programmable logic memories, where endurance is only required up to 100 cycles this present method could be utilized which allows for fast charging (programming) and discharging (erasing) at relatively low operational voltage.
The endurance could be improved by optimizing the gate oxide using such as nitrided oxide or re-engineering the peak electric field region (or buried channel doping) . In addition, thicker gate oxide (greater than 100 A) could be used so as to improve endurance because the present method relies upon hot-carrier injection rather than by Fowler-Norheim tunneling.
In order to study the degradation dependence upon the voltage applied to the drain during programming, the memory cell was erased each time using the conventional source-side erase (i.e., -9 V on the control gate for 100 ms, and +5 V on the source for 100 ms with the drain floating) . During programming, different voltages were applied to the drains but yet maintaining the same drain- to-substrate field. It was observed that the endurance of the memory cell was degraded approximately by one order of magnitude when the drain voltage Vd was at ≥ +2 V.
In view of performing the various experimentations described above, the inventors have now discovered the improved method for flash programming an array of flash EEPROM memory cells having a floating gate structure which is used in conjunction with the conventional source-side flash erase method could be improved significantly to provide an endurance of more than 100,000 cycles, as is illustrated in Figure 7(b) per the inset. The operation of the electrically erasable and programmable read-only memory device will now be described in accordance with the present technique with reference to Figure 7 (b) . The erasing operation is accomplished by applying -8.5 V to the control gate for 100 ms, +5 V to the source for 100 ms, and the drain being allowed to float. Thus, the erase condition is identical to that of the prior art which is referred to as the standard source-side erase.
In contrast, the programming operation is different from that of the prior art. This novel programming method according to the present invention is achieved by applying -8.5 V to the substrate for 5 μS, zero volts applied to the drain and control gate, and the source being allowed to float. The current requirement during programming is relatively small, on the order of 1 μA per cell, as compared to approximately 400 μA per cell for channel hot electron programming. In order to achieve this small current and reduced hot-carrier damage during breakdown, a 10 MΩ resistor is used in series with the drain. Because of this low current requirement, the high negative voltage applied to the substrate and gate during the respective programming and erase operations, can be generated internally on the same integrated circuit chip by a charge pump circuit that is connected to only a single, low voltage (5 Volt) power supply. Due to this low current per cell, this permits more than 1,000 cells (bits) be programmed simultaneously using approximately 1 mA. Further, the present flash programming and standard source-erase combination has a fast programming speed of less than 10 μS and a reliability of more than 100,000 cycles as illustrated in Figure 7(b).
It should be clear to those skilled in the art that the novel bulk (or byte) programming (charging) method according to the present invention is equally applicable to the DINOR type cell architecture of Figure 10 in order to achieve both program and erase speed within 100 μS or less. However, the bulk charging (referred to as erasing in the DINOR type architecture) will be done on the source side rather than on the drain side. In other words, the bulk charging is achieved by applying -8.5 V to the p-well for 5 uS, zero volts applied to the source and the control gate, and the drain being allowed to float. The n-well is also grounded.
Alternatively, the inventors have now also determined that this bulk charging can be achieved with positive voltages rather than using negative voltages. Specifically, for the DINOR type architecture the bulk charging is accomplished by applying +8.5 V to the source and to the control gate for 5 μS, zero volts applied to the p-well (substrate) , and the drain being allowed to float. The n-well is applied with a positive inter¬ mediate voltage of approximately +5 V. Further, the bulk charging may be accomplished alternatively by applying zero volts to the p-well (substrate) and +8.5 V to the drain and to the control gate for the 5 μS, the source being allowed to float.
The device structure and the flash programming/ standard source-side erase method discussed above permits the formation of a high density (1 megabit) EEPROM array in which a large section of the array can be programmed simultaneously. Referring now to Figure 8, an EEPROM array 110 of such devices is illustrated which can provide such high density. The array 110 is formed of a plurality of memory cells MC11...MCHMf with N rows and M columns. The peripheral circuitry on the device includes conventional row address decoder, column address decoder, sense amplifier circuitry, and input/output buffer circuitry which have been purposely omitted for the sake of clarity.
It can be seen that the drains of the transistors in the same column (MC11# MC21,...) are connected together and to a shared bit line (i.e., BL1) connectible to the column address decoder (not shown) . The gates of the transistors in the same row (i.e., MC11# MC12....) are connected together and to a shared wordline (i.e., WL1) . Further, sources of the transistors in the same row are connected together by a source line and then all of the source lines are joined together to a common source lead 112. Also, the substrates of the transistors in the same row are connected together by a substrate line and then all the substrate lines are joined together to a common substrate lead 114.
Due to the common source lead 112 in the array 110, erasing of the cells can be done on a whole array or a number of sectors (bulk erase) by utilizing the standard source-side erase method as previously described. For example, a negative voltage could be applied to all of the wordlines of the cells desired to be erased from the row address decoder (not shown) . At the same time, a common source lead 112 could be raised to the positive voltage. Further, due to the common substrate lead 114 programming of the cells can be easily performed on a byte-by-byte basis (smaller segments of rows can be selectively programmed as desired) .
In order to achieve this byte programming, the flash programming method of the present invention as previously described is used. In other words, the negative voltage would be applied to the substrate of the cells desired to be programmed by way of the common substrate lead 114. Simultaneously, the wordline containing the selected byte to be programmed would be held to a ground potential. Also, the bit lines containing the selected byte to be programmed would likewise be held to a ground potential. The common source lead 112 is allowed to float.
However, since the substrate in the unselected cells are also supplied with the negative voltage and since the drains of the other unselected cells are floating, the contents of these unselected cells may be disturbed if the bit line capacitance is high. In the preferred embodiment, in order to insure that the data in the unselected bytes is not disturbed, all of the unselected wordlines are connected to the same negative voltage supply, Vaub, to inhibit program disturb of the unselected bytes. The byte programming and disturbance character¬ istic of the unselected wordlines is illustrated in Figure 9. Further, in order to reduce the field below breakdown on the drain side of the unselected bit lines during programming, it would be preferable to suitably apply a negative voltage of approximately -3 V on the unselected lines and thus eliminate any disturbance.
From the foregoing detailed description, it should be appreciated that the improved performance of the present invention has been achieved by the combination of employing the standard source-side EEPROM or flash erase method for bulk erasing and employing the improved flash programming method of the instant invention for bulk (or byte) programming of the memory cells in an array. As a consequence, there is realized significant improvement over the previous EEPROM structure and method for programming the same. The present invention provides low current, fast programming which requires only a single, low voltage power supply. This is accomplished by applying a negative voltage to the substrate of the selected cells in the array and simultaneously applying zero volts to the drains and control gates thereof.
As an alternative, a positive bias configuration as mentioned above can be used to replace the negative bias configuration. This is because it is easier to design with positive voltages which could eliminate the need for a p-well.
While there has been illustrated and described what are at present considered to be preferred embodiments of the present invention, it will be understood by those skilled in the art that various changes and modifications may be made, and equivalents may be substituted for elements thereof without departing from the true scope of the invention. In addition, many modifications may be made to adapt a particular situation or material to the teachings of the invention without departing from the central scope thereof. Therefore, it is intended that this invention not be limited to the particular embodi¬ ments disclosed as the best modes contemplated for carrying out the invention, but that the invention will include all embodiments falling within the scope of the appended claims.

Claims

CLAIMSWHAT IS CLAIMED IS:
1. A method for bulk (or byte) charging an array of flash EEPROM memory cells, said memory cells being formed on a substrate to define columns and rows, where the substrate includes the common source line extending along at least one of the rows, common substrate line, and a plurality of bit lines extending along respective columns, where each memory cell includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines, said method comprising the bulk (or byte) charging steps of:
applying a negative voltage to the sub¬ strate of the array;
applying simultaneously a reference voltage of zero volts to the drain regions of selected memory cells in the array that are to be programmed; and
applying simultaneously the same reference voltage of zero volts to the control gates of the selected memory cells, said source regions being allowed to float.
2. A method as claimed in Claim 1, wherein said negative voltage is in the range of -6.0 V to -10 V.
3. A method as claimed in Claim 2, wherein said negative voltage is approximately -8.5 V.
4. A method as claimed in Claim 3, wherein said negative voltage is applied for less than 100 mS.
5. A method as claimed in Claim 1, further including the step of applying a current-limiting device in series with the drain regions so as to clamp the current during the program and erase operation.
6. A method as claimed in Claim 1, further includes the step of applying a programming-inhibiting voltage of a polarity magnitude the same as the substrate voltage to the control gates of non-selected memory cells in the array which are not to be programmed during said flash programming operation so as to insure against a disturbance.
7. A method as claimed in Claim 6, further including the step of applying a negative voltage to the drain regions of the non-selected memory cells so as to insure against a disturbance.
8. A method as claimed in Claim 7, wherein said negative voltage is approximately -3 V so as to reduce the field below breakdown and thus eliminate any disturbance.
9. A method as claimed in Claim 1, wherein said source regions are allowed to float during flash program¬ ming.
10. A method for bulk (or byte) charging and source- side erasing an array of flash EEPROM memory cells, said memory cells being formed on a substrate to define columns and rows, where the substrate includes the common source line extending along at least one of the rows, common substrate line, and a plurality of bit lines extending along respective columns, where each memory cell includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines, said method comprising the bulk (or byte) charging steps of:
applying a negative voltage to the sub¬ strate of the array;
applying simultaneously a reference voltage of zero volts to the drain regions of selected memory cells in the array that are to be programmed;
applying simultaneously the same reference voltage of zero volts to the control gates of the selected memory cells;
said method further including the source- side erasing steps of applying zero volts to the substrate of the array; applying a positive voltage to the source regions of the array; and
applying a second negative voltage to the control gates, said drain regions being allowed to float during erasure.
11. A method as claimed in Claim 10, wherein said negative voltage is in the range of -6.0 V to -10 V.
12. A method as claimed in Claim 11, wherein said negative voltage is approximately -8.5 V.
13. A method as claimed in Claim 12, wherein said negative voltage is applied for less than 10 μS.
14. A method as claimed in Claim 13, further including the step of applying a current-limiting device in series with the drain regions so as to clamp the current during the program and erase operation.
15. A method as claimed in Claim 10, further includes the step of applying a programming-inhibiting voltage of a polarity magnitude the same as the substrate voltage to the control gates of non-selected memory cells in the array which are not to be programmed during said flash programming operation so as to insure against a disturbance.
16. A method as claimed in Claim 15, further including the step of applying a negative voltage to the drain regions of the non-selected memory cells so as to insure against a disturbance.
17. A method as claimed in Claim 16, wherein said negative voltage is approximately -3 V so as to reduce the field below breakdown and thus eliminate any disturbance.
18. A method as claimed in Claim 10, wherein said source regions are allowed to float during flash program¬ ming.
19. A method for bulk (or byte) charging and flash erasing an array of flash EEPROM memory cells, said memory cells being formed on a substrate to define columns and rows, where the substrate includes the common source line extending along at least one of the rows, common substrate line, and a plurality of bit lines extending along respective columns, where each memory cell includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines, said method comprising the bulk (or byte) charging steps of:
applying a negative voltage to the sub¬ strate of the array;
applying simultaneously a reference voltage of zero volts to the drain regions of selected memory cells in the array that are to be programmed;
applying simultaneously the same reference voltage of zero volts to the control gates of the selected memory cells;
said method further including the flash erasing steps of applying a positive voltage the same magnitude as said substrate voltage during flash programming to the drain regions of the array; and applying the zero volts the same as that of said drain region during flash programming to the control gate and substrates of the array, said source regions being allowed to float during erasure.
20. A method as claimed in Claim 19, further includes the step of applying a programming-inhibiting voltage of a polarity magnitude the same as the substrate voltage to the control gates of non-selected memory cells in the array which are not to be programmed during said flash programming operations so as to insure against a disturbance.
21. A method for bulk (or byte) charging an array of flash EEPROM memory cells, said memory cells being formed on a substrate to define columns and rows, where the substrate includes the common source line extending along at least one of the rows, common substrate line, and a plurality of bit lines extending along respective columns, where each memory cell includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines, said method comprising the bulk (or byte) charging steps of:
applying a reference voltage of zero volts to the substrate of the array;
applying simultaneously a positive voltage to the drain regions of selected memory cells in the array that are to be programmed; and
applying simultaneously the same positive voltage to the control gates of the selected memory cells, said source regions being allowed to float.
22. A method for bulk (or byte) charging an array of flash EEPROM memory cells, said memory cells being formed on a substrate to define columns and rows, where the substrate includes the common source line extending along at least one of the rows, common substrate line, and a plurality of bit lines extending along respective columns, where each memory cell includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines, said method comprising the bulk (or byte) charging steps of:
applying a reference voltage of zero volts to the substrate of the array;
applying simultaneously a positive voltage to the source regions of selected memory cells in the array that are to be programmed; and
applying simultaneously the same positive voltage to the control gates of the selected memory cells, said drain regions being allowed to float .
23. A method for bulk (or byte) discharging an array of flash EEPROM memory cells, said memory cells being formed on a substrate to define columns and rows, where the substrate includes the common source line extending along at least one of the rows, common substrate line, and a plurality of bit lines extending along respective columns, where each memory cell includes an n-type source region coupled to the common source line, a control gate, a floating gate, a channel region, and an n-type drain region coupled to a respective one of the bit lines, said method comprising the bulk (or byte) discharging steps of:
applying a low negative voltage to the substrate of the array;
applying simultaneously an intermediate positive voltage to the drain regions of selected memory cells in the array that are to be erased; and
applying simultaneously a reference voltage of zero volts to the control gates of the selected memory cells, said source regions being allowed to float.
PCT/US1995/016805 1995-02-24 1995-12-22 Flash programming of flash eeprom array WO1996026522A1 (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
EP95943963A EP0819308B1 (en) 1995-02-24 1995-12-22 Flash programming of flash eeprom array
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US5491657A (en) 1996-02-13
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