WO1996028880A2

WO1996028880A2 - Transponder for electronic identification system

Info

Publication number: WO1996028880A2
Application number: PCT/GB1996/000622
Authority: WO
Inventors: Jos Scheelen
Original assignee: British Technology Group Inter-Corporate Licensing Limited
Priority date: 1995-03-16
Filing date: 1996-03-15
Publication date: 1996-09-19
Also published as: KR19980702934A; AU5012196A; JPH11502072A; WO1996028880A3; GB9505350D0; KR19980702933A; WO1996028879A1; JPH11503296A; EP0815638A1; AU5012096A; EP0815637A1

Abstract

A passive transponder for an electronic identification system is implementable in CMOS on a single chip and comprises a power antenna (18) and a rectifier circuit (26) to extract power from radiation impinging on the transponder, and to supply it to a powder storage capacitor (24); a data receive antenna (20), and a circuit (28) to extract a data signal from radiation impinging on the transponder; a data transmit antenna (22) for transmitting a data output signal; and an EEPROM (62) to store data and supply a signal to the antenna (22) which identifies the transponder.

Description

TRANSPONDER FOR ELECTRONIC IDENTIFICATION SYSTEM This invention relates to electronic identification systems, and more especially to systems comprising an interrogator and one or more non-contact transponders, and to circuits having applications in such systems and in other systems.

Electronic identification systems may be used for security purposes, for example to peπnit authorised persons carrying a transponder to pass through a checkpoint, or may be used to identify an article to which a transponder is attached, for example an item in a supermarket, especially in a loaded supermarket trolley passing through a checkout; or may be used to identify individual containers of sorted material for recycling or other waste collection system. In such systems, the transponders are often passive transponders which receive a power signal and an interrogation signal radiated from the interrogator, and in response generate and radiate a response communication signal. Often the radiating means in the interrogator and the signal receiving/radiating means in the transponder comprise resonant LC circuits, the data comprising a modulation applied to the resonant frequency. This invention in its first aspect relates especially to a passive resonant transponder for use in such a system, which will be referred to as a passive transponder of the type specified. The system may also comprise an interrogator as described in our copending patent applications Nos. 9508600.5 filed on 27 April 1995 and 9511085.4 filed on 1 June 1995. A known type of passive transponder, an information card, is disclosed in

EP 0336432, Toppan Printing Company Limited. The transponder has three external coils on a circuit board which in operation must be placed adjacent corresponding coils in a terminal unit.

Another known type of passive transponder, a computerised transaction card, is disclosed in WO 86/04705, American Telephone & Telegraph Company, and again the three coils must be positioned adjacent corresponding coils in a receptor for the card to operate. In an alternative passive transponder electronic detection system, described for example in European Patent Application Publication Number 0 598 624 Al, CSIR, an interrogator radiates a fixed-frequency signal, and a transponder identifies itself by applying modulations to a signal at that fixed frequency. This will be referred to as the Frequency-Back mode.

In a Frequency-Back system, the signalling rate is substantially higher than with a system operating on changes of Q factor. However, the Frequency-Back mode can only be used over a limited range of distance between the interrogator and the transponder.

In the present invention in its first aspect, positioning in correspondence with receptor coils is not necessary, the transponder can operate at a substantial distance from the interrogator disclosed in our copending applications referred to above. This advantage is the result of use of an inventive rectification circuit, see our copending divisional application No. [ ].

In the present invention in its first aspect, operation at a substantial distance from an interrogator circuit is possible, and in these circumstances it is advantageous to provide a local clock oscillator.

This invention in its second aspect relates to a local clock oscillator operating as a zero-cross detector circuit, for use for example on a passive transponder. A zero-cross detector circuit is disclosed in EP 0590303, Siemens, but the circuit uses a greater number of a different type of transistor to the inventive circuit. Another zero-cross detector circuit is disclosed in EP 0 367 981, Telefunken, but the circuit is not based on transistor pairs. A result of the provision of a local clock oscillator is that the clock signal and the data signal may be out of phase by 90°.

This invention in its third aspect relates to a circuit to apply a 90" phase shift to a signal such as a clocked data signal; use of such a circuit in a passive transponder permits the use of a Schmitt trigger for the extraction of amplitude-modulated data even when the output signal is 90" out of phase with a clock signal, and without the need for high frequency sampling with the need to supply considerable power to the transponder. Circuits relating to the detection of frequency and phase are disclosed in US 4773085 Cordell, US 4876699 Nelson, and US 4380083 Andersson, but the prior art circuits are different in operation and effect to the inventive circuit.

This invention in its fourth aspect relates to a passive transponder having a single antenna coil for power reception and data reception and data transmission; a disadvantage of such an arrangement is that the connection of circuitry to the single coil, and the use of a fullwave rectifier, results in high power consumption, and the risk of power leakage; and the fourth inventive aspect provides a circuit to overcome such disadvantages.

According to a first aspect of the invention, a passive transponder of the type specified comprises a power antenna and means to extract a power signal from radiation impinging on the transponder; power storage means for storing extracted power and supplying it to operate the transponder; a data receive antenna and means to extract a data input signal from radiation impinging on the transponder; a data transmit antenna for transmitting a data output signal; and data storage means responsive to a data input signal which supplies a data output signal to the data transmit means, the data output signal identifying the transponder.

It is an advantage of a passive resonant transponder according to the first aspect of the invention that it can be implemented in CMOS on a single semiconductor chip.

Preferably the data storage means is also responsive to a data input signal so as to record an initial or updated response signal.

The power antenna, data receive antenna and data transmit antenna may each comprise a coil forming part of a resonant LC circuit, in which case the power antenna coil will have a number of turns greater than the number of turns in the data receive and data transmit antenna coils, for example by a factor of 2; the data transmit coil will have a number of turns greater than the number of turns in the data receive coil, for example by a factor of 2.

Preferably the coils comprising the power antenna, data receive antenna and data transmit antenna are all provided in the form of embedded coils on an integrated circuit formed in CMOS technology; each coil may either be in the form of a coil surrounding the core of the respective part of the integrated circuit, or may be in the form of a coil deposited on top of the passivation layer of the CMOS circuit.

Optionally the coils for each antenna comprise at least one pair of "pancake" coils, that is coils having a planar spiral form, with the spirals of each pair of coils being of opposite hand.

Also according to the invention there is provided means associated with the data transmit antenna arranged so that the Q factor of that antenna is varied in a characteristic manner. Also according to an important feature of the invention, there is further provided in the transponder a calibration circuit arranged to supply calibration signals to the transmit antenna, and means to indicate when the power received by the power antenna reaches predetermined maximum and minimum power levels. The maximum and πώimum levels determine the preferred received power range for the particular distance of the transponder from its interrogator; the interrogator may vary the radiated power accordingly for efficient operation of the transponder.

Preferably there is further provided means to indicate the preferred frequency of operation of the transponder; the interrogator may then vary the radiated power signal and its frequency accordingly. Preferably the calibration circuit supplies a calibration signal to the transmit antenna in accordance with the power requirement of the transponder for its mode of operation; the interrogator may then vary the radiated power and optionally the frequency in accordance with the transponder's different power requirements for

(a) output of a calibration signal; (b) the extraction of a data input signal from radiation impinging on the data receive antenna and interpretation of that signal; and

(c) the output of a data output signal by the data transmit antenna.

It is a feature of a passive transponder according to the invention that the Q factor of the data transmit antenna is broad and flat; this is in contrast to the narrow and sharp Q factors of the combined data transmit/receive antennae previously provided in passive resonant transponders. Since the frequency of operation of the transponder is also variable, it is therefore essential that the associated interrogator has extremely precise signal analysis facilities; preferably a digital signal analyser is provided.

It will be apparent that, since the frequency of the power signal supplied to the transponder according to the invention can be varied, a local clock signal must be supplied.

While a conventional solution would be to use a Schmitt trigger circuit, such a circuit has a fixed trigger level which cannot operate in a passive transponder because the input signal may contain amplitude-modulated data, and the input signal may be weak.

According to a second aspect of the invention, a zero-cross detector circuit comprises two N channel transistors arranged as the inputs of a comparator circuit; a high impedance resistance divider which provides a reference voltage for the current source; and a current output circuit connected to each N channel transistor. Such a zero-cross detector circuit may be connected to the secondary coil of the data receive antenna in a passive transponder according to the first aspect of the invention, but also has other applications. Preferably there is also provided a follower circuit/transistor connected to each current output circuit, from which a stable clock signal can be provided corresponding to the polarity change of the clock signal received by the data receive antenna.

As stated above, it is an advantage of a passive transponder according to the first aspect of the invention that it can be implemented in CMOS technology. However the power supplied to the power antenna is in a.c. form, which requires rectification. Conventionally, rectification is provided by use of diodes, but diodes do not exist in CMOS form. Further, the voltage level must be limited to avoid damage to the CMOS circuitry, which can operate at a maximum of 40 volts, and often at a much lower maximum voltage, for example 5 volts. Preferably the transponder according to the first aspect of the invention is provided with a CMOS integrated full wave rectifier comprising a first pair of transistors arranged to switch on opposing half cycles, and a second pair of transistors arranged in current limiting mode which also operate on opposing half cycles. Preferably the transistors are all N channel transistors with the first pair having their gates connected to receive opposing half cycles of an a.c. input signal, and with the second pair connected in common drain mode.

Preferably there is also provided a voltage limiter circuit connected to the aforesaid full wave rectifier comprising a depletion transistor arranged to connect the gates of the current limiter transistors to ground when the voltage applied by the secondary coil exceeds a predetermined level.

It is an advantage of a CMOS full wave rectifier and voltage limiter according to this further invention that an integrated circuit can be connected through such circuitry to mains voltage without the need for a transformer. Such a rectifier may be used in a passive transponder according to the first aspect of the invention but has many other applications.

Referring once again to a passive transponder, in some arrangements the information received by the data receive antenna will be in amplitude-modulated form. It is an advantage of a transponder according to the invention that its operating distance from an interrogator need not be closely fixed, but a resultant disadvantage is that phase information cannot be extracted from the received data.

Optionally there is provided a passive transponder according to the first aspect of the invention and also comprising a CMOS integrated full wave rectifier and an associated voltage limiting circuit together capable of receiving an amplitude modulated signal on the data receive antenna, in which said depletion transistor is connected to a Schmitt trigger circuit whose output thereby comprises a data signal containing amplitude modulated information.

However in a passive transponder having a zero cross detector to provide a clock signal and a Schmitt trigger to permit extraction of amplitude modulated data from the signal received by the data receive antenna, the output signal from the Schmitt trigger is 90° out of phase with the clock signal.

A conventional solution would be to use high frequency sampling, but such sampling requires considerable power and a major object of the present invention is to limit the power consumption of the transponder. According to a third aspect of the present invention, there is further provided means to apply a 90° phase shift to a signal such as a clocked data signal said means comprising a combination of three AND gates, an OR gate and an inverter through which clock and data signals are supplied to a set-reset flipflop having a preferred resettable state; and first and second "D" latches in series supplied with the output of the flipflop and direct and inverted clock signals; the arrangement being such that the output of the flipflop is either 0 or a previous state, and the output of the second latch comprises the data signal read on the rising edge of the clock signal after a delay of two data cycles, whereby a 90° phase shift is applied. Such phase shifting means may be used in a passive transponder according to the first aspect of the invention.

In a fourth aspect of the invention, a passive responder of the type specified comprises a single antenna for power and data reception and data transmission, there being further provided at least one pair of depletion transistors each connected between one side of the antenna secondary coil and one side of an inverter circuit. In such an arrangement, a square wave input is converted to a burst frequency output signal.

It may however be the case that the transponder is too far from its interrogator for the output burst signal to be detected. Optionally there is further provided an oscillator circuit arranged to switch a signal burst at a frequency which is high in comparison with the frequency of the square wave input. A passive transponder according to the first aspect of the invention operating on variation of Q factor may also be used in association with a circuit of a complementary type, such as a frequency-back circuit, one of the circuits being activated in accordance with current conditions, such as the distance between the transponders and an associated interrogator, or the available stored power. The invention will now be described by way of example only with reference to the accompanying drawings in which:-

Figure 1 is a schematic diagram of an electronic identification system,

Figure 2 is a more detailed diagram of such a system,

Figure 3 illustrates in more detail a part of the transponder of Figure 2, Figure 4 illustrates a system having an additional calibration circuit, and Figures 4b and 4c illustrate the effect of two optional modes of operation,

Figure 5 illustrates the varying energy and frequency requirements of a transponder of the type specified when operating in different modes, Figure 6 illustrates a part of the integrated circuit which provides a local clock oscillator for the transponder operating on the zero cross principle,

Figure 7(a) illustrates a solid state full wave rectifier and over voltage protection circuit which can be implemented in CMOS technology,

Figures 7(b) and 7(c) illustrate the voltage cycles at various parts of the circuit of Figure 7(a),

Figures 7(d) and 7(e) illustrate the relative voltage magnitudes during operation of the circuits of Figure 7(a),

Figure 8 illustrates a circuit permitting extraction of amplitude modulated data,

Figure 9 illustrates clock and input signals of a transponder according to the invention,

Figure 10(a) illustrates a circuit to apply a 90° phase shift to a clock signal,

Figures 10(b) and 10(c) are timing diagrams for, respectively, data low and data high inputs to the circuit of Figure 10(a),

Figure 11 illustrates a capacitor coupled feedback signal for a passive transponder, Figure 12 illustrates the signals on parts of the Figure 11 circuit,

Figure 13 illustrates the full integrated circuit for a passive transponder according to the invention,

Figure 14 illustrates use of an electronic identification system according to the invention in combination with a complementary detection system. Figure 1 illustrates an electronic identification system comprising an interrogator 10 and a passive transponder 12. The interrogator transmits power to the transponder, as indicated at 14, for example at 150 to 250 kHz, and the transponder utilises the power to transmit an identification signal 16, for example at a few hundred MHz, modulated by amplitude, frequency or phase, the modulation being introduced by known techniques. Figure 2 shows in more detail a transponder 12 according to a first aspect of the invention. The transponder has three antennae 18, 20, 22, each in the form of an LC circuit; antenna 18 comprises a power antenna; antenna 20 comprises a data receive antenna; and antenna 22 comprises a data transmit antenna. Typically the number of windings in the respective coils of antennae 18, 20 and 22 is 120:30:60.

The power antenna 18 is connected to a power storage capacitor 24 through a full wave rectification circuit 26; the circuit 26 is indicated here by four diodes and will be described in more detail subsequently with reference to Figure 7.

The data receive antenna 20 is connected to a data input circuit 28, and the data transmit antenna 22 is connected to a data output circuit 30. All four integers are supplied with power from the power capacitor 24 and, as illustrated, the capacitor 24 and the data input and output circuits 28, 30 are formed as an integrated circuit (i.e.) 32.

Figure 2 also indicates part of the interrogator 10 having a transmitting antenna 34 connected to an i.e. 36 connected by a conventional serial or parallel data line 38 to signal processing circuitry (not shown).

In operation, antenna 34 radiates an alternating magnetic field which induces energy in the coils of all three antennae 18, 20, 22; as power antenna 18 contains substantially the largest number of coils, it receives the largest amount of energy which is rectified by circuit 26 and stored by capacitor 24 which then acts as the power source for all components of the transponder 12.

The data receive antenna 20 receives a smaller amount of energy, and the modulated signal is interpreted by its associated circuit 28. In data transmit mode, the circuit 30 provides a modulated identification signal which is transmitted by data transmit antenna 22 and received by antenna 34, then decoded to identify the transponder 12. In the interrogator 10, the integrated circuit 36 comprises a microprocessor 40 connected through a data line interface 42 to the data line 38 and to a data buffer 44; buffer 44 is connected to a digital signal analysing unit 46 which in turn is connected through an output transmitter 48 to the microprocessor 40 and to one side of antenna 34; there is also provided an integrated local oscillator 49 connected to the other side of the antenna 34. In operation, data received from data line 38 for transmission by antenna 34, or data received by antenna 34, are stored in buffer 44; for data transmission, the antenna 34 is modulated accordingly; data received is analysed by digital signal analysis unit 46.

The type of signals which may be transmitted and received by the apparatus shown in Figure 2 will be clarified with reference to Figure 3 which shows in more detail the data receive unit 28 and the data transmit unit 30.

The data receive unit 28 comprises a local clock oscillator 50 connected through a digital phase locked loop (PLL) 52 to a Manchester decoder 54 which supplies a signal to a processor 56. The PLL 52 is also connected to an input buffer 58, and there is provided an output buffer 60, and a local memory 62. The whole circuit is implemented in CMOS.

In operation, data received by the input buffer 58 from the antenna 20 (Figure 2) is clocked by local oscillator 50 at a frequency depending on the frequency of the data signal; the PLL 52 regulates the frequency and supplies an error code indicating frequency variations to the Manchester decoder 54; the decoded data is processed by processor 56 which, in response, executes certain functions on the chip 28 or returns certain predetermined data based on the contents of the local memory 62 via output buffer 60 to the data output unit 30 (Figure 2).

The local memory 62 is of a non- volatile type such that it retains data in the absence of an external power supply, that is, when the passive transponder 12 carrying it is not in the vicinity of an interrogator 10. Typically the stored data will indicate the identity of the carrier of the transponder, such as the type and price of goods in a supermarket, or the identity of a person carrying the transponder and possibly their associated level of e.g. authorisation to permit physical or electronic access.

It is an advantage of the transponder according to the invention that an input signal can be received which causes the contents of the local memory to be updated, e.g. by a price change for supermarket goods, or by initially loading the price. Such a change can be implemented during a write cycle signalled via antenna 20, and a subsequent read cycle would supply the updated information through antenna 22.

In a further application, transponders may be attached one to each of a number of containers for sorted recyclable waste collection supplied to a householder, and the interrogator is carried by a collection vehicle; on collection, the containers are individually weighed and the weight of the contents written into the transponder and into a store on the

vehicle; from the records, a monthly invoice for collected material can be issued to the householder.

Reference has previously been made to the ratio of the number of coils on the antennae 18, 20, 22 in Figure 1. In prior art arrangements it has been necessary to provide a power coil equivalent to antenna 18 with, say, 300 turns. In a transponder according to the invention having separate data receive and data transmit coils, and implemented in CMOS, a power antenna with 120 turns will be sufficient to power the chip, such power being supplied as a frequency between 150 and 250 kHz.

Antennae of such a low number of coils have inevitably a broad, flat Q factor. One arrangement for providing a data transmit signal will now be described also with reference to Figure 3. The output buffer 60 of data input circuit 28 is connected to the output logic part 64 of the output circuit 30. The part 64 codes the data to be output by modulating it in accordance with a Manchester protocol plus some additional control bits. Each logical level is arranged to open or close a switch 66 connected across data output antenna 22, and the circuit components are provided in CMOS form.

The effect of opening and closing switch 66 is to short a part of the coil of antenna 22 which varies the Q factor of the four-antenna system; the circuitry in interrogator 10 is arranged to detect such Q factor changes, and to interpret them as information relating to the transponder, e.g. the price of a supermarket article. Since the Q factor is broad and flat, it is essential therefore to use a digital signal analyser 46 in the interrogator 10.

As stated above, the major parts of the transponder can be implemented in CMOS, including the coils of antennae 18, 20, 22. Such coils may themselves be implemented in CMOS and surround the relevant active area of the integrated circuit. Such a coil is provided at the same time as the remainder of the integrated circuit is processed. Since the number of windings required for each antenna is small, the required area of silicon covered is not excessive, and can be as little as 1 square millimetre for a 350 nano Harvey coil. Alternatively the coils may be laid down on top of the passivation layer applied to the integrated circuit, using a known technique. A disadvantage of a coil surrounding an area of the integrated circuit is that the magnetic flux may pass through the active part of the chip, inducing unwanted current into the small metal parts it carries and thereby causing instability.

In a variation, the windings for each antenna 18, 20, 22 are provided as a pair of planar coils wound in opposite directions, known as "pancake" coils. Optionally each winding comprises a substantial number of pairs of coils, e.g. 30 or 40, placed outside the active parts of the chip, usually in a bonding area. In such an arrangement, unwanted currents are not induced into the active parts of the chip.

In such coils, the metal of the coil winding may be of the order 4 microns in width with the coils separated from each other by about 2 microns.

In an electronic identification system according to the invention in use, the distance between the interrogator and the transponder may vary substantially, for example when the transponder is attached to an article in a supermarket trolley, and indicates its price to an interrogator at a checkpoint. In prior art passive transponders, it is often essential for the distance of the transponder from the interrogator to be held within narrow limits so that the system can operate at a fixed level of transmitted energy; if the transponder approaches the interrogator too closely, the energy received by the power antenna is too high and the coil saturates. One solution is to provide a voltage limiter circuit to consume current and avoid coil saturation, but there is still a risk of the consuming current causing coil saturation. In practical situations it is preferable for the transponder 12 to be capable of operation at a variable distance from its interrogator 10.

A circuit permitting such a variable distance of operation is illustrated in Figure 4. In Figure 4a, the interrogator 10 is provided with a control circuit 74 connected to means 78 to vary the power supplied to antenna 34 in its transmitting mode, indicated schematically as 34T. The receiving mode of antenna 34 is indicated schematically as 34R. (It is emphasized that a single antenna 34 is physically present.) The transponder 12 is provided with a calibration circuit 72 connected to the data receive antenna 20, and variable received power on power antenna 18 is indicated at 70. The control circuit 74 is arranged to provide maximum power to antenna 34T at start-up and, optionally, at other times during a detection process. Depending on the distance of the transponder 12 from the interrogator 10, the power received by power antenna 18 may be so high that the coil of antenna 34 in receive mode 34R is saturated; in such circumstances, the signal from calibration circuit 72 does not reach the control circuit 74; the control circuit 74 then operates to reduce the output power to a level at which it receives a signal from the calibration circuit 72, and records the associated power output; circuit 72 continues to reduce the power output until the received power is so low that calibration circuit 72 ceases to operate. Control circuit 74 then records the associated power output. Circuit 74 now has a record of the power band within which transponder 12 can operate effectively at its particular distance from the interrogator 10, and controls the output power accordingly.

The power variations are illustrated in Figure 4b, which shows the maximum energy level received and the preferred operating band of energy levels between PI and P2; above and below these levels the transponder is inoperable for this particular distance between it and the interrogator 12. Setting the preferred power band allows power output to be minimised while maintaining the function of the transponder. In effect the normal operating power band is ascertained.

In a variation, control circuit 74 varies both power output and the frequency of operation of antenna 34; a plot of the preferred ranges of power and frequency is illustrated in Figure 4c. In use, the power and frequency requirements of a transponder vary not only with distance from the interrogator 12 but also depend on the operation being performed by the transponder 12. Reference is made above to reception of a "write" signal, either to load or to update information relating to the article identified by the transponder. Subsequently, this information is read out, and provision of the "read" signal may require substantially less energy than reception and application of the "write" signal. Further, the provision of a calibration signal as described above may require a third, intermediate, level of energy consumption.

The energy and frequency requirements of the transponder operating in these three modes are illustrated in Figure 5. At power-up, high energy and high frequency are provided (Figure 4c); the power capacitor 24 is loaded, and it is in this mode that the local memory 62 (Figure 3) is initially loaded to indicate e.g. price of an article; usually the local memory 62 is an

EEPROM and substantial power is required to write into it, as indicated by the highest energy level in Figure 5.

The EEPROM 62 is conventionally read out in two steps; first the command to read out, received via the data receive antenna 20 and its associated circuit 28, is interpreted by circuit 28; the information is written from EEPROM 62 to the output buffer 60, an operation requiring a substantial energy level. The EEPROM 62 can then be powered down and the data in buffer 60 provided to output antenna 22 with the chip requiring a substantially lower level of energy in this mode. During this operation, capacitor 24 is feeding the circuitry of transponder 12, and the next operation is to power up again in calibration mode, as shown in Figure 5. The power required in calibration mode is however less than that required in the write mode to the EEPROM. It will be apparent from the description of a passive transponder provided above that in some circumstances the transponder will be transmitting data information when it is not receiving a power input, when the energy available for the capacitor 24 is low or even zero, e.g. when the transponder is far from the interrogator. To permit the interrogator to detect such data, a local clock oscillator (indicated at 50 in Figture 2) is essential, triggered by the clock signal previously transmitted by the interrogator to the transponder.

A circuit to provide an appropriate local clock signal is illustrated in Figure 6, and operates as a zero cross detector. It is in paired transistor form.

The ends of the secondary coil 20a of data receive antenna 20 are connected one to the gate of each of two N channel transistors 80, 82. These two transistors provide the input of a comparator circuit comprising the transistors 84, 86, and 88, 90. Power capacitor 24 of the transponder 12 is connected across two transistors 92, 94 arranged as a high impedance divider and supplying the divided voltage to the gate of a transistor 96 which act as a current source.

The outputs of the comparator circuit are connected one to each of the transistors 98, 100, which comprise the output circuits. In one half cycle of the clock oscillation received from coil 20, current in the circuit flows through the transistors 84 and 80 to 96, and in the other half cycle current flows through the mirror image path. Since all transistor pairs are of equal value, one of the transistors 80, 82 must switch on or very close to the zero cross of the received clock signal, i.e. whenever its polarity changes.

The transistors 86, 90 follow transistors 84, 88 by reason of the gate connections, and could provide a clock output, but the use of transistors 98, 100 permits current balancing and provides a more stable clock.

As explained above, it is a major feature of a transponder according to the invention that it can be implemented in CMOS. The power supplied to the power antenna 18 is a.c, which must be rectified. Conventionally, diodes are used for rectification, but diodes cannot be implemented in CMOS. Further, CMOS technology operates only at low voltages, usually at selected values between 3.3 and 40 volts, frequently at 5 volts. If a higher voltage is received by the IC, it will be seriously damaged. This can easily occur as the distance from the interrogator 10 to the transponder 12 can vary considerably in practical use. A voltage limiter is therefore required.

A suitable circuit providing both of these functions and capable of implementation in CMOS is illustrated in Figure 7. The application of this circuit is not limited to an electronic detection system of the type specified and the circuit may be used in any CMOS chip requiring rectification and embedded over-voltage protection. It may have application also in any i.e. technology in which diodes cannot be provided.

In Figure 7a, a full wave rectifier (shown schematically in Figure 2 at reference 26) can be implemented in CMOS. It comprises four N channel transistors 102, 104, 106, 108 substituted for the diodes of the bridge 26. Transistors 104, 106 have their gates connected to opposite ends of the secondary winding 18a of power antenna 18 and therefore act as switches. Transistors 102, 108 are connected in common drain mode. The four transistors together form a rectifier circuit.

In one half cycle, e.g. when the left hand side of coil 18a is positive, current flows through transistor 102 to one side of power capacitor 24; current cannot pass through transistor 104 because the voltage on its gate keeps it closed, while transistor 106 is open; power capacitor 24 therefore receives charging current. In the other half cycle, a mirror image arrangement applies.

The voltage variations are shown in Figure 7(b); the loading voltage V_]oacj applied to capacitor 24 is initially high, then rapidly reduces as the capacitor charges up, as shown by cha_j-p_g. The voltage difference V_jjg- between the gates of transistors 104 and 108 is cyclical, and on start-up quickly reaches stability.

As is well known, CMOS technology is voltage sensitive, and voltage limiting means must be introduced. The circuit therefore comprises additional transistor pairs 112, 114, and 118, 120, one pair being connected to each end of the coil 18a, and the transistors 114, 120 being also connected in common drain mode. The gates of transistors 112, 118 are supplied from a transistor of opposite type, i.e. a P channel transistor, 110, whose gate is supplied with a reference voltage

The arrangement is such that when the voltage from coil 18a is too high for the CMOS components, transistor pairs 112, 114 or 118, 120, operating on opposite half cycles, short the current from the coil to the substrate, indicated as reference 116. The required relative magnitudes of is

shown in Figure 7(c).

Setting the gate voltages is critical. For operation at start-up mode, i.e. before power capacitor 24 is loaded so that no local power is available, a depletion transistor 124 is provided, connected to the gates of transistors 112 and 118. In one half cycle, transistor 112 is connected to substrate 116 through depletion transistor 124, and the rectifier circuit is protected. In the opposite half cycle, transistor 118 operates in similar fashion.

The relative changes of the voltages and currents at various parts of the circuit are shown in Figure 7(d).

The voltage on transistor 102 is initially zero, then increases to about 6 volts. The voltage V _{j j}2 ^{on e} 8^ate of transistor 118 is initially zero, then after a delay increases to about 2 volts, so that the transistor then operates, causing the current through transistor 118 to reduce, when all current passes into the current limiting circuit and none into the capacitor 24, shown by coincidence of the drain current and the total current of 112; the current limiter circuit is now in full operation, while capacitor 24 (IC_joacj) holds a stable voltage Vι_oacj, providing a stable reference voltage V_ref.

Figure 7(e) shows the voltages on the various transistors of the circuit, i.e. on the gates of transistors 104 and 108, the reference voltage, the voltage on the drain of 120, and on the gate of 112; the voltage on transistor 112 indicates operation of the current limiting circuit, when the voltage is sufficient to operate it.

The characteristics of the various transistors will be determined by the expected voltage from the secondary coil 18a and the maximum current the CMOS circuit can tolerate. If the resistance of the secondary coil 18a is too low, an additional resistor

(not shown) may be connected in series with it, and is preferably manufactured from polycrystalline silicon.

Reference has been made to the fact that an electronic identification system according to a first aspect of the invention can advantageously operate with a range of distances between the interrogator 10 and the transponder 12. If however the system is operating on amplitude modulated data, phase information may not be received by the data input circuit 28.

A solution to this difficulty will now be described with reference to Figure 8. When amplitude modulation is used in the data receive signal, the reference voltage VRef from P channel transistor 110 is connected to ground so that the signal level is never zero. The result is that if the voltage applied to transistor 120 by the secondary coil 18a exceeds a selected voltage, such as 3.6 volts, that transistor switches. If the output of the depletion transistor 124 is supplied to a conventional Schmitt trigger circuit 126, which may be implemented in CMOS, then the output of the trigger circuit relates to the amplitude modulated (AM) data and can be analysed by data input circuit 28.

In such an arrangement, the inverse signal received by coil 18 is rectified, which results in double data information about the received clock frequency, from both half cycles of the signal.

However the extracted clock signal and the AM data signal are now 90° out of phase, so that circuit 28 cannot directly process the information. The effect is illustrated in Figure 9 which shows the squarewave clock signal C received from the zero cross detector (Figure 6) and the sinewave signal data input signal I, shown to have a varying magnitude. The trigger level S of the Schmitt trigger circuit is also indicated.

When the magnitude of the data signal I equals the Schmitt trigger level S, it is 90° out of phase with the clock signal C. A high frequency sampling technique cannot be applied because it would increase the power consumption substantially. An alternative technique, in which the clock frequency is shifted by 90°, is illustrated in Figure 10; this technique permits optimal synchronisation of the clock and data signals.

The circuit illustrated in Figure 10(a) combines an asynchronous clock and an asynchronous clock circuit, an extremely unusual combination; in fact it is the practice in some electronics companies to forbid the use of asynchronous clocks.

Although the circuit is described here in use in the transponder of an electronic identification system, it has applications in any circuit, especially any integrated circuit, in which a 90" phase shift is required at very low power consumption. The local clock signal (see Figure 6) is supplied through connection 152 to one input of an AND gate 154 and via an inverter 156 to one input of each of two further AND gates 158, 160. The data signal (see Figure 8) is supplied through connection 150 to the other input of each of AND gates 154, 158.

The output of gate 154 forms one input of OR gate 162, the other input coming from gate 160. The output of gate 162 forms the reset input of a set-reset flipflop 164, which has a preferred resettable state, and whose set input is derived from gate 158. The output Q of flipflop 164 supplies a first "D" latch 166, the output of which supplies both a second "D" latch 168 and the second input of AND gate 160. The "D" latches are positive triggered. The clock inputs to the "D" latches are supplied from connection 152, directly in the case of the first latch 166, and after passage through the inverter 156 for the second latch 168.

Because the clock is not tied, the data signal must be stable when the clock is changing, i.e. on the clock rising or falling edge. The behaviour of the circuit is illustrated in the timing diagram of Figure 10(b), which illustrates the waveforms on the circuit components when the data signal on connector 150 is low, and in Figure 10(c), for a high data signal.

The duty cycle of the data signal depends on the level of the Schmitt trigger circuit (Figures 8 and 9) . The data must be synchronised not on the zero level but after a 90° shift, which gives optimal synchronisation.

In a further variation of an electronic identification system according to the invention, instead of using separate data receive and data transmit antennae 20, 22 as shown in Figure 2, a combined power/receive/transmit antenna can be used. In such an arrangement, a direct connection of the circuitry to the combined coil, in combination with use of a full wave rectifier as illustrated in Figure 7, results in high power consumption. If there is no data output, there is no leakage of power capacitor 24, but connection of a transistor circuit to the coil causes leakage.

A solution is illustrated in Figure 11. Antenna 128 is equivalent to a combination of power, data receive and data transmit antennae 18, 20, 22 in Figure 2. Respective ends of its secondary winding 128a are connected through three pairs of depletion transistors 130, 132 to the input and output of an inverter circuit 136. Each depletion transistor is equivalent in use to a capacitor of a stacked construction with metal 1 and metal 2 and an N channel transistor placed in an N-well, and connected on one side to the gate of the transistor and on the other side as a shorted source-drain connection. The depletion transistors are therefore used in a mode which is contrary to conventional circuit design rules; they act as capacitors, not transistors.

Feedback to the depletion transistors 130, 132 is provided from a Schmitt trigger circuit 138 and NAND circuit 140 by which a burst of frequency can be generated, provided the energy level of the data signal is above a certain level - the energy of a spike signal is too low for detection. The oscillation frequency of the burst signal can for example be 200 to 400 MHz. This signal is transmitted through the transistors 130, 132, and the coil 128a, which has a 50% duty cycle on that frequency.

The effect is illustrated in Figure 12. Figure 12(a) shows the output of the upper half of the circuit in Figure 11, and Figure 12(b) shows the output of the circuit in the lower half. The square wave input data I is integrated because the capacity values of the depletion transistors 130, 132 are limited - this is a result of use of CMOS technology. The capacitors may for example have a value of 1 pF. The result is a burst output signal O which is applied to the coil 128a as a data transmit circuit; if there is a high frequency signal e.g. at 100 megahertz, the radiation can be received by the interrogator 10 even when there is a considerable distance between it and the transponder 12.

A disadvantage is that the NAND-Schmitt trigger circuits 140, 138 consume a substantial current, but the advantage is a high output field.

Figure 12b illustrates a plot of a typical current injection the coil 34. Figure 13 illustrates the entire CMOS i.e. carried by a transponder according to the invention.

In all versions of the electronic detection system described so far, data transmission has been on the basis of varying the Q factor of the system, which requires a very precise interrogator circuit. Also, the signalling rate available with variations of Q factor may in some circumstances be undesirably low.

In the alternative detection system known as a Frequency-Back system disclosed in EP 0 598 624, referred to above, the signalling rate is substantially higher than with a system operating on changes of Q factor. However, the Frequency-Back mode can only be used over a limited range of distance between the interrogator and the transponder. A system incorporating both modes of operation is illustrated schematically in

Figure 14(a) which illustrates a variation of the data output circuit of Figure 3. Figure 14(a) shows the data transmit antenna 22 connected through switch 66 to output logic 64 and EEPROM 62. The data output circuit 30 is also shown. In addition there is provided a Frequency Back mode circuit 180 incorporating an oscillator 182; the output circuit 30 is connected to both the switch 66 and the Frequency Back circuit 180, and operates so that either switch 66 or oscillator 182 is connected across the antenna 22.

The logic circuit 64 operates so that the switch 66, causing Q factor changes of the system, is connected to antenna 22 during power-up of the transponder. When a predetermined level of stored power is available, the circuit is switched to the Frequency Back mode circuit 180. This allows faster data transmission and greater operating distances, e.g. up to 4 or 5 metres, but a disadvantage is relatively high power consumption. When available power falls, the Q factor modulation of switch 66 is again operated.

The change of mode of operation can be programmed into the EEPROM 62, as two consecutive "l"s (Figure 14(b)).

Typical data rates are as follows; for Q factor changes, the transponder operates at about 250 kHz; data is sent in Manchester coding; the high time of the data is typically 10 cycles long, so the data rate output is less than 12 kHz.

In Frequency Back mode, the frequency is typically 200 MHz. Data will be sent under an asynchronous protocol as described with reference to Figure 10. Data is sent only during the high cycle of the clock and not on the zero cycle - see Figures 10(b) and 10(c); the overall cycle rate is approximately zero, but is less effective than Manchester coding.

The circuits providing a local clock oscillator, Figure 6, a CMOS rectifier, Figure 7, an extractor circuit for FM modulation, Figure 8, a 90° phase shift circuit, Figure 10, and a capacitor-coupled circuit, Figure 11 , may also find application in a Frequency Back mode system, as well as in many other circuits implemented in CMOS.

Claims

1. A passive transponder for an electronic identification system characterised by comprising:- a power antenna (18) and means (26) to extract a power signal from radiation impinging on said transponder; power storage means (24) for storing power and supplying it to operate the transponder; a data receive antenna (20) and means (28) to extract a data signal from radiation impinging on said transponder; a transmit antenna (22) for transmitting a data output signal, and data storage means (62) responsive to said data signal, said data storage means supplying a response signal to the data transmit antenna (22) which response signal identifies the transponder.

2. A passive transponder according to Claim 1 characterised in that said antennae and said data storage means are implemented on a single semiconductor chip.

3. A passive transponder according to Claim 2 characterised in that the single semiconductor chip is a CMOS chip.

4. A passive transponder according to Claim 1 characterised in that the data storage means (28, 30) is also responsive to a data input signal to record an initial or updated response signal.

5. A passive transponder according to Claim 1 characterised in that the power antenna (18), data receive antenna (20) and data transmit antenna (22) each comprise a coil forming part of a resonant LC circuit.

6. A passive transponder according to Claim 5 in which the power antenna coil (18) has a number of turns greater than the number of turns of the data receive antenna coil (20) or of the data transmit antenna coil (22).

7. A passive transponder according to Claim 6 in which the data transmit antenna coil (22) has a number of turns greater than the number of turns of the data receive antenna coil (20).

8. A passive transponder according to Claim 5 in which the coils comprising the power antenna (18), the data receive antenna (20) and the data transmit antenna (22) each comprise an embedded coil on an integrated circuit formed in CMOS technology.

9. A passive transponder according to Claim 8 characterised in that each said embedded coil (18, 20, 22) is arranged to surround the core of an associated part of the integrated circuit.

10. A passive transponder according to Claim 8 characterised in that each said embedded coil (18, 20, 22) is deposited on top of a passivation layer of said CMOS circuit.

11. A passive transponder according to Claim 5 characterised in that each of the power antenna (18), the data receive antenna (20) and the data transmit antenna (22) comprises at least one pair of pancake coils in planar spiral form with the spirals of each pair of coils being of opposite hand.

12. A passive transponder according to Claim 1 characterised in that the data receive antenna (20) is connected to a data receive unit (28) comprising a local clock oscillator (50) connected through a digital phase locked loop (52) to decoder means (54) which is connected through a processor (56) to an output buffer (60) and local non-volatile memory means (62).

13. A passive transponder according to Claim 1 characterised in that the data receive antenna (20) is connected to a local clock oscillator (50) arranged to be triggered by a clock signal previously received by the data receive antenna.

14. A passive transponder according to Claim 13 characterised in that the local clock oscillator comprises a zero-cross detector circuit having a pair of identical N channel transistors (80, 82) arranged as the inputs of a comparator circuit comprising two pairs of identical transistors arranged in opposition (84, 86 and 88, 90); and a high impedance resistance divider comprising a pair of identical transistors 92, 94 which provides a reference voltage for a current source (96); whereby one of the transistors (80, 82) switches whenever an input signal received by said transistors (80, 82) changes in polarity.

15. A passive transponder according to Claim 14 in which the zero-cross detector circuit further comprises a follower circuit comprising a pair of transistors (98, 100) connected as a current output circuit whereby a stable clock signal can be provided corresponding to the polarity change of an unstable clock signal input received by the detector circuit.

16. A passive transponder according to Claim 1 characterised in that there is provided in association with the data transmit antenna (22) means (64, 66) to vary the Q factor of said antenna.

17. A passive transponder according to Claim 16 characterised in that said means comprises output logic means (64) arranged to control switch means (66) connected across said data transmit antenna.

18. A passive transponder according to Claim 16 characterised by further comprising frequency-back circuit means (180, 182) arranged to apply modulations to a fixed-frequency received signal and connectable to the data transmit antenna (22); and logic means (64) arranged to connect the switch means (66) to the data transmit antenna (22) when power stored in the power storage capacitor (24) is below a predetermined level and to connect the frequency-back circuit means (180, 182) to the data transmit antenna when power stored in the power storage capacitor is above a predetermined level.

19. A passive transponder according to Claim 1 characterised in that the power antenna (18) is connected to a CMOS integrated full-wave rectifier comprising a first pair of transistors (104, 106) arranged to switch on opposing half cycles of an a.c. signal received by the power antenna, and a second pair of transistors (102, 108) arranged in current limiting mode and also operating on opposing half cycles of said signal.

20. A passive transponder according to Claim 19 characterised in that the transistors (102, 104, 106, 108) are all N channel transistors with the first pair ( 104, 106) having their gates connected to receive opposing half cycles of said a.c. input signal, and with the second pair (102, 108) connected in common drain mode.

21. A passive transponder according to Claim 20 characterised by further comprising a voltage limiter circuit comprising a third pair of transistors (112, 114), a fourth pair of transistors (118, 120) and a depletion transistor (124) arranged to connect the gates of the current limiter transistors (102, 108) to ground when the input voltage to the rectifier exceeds a predetermined level.

22. A passive transponder according to Claim 21 characterised in that the depletion transistor (124) is connected to a Schmitt trigger (126).

23. A passive transponder according to Claim 22 characterised in that the Schmitt trigger (126) is connected to means to apply a 90° phase shift to a local clock signal comprising in combination three AND gates (154, 158, 160), an OR gate (162) and an inverter (156) through which said local clock and said data signals are supplied to a set-reset flipflop (164) having a preferred resettable state; and first and second "D" latches (166, 168) in series supplied with the output of the flipflop and direct and inverted clock signals; the arrangement being such that the output of the flipflop (164) is either zero or a previous state, and the output of the second latch (168) comprises the data signal read on the rising edge of the clock signal after a delay of two data cycles, whereby a 90° phase shift is applied.

24. A passive transponder according to Claim 1 characterised in that the data receive antenna (20) is connected to calibration means (72) and the power receive antenna (18) is connected to power indication means (70), the calibration means (72) being arranged to provide an output signal only when the power received by the power antenna (18) is within a preset range.

25. A passive transponder for an electronic identification system characterised by comprising a single antenna (128) for power and data reception and data transmission, there being further provided at least one pair of depletion transistors (130, 132) each connected between one side of the antenna secondary coil (128a) and one side of an inverter circuit (136), whereby a square wave input is converted to a burst frequency output signal.

26. A passive transponder according to Claim 25 further comprising an oscillator circuit (138, 140) arranged to switch a signal burst at a frequency which is high in comparison with the frequency of the square wave input.

27. An electronic identification system characterised by comprising a passive transponder according to Claim 1 , and an interrogator comprising antenna means (34) to radiate an alternating magnetic field; means (38, 40, 42, 48) to supply data to the antenna means; and means (49) to receive an identification signal.

28. An electronic identification system characterised by comprising a passive transponder according to Claim 26, and an interrogator comprising antenna means (34) to radiate an alternating magnetic field; means (38, 40, 42, 48) to supply data to the antenna means; receiving means (34, 40, 44, 46) to receive a signal from the passive transponder (12); control circuit means (74); and power variation means (78), arranged so that the control circuit means varies the power supplied to the antenna means (34) in accordance with a signal received by the receiving means from the calibration circuit (72) whereby the power received by the power antenna (18) is maintained within a preset range.

29. An electronic identification system according to Claim 27 characterised in that the power supplied to the power antenna (18) is varied in energy level.

30. An electronic identification system according to Claim 27 in which the power supplied to the power antenna (18) is varied in energy level and in frequency.

31. An electronic identification system according to Claim 27 in which the power supplied to the power antenna (18) is varied in accordance with the operation being performed by the passive transponder (10).

32. A zero-cross detector circuit characterised by comprising a pair of identical N channel transistors (80, 82) arranged as the inputs of a comparator circuit comprising two pairs of identical transistors arranged in opposition (84, 86 and 88, 90); a high impedance resistance divider comprising a pair of identical transistors 92, 94 which provides a reference voltage for a current source (96); whereby one of the transistors (80, 82) switches whenever an input signal received by said transistors (80, 82) changes in polarity.

33. A zero cross detector circuit according to Claim 32 further comprising a follower circuit comprising a pair of transistors (98, 100) connected as a current output circuit whereby a stable clock signal can be provided corresponding to the polarity change of an unstable clock signal input received by the detector.

34. Phase shift apparatus to apply a 90° phase shift to a clock signal characterised by comprising in combination three AND gates (154, 158, 160), an OR gate (162) and an inverter (156) through which clock and data signals are supplied to a set-reset flipflop (164) having a preferred resettable state; and first and second "D" latches (166, 168) in series supplied with the output of the flipflop and direct and inverted clock signals; the arrangement being such that the output of the flipflop (164) is either zero or a previous state, and the output of the second latch (168) comprises the data signal read on the rising edge of the clock signal after a delay of two data cycles, whereby a 90° phase shift is applied.