WO1996038859A1 - Surface conditioning insulating layer for fine line conductive pattern - Google Patents
Surface conditioning insulating layer for fine line conductive pattern Download PDFInfo
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- WO1996038859A1 WO1996038859A1 PCT/US1996/008230 US9608230W WO9638859A1 WO 1996038859 A1 WO1996038859 A1 WO 1996038859A1 US 9608230 W US9608230 W US 9608230W WO 9638859 A1 WO9638859 A1 WO 9638859A1
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- insulating layer
- semiconductor device
- conductive pattern
- hydrogen peroxide
- ammonium hydroxide
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
The surface of an insulating layer is conditioned by treatment with ammonium hydroxide and hydrogen peroxide. Subsequently a conductive pattern with fine lines is formed thereon.
Description
SURFACE CONDITIONING INSULATING LAYER FOR FINE LINE CONDUCTIVE PATTERN
Technical Field
The present invention relates to a semiconductor device comprising a substrate having a conductive pattern thereon, and to a process for forming a conductive pattern. The invention has particular application in submicron circuit manufacturing.
Background Art
The escalating requirements for density and performance associated with ultra large scale integration semiconductor wiring require responsive changes in interconnection technology, which is considered one of the most demanding aspects of ultra large scale integration technology. High density demands for ultra large scale integration semiconductor wiring require minimal spacing between conductive wiring lines, i.e., an interwiring spacing of less than 1 micron, preferably less than 0.5 microns.
A traditional method for forming interconnection structures comprises the use of a subtractive etching or etch back step as the primary metal-patterning technique. One such traditional technique comprises depositing a layer of conductive material, such as aluminum or tungsten, on an insulating layer, and patterning the conductive layer in a conventional manner, as by photolithographic and etching techniques, to form a pattern of conductive lines having an interwiring spacing
therebetween. A dielectric layer is then applied and planarized, as by etching or chemical-mechanical polishing (CMP).
A recent technique employed to form a conductive pattern comprising conductive lines having an interwiring spacing therebetween comprises the application of the centuries old art of damascene, used for the fabrication of jewelry, to the semiconductor industry. Damascene basically involves the formation of a trench which is filled in with a metal. Thus, damascene differs from the traditional etch back methods of providing an interconnection structure by providing a trench which is filled in with metal followed by planarization; whereas, the traditional etch back technique involves building up a metal wiring layer and filling in the interwiring spaces with a dielectric material. Such applications comprise a single damascene technique wherein photoresist pattern is formed on an insulating layer and openings formed in the insulating layer by etching, such as reactive ion etching. Subsequently, a metal, such as tungsten, is deposited within the openings on the insulating layer, as by chemical vapor deposition. Alternatively, hot aluminum can be formed in the openings and on the insulating layer. Subsequent to metallization, planarization is effected as by etching or CMP. The process is then repeated by depositing a second insulating layer, forming openings, depositing metal and planarizing to obtain an interconnection structure.
An improvement in the single damascene process, called dual damascene, has recently been developed by IBM. See, for example, Joshi, "A New Damascene Structure for Sub icrometer Interconnect Wiring," IEEE Electron Letters, Vol. 14, No. 3, March 1993, pp. 129-132; and Kaanta et al., "Dual Damascene: A ULSI Wiring Technology," June 11-12, 1991, VMIC Conference, IEEE, pp. 144-152. The use of a damascene technique wherein the
dielectric is planarized by chemical-mechanical polish is discussed in Kenny et al., "A Buried-Plate Trench Cell for a 64-Mb DRAM," 1992, Symposium on VLSI Technology Digest of Technical Papers, IEEE, pp. 14-15. U.S. Patent No. 5,262,354 discloses a three-step method of forming electrically conductive vias and lines involving a damascene technique to create lines on a substrate. In addition, this patent discloses the advantages of chemical-mechanical polishing with an aluminum slurry in dilute nitric acid to planarize a dielectric surface.
U.S. Patent No. 5,093,279 discloses a laser ablation damascene process for planarizing metal/polymer structures in the fabrication of both interlevel via metallization and circuitization layers in integrated circuit interconnects.
As densification increases and the distance between the conductive lines of a conductive pattern, i.e., the interwiring spacing, decreases, the frequency of shorting between the conductive lines, particularly at interwiring spacings of less than 1 micron, increases, thereby generating a high rejection rate. Previous attempts to solve this interwiring shorting problem focused upon further reducing contamination in process areas. However, such attempts have not proved successful.
The occurrence of shorting between conductive lines of a conductive pattern presents a major problem in the semiconductor industry causing a high rejection rate with an attendant increase in production time and cost. Accordingly, there exists a need to reduce the frequency of interwiring shorting, particularly in conductive patterns having an interwiring spacing less than 1 micron, such as below 0.5 microns.
Disclosure of the Invention
An object of the present invention is a semiconductor device having a wiring pattern with an interwiring spacing of less than 1 micron free of shorting between conductive lines.
Another object of the present invention is a method of producing a semiconductor device comprising a conductive pattern of conductive lines with an interwiring spacing of less than 1 micron without shorting between the conductive lines.
Additional objects, advantages and other features of the invention will be set forth in part of the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and obtained as particularly pointed out in the appended claims.
According to the present invention, the foregoing and other objects are achieved in part by a semiconductor device comprising: a substrate; an insulating layer formed on the substrate; a conductive pattern comprising a plurality of conductive lines having an interwiring spacing therebetween formed on the insulating layer; wherein, the conductive pattern is formed by: treating a surface of the insulating layer with ammonium hydroxide and hydrogen peroxide; and forming the conductive pattern on the treated surface of the insulating layer.
A further object of the present invention is a semiconductor device comprising a substrate; an insulating layer formed on the substrate; a conductive pattern comprising a plurality of conductive lines having an interwiring spacing therebetween formed on the insulating layer; wherein the conductive pattern is formed by treating the surface of the insulating layer with a solution of ammonium hydroxide and hydrogen
peroxide for a period of time sufficient to condition the surface, thereby reducing the frequency of shorting between the conductive lines.
Another object of the invention is a method of manufacturing a semiconductor device, comprising: forming an insulating layer on a substrate; treating a surface of the insulating layer with ammonium hydroxide and hydrogen peroxide; and forming a conductive pattern comprising a plurality of conductive lines having an interwiring spacing therebetween on the treated surface of the insulating layer.
A further object of the present invention is a method of manufacturing a semiconductor device, comprising: forming an insulating layer on a substrate; treating the surface of the insulating layer with a solution of ammonium hydroxide and hydrogen peroxide for a sufficient period of time sufficient to condition the surface, thereby reducing the frequency of shorting between conductive lines subsequently formed thereon, and forming a conductive pattern comprising a plurality of conductive lines having an interwiring spacing therebetween on the treated surface of the insulating layer.
Additional objects and advantages of the present invention will become readily apparent to those skilled in this art from the following detailed description, wherein only the preferred embodiment of the invention is shown and described, simply by way of illustration of the best mode contemplated for carrying out the invention. As will be realized, the invention is capable of other and different embodiments, and its several details are capable of modifications in various obvious respects, all without departing from the invention. Accordingly, the description is to be regarded as illustrative in nature, and not as restrictive.
Description of the Invention
The present invention addresses the problem of shorting between conductive lines of a conductive pattern, which problem is acute in conductive patterns having an interwiring spacing of less than 1 micron, particularly in conductive patterns having an interwiring spacing less than about 0.5 microns. The interwiring shorting problem occurs in conductive patterns regardless of the method by which they are formed, i.e., etch back or damascene techniques. The occurrence of shorting between conductive lines is a serious problem in the semiconductor industry, resulting in a high rejection rate and consequential increased production time and expense. In attempting to solve the interwiring shorting problem, extensive experimentation was initially conducted focusing on reduced contamination. An experimental procedure was followed comprising forming a conductive pattern by conventional techniques, such as conventional etch back, damascene employing photolithography and etching techniques, and testing to determine the defect, i.e., shorting, density. Continuous efforts were made during processing to minimize contamination from various potential sources, including environmental sources and etching residues.
However, a solution to the interwiring shorting problem remained elusive, in that the defect density remained high, causing an economically undesirably rejection rate.
During the course of experimentation, normal semiconductor processing techniques were followed to provide realistic conditions. Such normal semiconductor processing techniques include metal etch back techniques, such as a tungsten etch to etch back tungsten applied to an insulating layer, and CMP. Throughout the course of experimentation, the frequency of interwiring shorting, i.e., defect density, was monitored.
During the course of experimentation, the surface of an insulating layer was treated in various ways consistent with the type of treatment to which it would have been exposed during various processing phases. During such experimentation, it was unexpectedly found that the treatment of the surface of an insulating layer with ammonium hydroxide and hydrogen peroxide somehow reduced the frequency of shorting between conductive lines of a conductive pattern subsequently formed on the insulating layer. A solution of ammonium hydroxide and hydrogen peroxide is sometimes employed during initial semiconductor processing, as for cleaning a gate oxide film, or during chemical-mechanical polishing when planarizing a tungsten conductive pattern. It was, therefore, quite unexpected that the treatment of an insulating layer with a solution of ammonium hydroxide and hydrogen peroxide significantly reduced the defect density of a subsequently formed conductive pattern.
These experiments were repeated successfully by initially treating the surface of an insulating layer with ammonium hydroxide and hydrogen peroxide, preferably a solution of ammonium hydroxide, hydrogen peroxide and water, preferably deionized water, for a period of time sufficient to condition the surface. A layer of conductive material was subsequently deposited on the portion of the surface of the insulating layer which had been treated with ammonium hydroxide and hydrogen peroxide, and a conductive pattern comprising a plurality of conductive lines separate by an interwiring spacing formed thereon by conventional photolithographic and etching techniques. It was unexpectedly found that the surface of the insulating layer was altered in some manner by treatment with a solution of ammonium hydroxide and hydrogen peroxide in water, so that the frequency of shorting or defect density between conductive lines of a subsequently formed conductive pattern thereon was
dramatically decreased vis-a-vis a similar conductive pattern formed in a similar manner without treating the surface of the insulating layer with the solution of ammonium hydroxide, hydrogen peroxide and water. Accordingly, the present invention comprises treating the surface of an insulating layer with ammonium hydroxide and hydrogen peroxide, and forming a conductive pattern comprising a plurality of conductive lines having an interwiring spacing therebetween on the treated surface of the insulating layer. The conductive pattern is suitably formed in any conventional manner, such as by a damascene process with subsequent metallization or by depositing a layer of conductive material and employing conventional photolithographic and etching techniques. In employing a damascene process, surface treatment of the insulating layer can be conducted prior to trench formation or after trench formation and prior to deposition of conductive material therein. It was unexpectedly found that the surface of the insulating layer is modified in some manner by treatment with ammonium hydroxide and hydrogen peroxide to effectively reduce shorting between the conductive lines of the subsequently formed conductive pattern on the treated insulating surface. The particular manner in which the surface of the insulating layer is altered to effect reduction of the frequency of shorting between conductive lines of a subsequently formed conductive pattern on the treated insulating layer is not known. Without wishing to be bound to any particular theory, it is speculated that the surface of the insulating layer is altered by treatment with ammonium hydroxide and hydrogen peroxide so that contamination, such as particulate contamination, which would otherwise cause shorting between conductive lines, is repelled from the treated surface. Thus, in accordance with the present invention, fine line
conductive patterns can be formed with minimal interwiring spacings, such as less than about 0.1 micron, preferably less than about 0.5 microns, with a reduced defect density and, hence, reduced rejection rate. In a preferred embodiment according to the present invention, the surface of the insulating layer is treated for a period of time sufficient to condition the surface so that the frequency of shorting between conductive lines of a subsequently formed conductive pattern on the treated surface of the insulating layer is significantly reduced. In a preferred aspect, the surface of the insulating layer is treated with a solution of ammonium hydroxide and hydrogen peroxide in water, preferably deionized water. The amounts of ammonium hydroxide and hydrogen peroxide, as well as the time and temperature of treatment, are variables which one having ordinary skill in the art could easily optimize in a particular situation to reduce the frequency of shorting between conductive lines of a subsequently formed conductive pattern thereon.
It has been found that a solution containing about 4% to about 15% by volume ammonium hydroxide and about 8% to about 30% by volume hydrogen peroxide can be employed, preferably a solution containing about 6% to about 10% by volume ammonium hydroxide and about 10% to about 20% by volume hydrogen peroxide. In a particularly preferred embodiment, a solution containing about 8% by volume ammonium hydroxide, about 15% by volume hydrogen peroxide and about 77% by volume deionized water is employed. The duration of treatment of the surface of the insulating layer should be sufficient to effect sufficient alteration of the surface to advantageously reduce the frequency of shorting between conductive lines of the subsequently formed conductive pattern thereon. It has been found that about 3 to about 10 minutes is usually sufficient, most preferably about 6 minutes.
The manner in which the surface of the insulating layer is treated is not critical, as long as the surface is sufficiently exposed to the solution of ammonium hydroxide and hydrogen peroxide. Suitable types of treatment comprise rinsing, immersing, spraying, or the use of any of various types of conventional equipment typically employed to apply a fluid to the surface of a solid, such as a semiconductor wafer. For example, it has been found effective treat the surface of the insulating layer with a solution of ammonium hydroxide and hydrogen peroxide in an FSI rotor type system, such as Model FSI Mercury MP, marketed by FSI International, Inc. located in Chanhassan, Minnesota. In such type of apparatus, the semiconductor wafer is rotated while a solution comprising ammonium hydroxide, hydrogen peroxide and water is applied to the surface of the insulating layer through a nozzle.
The temperature during surface treatment can vary within wide limits. However, it has been found advantageous to conduct treatment between about 70°C to about 120°C, preferably 80°C to about 110°C, most preferably at 100°C. The surface treatment can be conducted at atmosphere pressure. When applying a spray through a nozzle, the pressure can be optimized in a particular situation to achieve a desired reduction of shorting between conductive lines of a subsequently formed conductive pattern.
The insulating layer of the present invention subjected to surface treatment can be any insulating material conventionally employed in the manufacture of semiconductor devices. Preferably, the insulating layer comprises a material selected from the group consisting of oxides, nitrides and oxynitrides. Silicon dioxide, silicon nitride and silicon oxynitride have been found particularly suitable, preferably silicon dioxide, most preferably silicon dioxide derived from deposited tetra
ethyl ortho silicate (TEOS). The insulating layer is typically formed on a semiconductor substrate, such as silicon.
The conductive material employed in the present invention can comprise any conductive material conventionally employed in the semiconductor industry to form a conductive pattern, such as aluminum, aluminum- base alloys, such as aluminum copper alloys, refractory metals, compounds or alloys thereof, preferably tungsten and tungsten-base alloys and polysilicon. The conductive layer can also comprise a plurality of layers, including an initial conventional barrier layer of titanium, titanium nitride or titanium-titanium nitride, and a layer of conductive material, such as tungsten, deposited thereon.
The insulating layer and conductive material are formed by any of various conventional techniques. For example, the insulating layer can be formed by thermal oxidation of a deposited silicon layer, spin on techniques, or deposited by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), or thermal enhanced CVD. The conductive material can be deposited in any conventional manner, as by conventional metallization techniques, preferably, CVD techniques, including low pressure CVD, and PECVD. Low melting point metals can be deposited by melting or sputtering.
In accordance with the present invention, any portion of the insulating layer can be treated with a solution of ammonium hydroxide and hydrogen peroxide to reduce interwiring shorting between conductive lines of a subsequently formed conductive pattern. In a preferred embodiment, treatment is conducted with a solution of ammonium hydroxide and hydrogen peroxide on an unpatterned insulating layer prior to formation of a conductive pattern thereon. Preferably, the insulating
layer is silicon dioxide, most preferably formed from deposited TEOS.
EXAMPLE
In order to demonstrate the effectiveness of the present invention, comparison testing was conducted wherein a conductive pattern was formed with and without prior treatment of the insulating surface with ammonium hydroxide and hydrogen peroxide. Basically, the processing steps and materials were identical except for the treatment of the insulating surface with a solution of ammonium hydroxide and hydrogen peroxide prior to formation of a conductive pattern thereon. In conducting each test, three separate samples were prepared and run.
Teat 1 A silicon semiconductor substrate was coated with a thin film of silicon dioxide derived from TEOS having a thickness of about 450θA. Without any surface conditioning, a conductive pattern comprising aluminum metal lines was formed by CVD and conventional lithographic and etching techniques. Three different substrates were prepared and the defect density measured. The measured defect densities were 3.08, 3.8 and 2.67 for an average of 3.18.
Teat 2 The procedure employed in Test 1 was repeated, except that the surface of the insulating layer was treated with a mixture comprising about 8% by volume ammonium hydroxide, about 15% by volume hydrogen peroxide, and about 77% by volume deionized water, for about 6 minutes at about 100°C, in an FSI rotor system. The three samples exhibited defect densities of 3.4, 3.06 and 1.27, for an average defect density of 2.58. This reduction in defect density caused by treating the
surface of the insulating layer with a solution comprising ammonium hydroxide and hydrogen peroxide is unexpected and significant.
The above reported comparison testing demonstrates that treatment in accordance with the present invention of the surface of an insulating layer with a solution of ammonium hydroxide and hydrogen peroxide conditions the surface by altering it so that the frequency of shorting between conductive lines of a subsequently formed conductive pattern thereon is significantly reduced. The present invention has utility in various phases of semiconductormanufacturing, particularly in forming fine line patterns separated by minimal interwiring spacings, preferably less than about 1.0 micron, most preferably less than about 0.5 microns. The present invention is not limited to any particular insulating layer, conductive material, manner of forming the conductive pattern or manner of treating the surface of the insulating layer, as long as the insulating layer is treated with ammonium hydroxide and hydrogen peroxide for a period of time sufficient to condition the surface of the insulating layer, thereby reducing the frequency of shorting between conductive lines subsequently formed thereon. The present invention reduces interwiring shorting of conductive patterns formed in any manner, including by etch back and damascene techniques. Thus, by the present invention, conductive patterns can be formed having interwiring spacings less than 1.0 micron, preferably less than about 0.5 microns, with reduced frequency of interwiring shorting and consequential reduction in rejection rate, increased production speed and reduction in expense.
Only the preferred embodiment of the invention and but a few examples of its versatility are shown and described in the present disclosure. It is to be
understood that the invention is capable of use in various other combinations and environments and is capable of changes or modifications within the scope of the inventive concept as expressed herein.
Claims
1. A semiconductor device, comprising: a substrate; an insulating layer formed on the substrate; a conductive pattern comprising a plurality of conductive lines having an interwiring spacing therebetween formed on the insulating layer; wherein, the conductive pattern is formed by: treating a surface of the insulating layer with ammonium hydroxide and hydrogen peroxide; and forming the conductive pattern on the treated surface of the insulating layer.
2. The semiconductor device according to claim 1, wherein the conductive pattern is formed by depositing a layer of conductive material and etching.
3. The semiconductor device according to claim 1, wherein the conductive pattern is formed by a damascene technique comprising forming trenches defining the conductive pattern and depositing a conductive material therein.
4. The semiconductor device according to claim 1, wherein the surface of the insulating layer is treated with a solution of ammonium hydroxide and hydrogen peroxide for a period of time sufficient to condition the surface, thereby reducing the frequency of shorting between the conductive lines.
5. The semiconductor device according to claim 4, wherein the surface of the insulating material is treated with a solution of ammonium hydroxide, hydrogen peroxide and water.
6. The semiconductor device according to claim 5, wherein the water is deionized water.
7. The semiconductor device according to claim 5, wherein the solution contains about 4% to about 15% by volume ammonium hydroxide and about 8% to about 30% by volume hydrogen peroxide.
8. The semiconductor device according to claim 7, wherein the solution contains about 6% to about 10% by volume ammonium hydroxide and about 10% to about 20% by volume hydrogen peroxide.
9. The semiconductor device according to claim 8, wherein the solution contains about 8% by volume ammonium hydroxide, about 15% by volume hydrogen peroxide and about 77% by volume deionized water.
10. The semiconductor device according to claim 4, wherein the surface of the insulating layer is treated for about 3 to about 10 minutes.
11. The semiconductor device according to claim 9, wherein the surface of the insulating layer is treated for about 6 minutes.
12. The semiconductor device according to claim 4, wherein the surface of the insulating layer is treated by rinsing.
13. The semiconductor device according to claim 4, wherein the surface of the insulating layer is treated by placing the substrate containing the insulating layer into an apparatus in which the substrate is rotated while a solution comprising ammonium hydroxide, hydrogen peroxide and water is applied to the surface of the insulating layer.
14. The semiconductor device according to claim 1, wherein the conductive pattern comprises a metal.
15. The semiconductor device according to claim 14, wherein the metal is tungsten.
16. The semiconductor device according to claim 14, wherein the conductive pattern comprises a barrier layer.
17. The semiconductor device according to claim 15, wherein the conductive pattern comprises a barrier layer.
18. The semiconductor device according to claim 16, wherein the barrier layer comprises titanium, titanium nitride or titanium-titanium nitride.
19. The semiconductor device according to claim 17, wherein the barrier layer comprises titanium, titanium nitride or titanium-titanium nitride.
20. The semiconductor device according to claim 1, wherein the interwiring spacing is less than about 1 micron.
21. The semiconductor device according to claim 20, wherein the interwiring spacing is less than about 0.5 microns.
22. The semiconductor device according to claim 1, wherein the insulating layer comprises a material selected from the group consisting of oxides, nitrides and oxynitrides.
23. The semiconductor device according to claim 22, wherein the insulating material comprises silicon dioxide.
24. The semiconductor device according to claim 22, wherein the insulating material comprises silicon nitride.
25. The semiconductor device according to claim 22, wherein the insulating material comprises silicon oxynitride.
26. A method of manufacturing a semiconductor device, comprising: forming an insulating layer on a substrate; treating a surface of the insulating layer with ammonium hydroxide and hydrogen peroxide; and forming a conductive pattern comprising a plurality of conductive lines having an interwiring spacing therebetween on the treated surface of the insulating layer.
27. The method according to claim 26, comprising depositing a layer of conductive material and etching the deposited conductive material to form the conductive pattern.
28. The method according to claim 26, wherein the conductive pattern is formed by a damascene technique comprising forming trenches defining the conductive pattern and depositing a conductive material therein.
29. The method according to claim 26, comprising treating the surface of the insulating layer with a solution of ammonium hydroxide and hydrogen peroxide for a period of time sufficient to condition the surface. thereby reducing the frequency of shorting between the conductive lines.
30. The method according to claim 29, comprising treating the surface of the insulating layer with a solution of ammonium hydroxide, hydrogen peroxide and water.
31. The method according to claim 30, wherein the water is deionized water.
32. The method according to claim 30, wherein the solution contains about 4% to about 15% by volume ammonium hydroxide and about 8% to about 30% by volume hydrogen peroxide.
33. The method according to claim 32, wherein the solution contains about 6% to about 10% by volume ammonium hydroxide and about 10% to about 20% by volume hydrogen peroxide.
34. The method according to claim 33, wherein the solution contains about 8% by volume ammonium hydroxide, about 15% by volume hydrogen peroxide and about 77% by volume deionized water.
35. The method according to claim 29, comprising treating the surface of the insulating layer for about 3 to about 10 minutes.
36. The method according to claim 35, comprising treating the surface of the insulating layer for about 6 minutes.
37. The method according to claim 26, comprising treating the surface of the insulating layer by rinsing.
38. The method according to claim 26, comprising treating the surface of the insulating layer by immersion.
39. The method according to claim 26, comprising placing the semiconductor substrate with insulating layer thereon into an apparatus and rotating the semiconductor substrate while a solution comprising ammonium hydroxide, hydrogen peroxide and water is applied to the surface of the insulating layer.
40. The method according to claim 26, wherein the conductive pattern comprises a metal.
41. The method according to claim 40, wherein the metal comprises tungsten.
42. The method according to claim 40, wherein the conductive pattern comprises a barrier layer.
43. The method according to claim 41, wherein the conductive pattern comprises a barrier layer.
44. The method according to claim 42, wherein the barrier layer comprises titanium, titanium nitride or titanium-titanium nitride.
45. The method according to claim 43, wherein the barrier layer comprises titanium, titanium nitride or titanium-titanium nitride.
46. The method according to claim 26, wherein the interwiring spacing is less than about 1 micron.
47. The method according to claim 46, wherein the interwiring spacing is less than about 0.5 microns.
48. The method according to claim 26, wherein the insulating material is selected from the group consisting of oxides, nitrides and oxynitrides.
49. The method according to claim 48, wherein the insulating material comprises silicon dioxide.
50. The method according to claim 48, wherein the insulating material comprises silicon nitride.
51. The method according to claim 48, wherein the insulating material comprises silicon oxynitride.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US45858495A | 1995-06-02 | 1995-06-02 | |
| US08/458,584 | 1995-06-02 |
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| Publication Number | Publication Date |
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| WO1996038859A1 true WO1996038859A1 (en) | 1996-12-05 |
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| Application Number | Title | Priority Date | Filing Date |
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| PCT/US1996/008230 WO1996038859A1 (en) | 1995-06-02 | 1996-05-31 | Surface conditioning insulating layer for fine line conductive pattern |
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| WO (1) | WO1996038859A1 (en) |
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| JPH10242271A (en) * | 1997-02-28 | 1998-09-11 | Sony Corp | Semiconductor device and its manufacture |
| US6472335B1 (en) | 1998-10-19 | 2002-10-29 | Taiwan Semiconductor Manufacturing Company | Methods of adhesion promoter between low-K layer and underlying insulating layer |
| US6187663B1 (en) | 1999-01-19 | 2001-02-13 | Taiwan Semiconductor Manufacturing Company | Method of optimizing device performance via use of copper damascene structures, and HSQ/FSG, hybrid low dielectric constant materials |
| US6265319B1 (en) | 1999-09-01 | 2001-07-24 | Taiwan Semiconductor Manufacturing Company | Dual damascene method employing spin-on polymer (SOP) etch stop layer |
| US6391761B1 (en) | 1999-09-20 | 2002-05-21 | Taiwan Semiconductor Manufacturing Company | Method to form dual damascene structures using a linear passivation |
| US6583046B1 (en) * | 2001-07-13 | 2003-06-24 | Advanced Micro Devices, Inc. | Post-treatment of low-k dielectric for prevention of photoresist poisoning |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US5393686A (en) * | 1994-08-29 | 1995-02-28 | Taiwan Semiconductor Manufacturing Company | Method of forming gate oxide by TLC gettering clean |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4014772A (en) * | 1975-04-24 | 1977-03-29 | Rca Corporation | Method of radiation hardening semiconductor devices |
| GB2216336A (en) * | 1988-03-30 | 1989-10-04 | Philips Nv | Forming insulating layers on substrates |
| GB2220298A (en) * | 1988-06-29 | 1990-01-04 | Philips Nv | A method of manufacturing a semiconductor device |
| US5093279A (en) * | 1991-02-01 | 1992-03-03 | International Business Machines Corporation | Laser ablation damascene process |
| US5262354A (en) * | 1992-02-26 | 1993-11-16 | International Business Machines Corporation | Refractory metal capped low resistivity metal conductor lines and vias |
| US5407529A (en) * | 1992-03-04 | 1995-04-18 | Nec Corporation | Method for manufacturing semiconductor device |
-
1996
- 1996-05-31 WO PCT/US1996/008230 patent/WO1996038859A1/en active Application Filing
-
1997
- 1997-01-24 US US08/789,599 patent/US5767582A/en not_active Expired - Lifetime
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5393686A (en) * | 1994-08-29 | 1995-02-28 | Taiwan Semiconductor Manufacturing Company | Method of forming gate oxide by TLC gettering clean |
Non-Patent Citations (2)
| Title |
|---|
| H. KAIGAWA ET AL.: "ETCHING OF THERMALLY GROWN SIO2 BY NH4OH IN MIXTURE OF NH4OH AND H202 CLEANING SOLUTION", JAPANESE JOURNAL OF APPLIED PHYSICS, vol. 33, no. 7A, July 1994 (1994-07-01), pages 4080 - 4085, XP000579912 * |
| N.WATANABE ET AL.: "ETCHING RATES OF SIO2 AND SI3N4 INSULATING FILMS IN AMMONIA HYDROGEN-PEROXIDE CLEANING PROCESS", EXTENDED ABSTRACTS, vol. 83, no. 1, May 1983 (1983-05-01), PENNINGTON,NEW JERSEY,USA, pages 221, XP002011796 * |
Also Published As
| Publication number | Publication date |
|---|---|
| US5767582A (en) | 1998-06-16 |
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