WO1997000481A1 - An apparatus and method for providing remote pci slot expansion - Google Patents

An apparatus and method for providing remote pci slot expansion Download PDF

Info

Publication number
WO1997000481A1
WO1997000481A1 PCT/US1996/010460 US9610460W WO9700481A1 WO 1997000481 A1 WO1997000481 A1 WO 1997000481A1 US 9610460 W US9610460 W US 9610460W WO 9700481 A1 WO9700481 A1 WO 9700481A1
Authority
WO
WIPO (PCT)
Prior art keywords
expansion
pci
host
bridge
bus
Prior art date
Application number
PCT/US1996/010460
Other languages
French (fr)
Inventor
Bruce Young
Original Assignee
Intel Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to KR1019970709312A priority Critical patent/KR100291051B1/en
Priority to EP96921651A priority patent/EP0832458B1/en
Priority to DE69636519T priority patent/DE69636519D1/en
Priority to JP9503396A priority patent/JPH11514112A/en
Priority to AU62818/96A priority patent/AU6281896A/en
Publication of WO1997000481A1 publication Critical patent/WO1997000481A1/en
Priority to HK98110832A priority patent/HK1009866A1/en

Links

Classifications

    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/38Information transfer, e.g. on bus
    • G06F13/40Bus structure
    • G06F13/4004Coupling between buses
    • G06F13/4027Coupling between buses using bus bridges
    • G06F13/4045Coupling between buses using bus bridges where the bus bridge performs an extender function
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/10Distribution of clock signals, e.g. skew
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F2213/00Indexing scheme relating to interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F2213/0024Peripheral component interconnect [PCI]

Definitions

  • the invention relates to bussing in a computer system. More specifically, the invention relates to using PCI as a cable bus to expand the number of PCI slots available in a system.
  • PCI peripheral component interconnect
  • the peripheral component interconnect (PCI) bus is a high performance low latency I/O bus architected to minimize system cost.
  • PCI has quickly gained wide acceptance in the computer industry.
  • the PCI bus standard provides for a high bandwidth and a flexibility that is independent of new processor technologies and increased processor speed.
  • computer system architects are primarily designing speed sensitive peripherals such as graphics accelerators and SCSI disk drive controllers to be utilized with the PCI bus.
  • PCI PCI Local Bus Specification, rev. 2.0, April 30, 1993.
  • the specification reflects that PCI is capable of running at any frequency up to 33 MHz. This high level of possible throughput makes PCI an ideal choice for volume servers.
  • the PCI bus can only support 3 - 4 slots along a single bus segment. This number of slots is unacceptably low for a practical application in the volume server market.
  • Some prior systems have addressed this problem by cascading PCI buses on the host mother board. Unfortunately, such cascading increases the cost of the basic system and still fails to provide a level of slot expansion necessary in volume servers.
  • single chassis systems are not readily expandable as the user's needs change.
  • PCI bus specification requires four active low, level sensitive interrupt pins for all slots supported and defines these interrupts' use as hardware shareable. That means that multiple PCI devices can drive the same interrupt line or that multiple PCI interrupt lines can be driven by different devices but may result in a single interrupt being generated to the system interrupt controller to be serviced by a shared interrupt driver.
  • the resources and overhead required to resolve the source of the interrupt also increases as the number of sharing slots increases.
  • Figure 1 shoes a block diagram of a host and expansion module of the invention.
  • Figure IA is a table of the signals and required pins in the cabled bus of the invention.
  • FIG. 2 is a block diagram of the module interfaces of the instant invention.
  • FIG. 3 is a diagram of the clock generation circuit for the expansion module of the invention.
  • Figure 4 is a table listing specifications of cables suitable for the instant invention.
  • Figure 4A is a table showing timing budgets of two possible operating point for the invention.
  • the instant invention provides an apparatus and method for expanding the number of PCI slots available to a host system.
  • host and expansion time domains are segregated.
  • a cabled PCI bus responsive to a clock signal generated and controlled in the expansion module is used to carry the signals between independent host and expansion chassis. Because the expansion system is not dependent on the host clock or the functionalities of the host system, it is suitable for integration into existing system, and it will not increase the cost of a base host system. Thus, the invention provides ready expandability as needs change.
  • the invention provides interrupt expansion in addition to slot expansion. This is accomplished by providing a means for connecting to the host APIC bus on the expansion card and a means of encoding the PCI interrupts generated by the expansion PCI slot into APIC on the expansion mother board. This expansion will reduce the overhead associated with servicing interrupts shared by the expanded slots.
  • the present invention provides a method and apparatus for using a cabled PCI bus to provide an expansion of the number of PCI slots available to a host system.
  • specific details are set forth to provide a thorough understanding of the present invention. However, it will be understood by one skilled in the art, from reading this disclosure, that the invention may be practiced without these details. Moreover, well known elements devices, process steps and the like are not set forth in order to avoid obscuring the invention.
  • FIG. 1 shows a block diagram of a system incorporating the instant invention.
  • the host system resides within a host chassis 1 and includes a host mother board 3.
  • the host mother board has a CPU 5 connected to a memory 6 by a system bus 7.
  • a bridge 8 is provided on the mother board to bridge between the system bus 7 and a host PCI bus 9.
  • the PCI specification only permits 3 - 4 slots 10 along a single bus segment.
  • the expansion card 11 has a primary expansion bridge (PEB) 12 described more fully with reference to Figure 2 below, and a cable connector 15, an exemplary embodiment employs a 100 pin cable connector.
  • the expansion card also provides an optional APIC connector 14 to allow the card 11 to be connected to the APIC bus not shown on the host mother board 3. This allows for sufficient signal conductors to accommodate parallel transmission of all PCI required signals and adequate grounding.
  • Figure IA is a table of the relevant PCI signals.
  • the cable 16 is selected based on propagation speed down the cable 16 and cable skewing. It is desirable to choose a cable 16 with minimal skewing with maximum propagation speed.
  • the cable 16 functions as a point to point PCI bus between the expansion side of the PEB 12 and the secondary expansion bridge (SEB) 19 which is described more fully below.
  • the cable 16 should be well terminated at either end with impedances approximately equal to the characteristic impedance in the cable.
  • a six foot HIPPI cable with a characteristic impedance of 88 ⁇ 5 ohms is used.
  • HIPPI cable meets ANSI standards and includes 50 twisted pairs, thereby providing an adequate number of signal lines. It would be possible to use a smaller cable and lower pin count connector but such would limit possible functionality somewhat.
  • the expansion chassis 2 contains an expansion mother board 4 to which the cable 16 connects via connector 17.
  • a PCI bus runs from the connector to the SEB 19.
  • the clocking in the expansion system is provided by a clock generator 18 which is asynchronous with and independent of the host clock (not shown).
  • the number of slots 21 available on the secondary PCI bus (SPB) 20 is determined by the speed of the clock signal generated. At 25 MHz, 8 - 12 slots are available, while at 33 MHz, only 3 - 4 slots would be available.
  • expansion modules could be coupled to a single host (one card per available PCI slot). It is also within the scope of the invention to cascade an expansion module off an expansion module.
  • Figure 2 more clearly sets forth the relationship between the PEB 12, Cable 16, and SEB 19.
  • Figure 2 is divided into three clock domains.
  • the instant invention employs an asynchronous bridge 33 between the host and expansion module.
  • a PCI to PCI bridge comprises a primary bus interface and a secondary bus interface.
  • the primary interface is responsive to the host clock while the secondary interface is responsive to the expansion clock, thereby creating an asynchronous boundary 13 between the host clock domain 30 and expansion clock domain 32.
  • this could be implemented with a pair of D flip flops for each relevant signal.
  • Inbound and outbound queues of 4x16 bytes have been found adequate. For further detail see PCI to PCI Bridge Spec. Revision 1.0, April 15, 1994.
  • the host PCI bus is connected to an asynchronous PCI to PCI bridge 33 contained in PEB 12 on the expansion card.
  • the host side of the bridge 33 operates in the host clock domain 30 while the expansion side is synchronous with the expansion clock domain 32.
  • the PEB 12 also contains a demultiplexer 38 to demultiplex the 4 PCI supported interrupts coming from the expansion system.
  • An optional APIC bus interface 36 can also be provided within the PEB 12, thereby expanding the interrupts available to the expansion system. Such interface must be asynchronous operating partially in the APIC clock domain 31 and partially in the expansion clock domain 32. Significantly, this option does not comply with PCI specification.
  • Intelligent VO units like those described in co-pending application, Architecture for I/O Processor that Integrates a PCI-to-PCI Bridge, Serial No. supports these functionalities. Accordingly, one embodiment envisioned in the instant invention employs such an intelligent I/O unit as the PEB 12.
  • the expansion end of the asynchronous bridge 33 is coupled through a cabled PCI bus 16 to the SEB 19 on the expansion mother board 41.
  • the cable 16 contains the PCI bus signals 44, the expansion domain clock signal 40, an SINT# 39.
  • SINT #39 is not a standard PCI line. Rather, it is a line carrying the serialization of the standard PCI interrupts.
  • One way to serialize this is to continuously synchronize the four standard PCI interrupt signals to the PCI clock and send the information across the interface on SINT# whenever a change occurs using a protocol of one start bit (low), INTA#, INTB#, INTC#, INTD#, odd parity and one stop bit (high) as shown in Figure 5.
  • an interrupt is unmasked in the I/O APIC, then that INT# line should not be serialized on the SINT# signal (i.e. it should be interpreted as inactive). In such case, the I/O APIC will handle distributing the interrupt to the host.
  • the SINT# protocol will be driven continuously (with all interrupts inactive) during reset.
  • the interrupt serializer will also send a new message after 16 clocks of inactivity.
  • SINT# is used by the PEB to decode the current value of INTA#, INTB#, INTC#, INTD#. Whenever the interrupt demux block sees SINT# go low, it will capture the data for the next four clocks and if the parity (5th cloth after Start) is good, use the data to update its current value for the four interrupt outputs. If bad parity is detected, the data will be ignored.
  • This interrupt serialization process causes a worst case delay of 9 clocks for each level of expansion subsystem (2 for synchronization and 7 to send) which is 360 ns at 25 MHz. This is merely one simple way to serialize interrupts. Other serialization schemes will occur to one of ordinary skill in the art, such schemes are contemplated for use with the instant invention.
  • the SEB 19 contains a PCI to PCI bridge 34 which may be synchronous or asynchronous.
  • SEB 19 also optionally contains an I O APIC 35 which expands the number of interrupts available for use by the expansion system, and reduces or eliminates the polling which would be required if all PCI slots in the combined host and expansion system shared only the four PCI provided interrupts.
  • an interrupt steering device 37 is provided to either steer the PCI supported interrupts across the cable 16 to the demultiplexer 38, or if provided, steers slot interrupt into the VO APIC 35 which in turn buses the interrupt along the cable 16 to the APIC bus interface 36.
  • Serial No. could be used to implement SEB 19. Also, on the expansion mother board 4 are the clock generation device 18 and the secondary PCI bus 45.
  • PCI does not define a maximum number of slots, rather it has rigidly defined electrical characteristics. Specifically, PCI defines that clock skew + clock to out at master + setup at target + settling time ⁇ clock period. In the clock generation scheme described below the time allotted for settling is used as flight time down the cable 16 thereby reducing the latency in the transaction between host and expansion modules. Since the introduction of each slot 21 increases the capacitance of the system thereby negatively affecting the transition speed between states, i.e., the settling time, a slower clock increases the time available for settling and accordingly increase the number of loads (slots) the system can handle. If operation is at 25 MHz, it is contemplated that 8 - 12 slots could be provided.
  • FIG 3 shows the clock generation of the instant invention
  • an oscillator 50 generates a clock signal of a desired frequency up to 33 MHz. It will be recognized that an oscillator need not be employed to generate the clock signal, any conventional method of generating a signal of the desired frequency can be employed. In an exemplary embodiment, the oscillator 50 generates a 25 MHz clock signal.
  • FIG. 3 shows the clock signal going to the cable 16 and ten other lines 58. This is adequate for right slots 21 and the SEB 19. It is necessary that the clock used at the host interface end of the cable 15 and expansion chassis interfaces 58 arrive within the clock skew timing specifications. To this end, low skew clock drivers 51 are employed along each line to minimize skew along the different lines, and a delay element 52 is introduced between the local lines and the remote interface 15. By matching the propagation delay in the cable 16 to the host (remote) interface 15 with a delay element 52, it is possible to achieve the desired synchronization of the clocks at the respective interfaces 15 and 58.
  • each clock signal line should be matched as closely as possible.
  • the same number of buffer drivers 51 are employed along each line.
  • Impedances 56 should be matched with the characteristic impedance of the clock traces on expansion motherboard 4.
  • the lengths of printed circuit board traces from the buffers 51 to their destinations should be as closely matched as possible, including the trace from the buffer driving the cable connection. This can be done by increasing the lengtii of all traces to match which ever trace has the longest length naturally.
  • the most critical length match is between the clock going to the SEB 19 and the one driving the PEB 12 through the cable 16. Appropriately selecting delay 52 line value will improve this match.
  • the electrical connection scheme uses the bridge chips (i.e., PEB and SEB) to connect to the cable using series termination.
  • This termination is external.
  • the series termination value is equal to the impedance of the cable minus the impedance of the driver.
  • the source end of the cable is driving with a 1/2 voltage incident waveform which doubles to a full voltage waveform due to the reflection coefficient of 1 it encounters at the destination end of the cable.
  • the series termination forms a half wave incident waveform which encounters a reflection coefficient of one.
  • the characteristic impedance of such cable is 88 ⁇ 5 ohms. Accordingly appropriate termination impedances can be selected with reference to the impedance of the selected driver.

Abstract

An apparatus and method for providing PCI slot expansion (21). An asynchronous PCI to PCI bridge (34) for insertion into a host PCI slot (10) is coupled via a cabled PCI bus (16) to an expansion module (4). The bridge establishes two distinct time domains. An expansion clock signal (18) is generated and its timing matched for consistent arrival throughout the expansion clock domain. An expanded number of PCI slots are thereby available to the host system.

Description

AN APPARATUS AND METHOD FOR PROVIDING
REMOTE PCI SLOT EXPANSION
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates to bussing in a computer system. More specifically, the invention relates to using PCI as a cable bus to expand the number of PCI slots available in a system.
2. Related Art
The peripheral component interconnect (PCI) bus is a high performance low latency I/O bus architected to minimize system cost. PCI has quickly gained wide acceptance in the computer industry. The PCI bus standard provides for a high bandwidth and a flexibility that is independent of new processor technologies and increased processor speed. At this time, computer system architects are primarily designing speed sensitive peripherals such as graphics accelerators and SCSI disk drive controllers to be utilized with the PCI bus.
The PCI specification is well defined. See particularly, PCI Local Bus Specification, rev. 2.0, April 30, 1993. The specification reflects that PCI is capable of running at any frequency up to 33 MHz. This high level of possible throughput makes PCI an ideal choice for volume servers. Unfortunately, at such speed, the PCI bus can only support 3 - 4 slots along a single bus segment. This number of slots is unacceptably low for a practical application in the volume server market. Some prior systems have addressed this problem by cascading PCI buses on the host mother board. Unfortunately, such cascading increases the cost of the basic system and still fails to provide a level of slot expansion necessary in volume servers. Moreover, such single chassis systems are not readily expandable as the user's needs change.
The possibility of bussing between multiple modular chassis implicates some unique problem in the context of PCI. Specifically, using available PCI to PCI bridges, it is necessary to synchronize the clock system wide. Because PCI does not require a standard host clock signal, phase lock loops cannot be employed to synchronize both sides of the bridge. The shear physical dimension of a multi-chassis system makes such synchronization of a single clock domain even more problematic. These problems necessitated custom design for circuits to provide out of chassis slot expansion.
Additionally, the PCI bus specification requires four active low, level sensitive interrupt pins for all slots supported and defines these interrupts' use as hardware shareable. That means that multiple PCI devices can drive the same interrupt line or that multiple PCI interrupt lines can be driven by different devices but may result in a single interrupt being generated to the system interrupt controller to be serviced by a shared interrupt driver. Thus, as the number of slots amongst which the interrupts must be shared increases, the resources and overhead required to resolve the source of the interrupt also increases as the number of sharing slots increases.
It is therefore desirable to provide an apparatus which allows PCI slot expansion without unnecessarily increasing the cost of the host system. Such apparatus should be forward and backward compatible, without requiring customization to each specific system. The performance of an expanded slot must be maintained at an acceptably high level, and the system should be readily expandable to meet the demands of increasing processor power. It is also desirable to develop a way to simplify the interrupts generated by such an expanded system.
BRIEF DESCRIPTION OF THE DRAWINGS
Figure 1 shoes a block diagram of a host and expansion module of the invention.
Figure IA is a table of the signals and required pins in the cabled bus of the invention.
Figure 2 is a block diagram of the module interfaces of the instant invention.
Figure 3 is a diagram of the clock generation circuit for the expansion module of the invention.
Figure 4 is a table listing specifications of cables suitable for the instant invention.
Figure 4A is a table showing timing budgets of two possible operating point for the invention. SUMMARY OF THF INVENTION
The instant invention provides an apparatus and method for expanding the number of PCI slots available to a host system. By employing an asynchronous PCI to PCI bridge, host and expansion time domains are segregated. A cabled PCI bus responsive to a clock signal generated and controlled in the expansion module is used to carry the signals between independent host and expansion chassis. Because the expansion system is not dependent on the host clock or the functionalities of the host system, it is suitable for integration into existing system, and it will not increase the cost of a base host system. Thus, the invention provides ready expandability as needs change.
In one embodiment, the invention provides interrupt expansion in addition to slot expansion. This is accomplished by providing a means for connecting to the host APIC bus on the expansion card and a means of encoding the PCI interrupts generated by the expansion PCI slot into APIC on the expansion mother board. This expansion will reduce the overhead associated with servicing interrupts shared by the expanded slots.
DETAILED DESCRIPTION OF THE INVENTION
The present invention provides a method and apparatus for using a cabled PCI bus to provide an expansion of the number of PCI slots available to a host system. For the purpose of explanation, specific details are set forth to provide a thorough understanding of the present invention. However, it will be understood by one skilled in the art, from reading this disclosure, that the invention may be practiced without these details. Moreover, well known elements devices, process steps and the like are not set forth in order to avoid obscuring the invention.
Figure 1 shows a block diagram of a system incorporating the instant invention. The host system resides within a host chassis 1 and includes a host mother board 3. The host mother board has a CPU 5 connected to a memory 6 by a system bus 7. A bridge 8 is provided on the mother board to bridge between the system bus 7 and a host PCI bus 9. At 33 MHz, the PCI specification only permits 3 - 4 slots 10 along a single bus segment. By installing an expansion card 11 in at least one of the slots 10 on the host PCI bus 9, it is possible to expand the number of slots of the system as a whole.
The expansion card 11 has a primary expansion bridge (PEB) 12 described more fully with reference to Figure 2 below, and a cable connector 15, an exemplary embodiment employs a 100 pin cable connector. The expansion card also provides an optional APIC connector 14 to allow the card 11 to be connected to the APIC bus not shown on the host mother board 3. This allows for sufficient signal conductors to accommodate parallel transmission of all PCI required signals and adequate grounding. Figure IA is a table of the relevant PCI signals. The cable 16 is selected based on propagation speed down the cable 16 and cable skewing. It is desirable to choose a cable 16 with minimal skewing with maximum propagation speed. The cable 16 functions as a point to point PCI bus between the expansion side of the PEB 12 and the secondary expansion bridge (SEB) 19 which is described more fully below. The cable 16 should be well terminated at either end with impedances approximately equal to the characteristic impedance in the cable. In an exemplary embodiment, a six foot HIPPI cable with a characteristic impedance of 88 ± 5 ohms is used. HIPPI cable meets ANSI standards and includes 50 twisted pairs, thereby providing an adequate number of signal lines. It would be possible to use a smaller cable and lower pin count connector but such would limit possible functionality somewhat.
The expansion chassis 2 contains an expansion mother board 4 to which the cable 16 connects via connector 17. A PCI bus runs from the connector to the SEB 19. The clocking in the expansion system is provided by a clock generator 18 which is asynchronous with and independent of the host clock (not shown). The number of slots 21 available on the secondary PCI bus (SPB) 20 is determined by the speed of the clock signal generated. At 25 MHz, 8 - 12 slots are available, while at 33 MHz, only 3 - 4 slots would be available.
It is possible and contemplated as within the scope of this invention that multiple expansion modules could be coupled to a single host (one card per available PCI slot). It is also within the scope of the invention to cascade an expansion module off an expansion module.
Figure 2 more clearly sets forth the relationship between the PEB 12, Cable 16, and SEB 19. Figure 2 is divided into three clock domains. The host clock domain 30. the expansion clock domain 32, and an optional APIC clock domain 31. The instant invention employs an asynchronous bridge 33 between the host and expansion module. A PCI to PCI bridge comprises a primary bus interface and a secondary bus interface. In the case of an asynchronous bridge the primary interface is responsive to the host clock while the secondary interface is responsive to the expansion clock, thereby creating an asynchronous boundary 13 between the host clock domain 30 and expansion clock domain 32. At the most basic level this could be implemented with a pair of D flip flops for each relevant signal. As a practical matter to ensure data validity where clock rates vary it is desirable to provide some storage between the two interfaces. Inbound and outbound queues of 4x16 bytes have been found adequate. For further detail see PCI to PCI Bridge Spec. Revision 1.0, April 15, 1994.
In one exemplary embodiment, the host PCI bus is connected to an asynchronous PCI to PCI bridge 33 contained in PEB 12 on the expansion card. The host side of the bridge 33 operates in the host clock domain 30 while the expansion side is synchronous with the expansion clock domain 32. The PEB 12 also contains a demultiplexer 38 to demultiplex the 4 PCI supported interrupts coming from the expansion system. An optional APIC bus interface 36 can also be provided within the PEB 12, thereby expanding the interrupts available to the expansion system. Such interface must be asynchronous operating partially in the APIC clock domain 31 and partially in the expansion clock domain 32. Significantly, this option does not comply with PCI specification. Intelligent VO units like those described in co-pending application, Architecture for I/O Processor that Integrates a PCI-to-PCI Bridge, Serial No. supports these functionalities. Accordingly, one embodiment envisioned in the instant invention employs such an intelligent I/O unit as the PEB 12.
The expansion end of the asynchronous bridge 33 is coupled through a cabled PCI bus 16 to the SEB 19 on the expansion mother board 41. The cable 16 contains the PCI bus signals 44, the expansion domain clock signal 40, an SINT# 39. SINT #39 is not a standard PCI line. Rather, it is a line carrying the serialization of the standard PCI interrupts. One way to serialize this is to continuously synchronize the four standard PCI interrupt signals to the PCI clock and send the information across the interface on SINT# whenever a change occurs using a protocol of one start bit (low), INTA#, INTB#, INTC#, INTD#, odd parity and one stop bit (high) as shown in Figure 5. If an interrupt is unmasked in the I/O APIC, then that INT# line should not be serialized on the SINT# signal (i.e. it should be interpreted as inactive). In such case, the I/O APIC will handle distributing the interrupt to the host. The SINT# protocol will be driven continuously (with all interrupts inactive) during reset. The interrupt serializer will also send a new message after 16 clocks of inactivity.
SINT# is used by the PEB to decode the current value of INTA#, INTB#, INTC#, INTD#. Whenever the interrupt demux block sees SINT# go low, it will capture the data for the next four clocks and if the parity (5th cloth after Start) is good, use the data to update its current value for the four interrupt outputs. If bad parity is detected, the data will be ignored. This interrupt serialization process causes a worst case delay of 9 clocks for each level of expansion subsystem (2 for synchronization and 7 to send) which is 360 ns at 25 MHz. This is merely one simple way to serialize interrupts. Other serialization schemes will occur to one of ordinary skill in the art, such schemes are contemplated for use with the instant invention.
At the expansion end of cable 16, the SEB 19 contains a PCI to PCI bridge 34 which may be synchronous or asynchronous. SEB 19 also optionally contains an I O APIC 35 which expands the number of interrupts available for use by the expansion system, and reduces or eliminates the polling which would be required if all PCI slots in the combined host and expansion system shared only the four PCI provided interrupts. Finally, an interrupt steering device 37 is provided to either steer the PCI supported interrupts across the cable 16 to the demultiplexer 38, or if provided, steers slot interrupt into the VO APIC 35 which in turn buses the interrupt along the cable 16 to the APIC bus interface 36. Again, it is contemplated that an intelligent VO unit as described in co-pending application
Serial No. could be used to implement SEB 19. Also, on the expansion mother board 4 are the clock generation device 18 and the secondary PCI bus 45.
In Figure 2, eight slots 21 are shown on the secondary PCI bus 45. PCI does not define a maximum number of slots, rather it has rigidly defined electrical characteristics. Specifically, PCI defines that clock skew + clock to out at master + setup at target + settling time < clock period. In the clock generation scheme described below the time allotted for settling is used as flight time down the cable 16 thereby reducing the latency in the transaction between host and expansion modules. Since the introduction of each slot 21 increases the capacitance of the system thereby negatively affecting the transition speed between states, i.e., the settling time, a slower clock increases the time available for settling and accordingly increase the number of loads (slots) the system can handle. If operation is at 25 MHz, it is contemplated that 8 - 12 slots could be provided.
Figure 3 shows the clock generation of the instant invention, an oscillator 50 generates a clock signal of a desired frequency up to 33 MHz. It will be recognized that an oscillator need not be employed to generate the clock signal, any conventional method of generating a signal of the desired frequency can be employed. In an exemplary embodiment, the oscillator 50 generates a 25 MHz clock signal.
The present application requires multiple copies of the clock be generated from a single source. Figure 3 shows the clock signal going to the cable 16 and ten other lines 58. This is adequate for right slots 21 and the SEB 19. It is necessary that the clock used at the host interface end of the cable 15 and expansion chassis interfaces 58 arrive within the clock skew timing specifications. To this end, low skew clock drivers 51 are employed along each line to minimize skew along the different lines, and a delay element 52 is introduced between the local lines and the remote interface 15. By matching the propagation delay in the cable 16 to the host (remote) interface 15 with a delay element 52, it is possible to achieve the desired synchronization of the clocks at the respective interfaces 15 and 58. To select an appropriate delay line 52 value two options exist, one can either delay the local lines by the propagation delay in the cable or delay the signal to the cable by the period of its clock signal minus the propagation delay. Figure 3 depicts the delay element 52 introduced along the local lines. It is contemplated that either a passive delay line or suitable high speed buffer might be employed to accomplish the desired delay. The maximum clock skew between slots 21 on the expansion mother board 4 and the SEB 19 is 2 ns. Figure 4 reflects possible selections which will satisfy the PCI specifications. Significantly, each clock signal line should be matched as closely as possible. Thus, the same number of buffer drivers 51 are employed along each line. Impedances 56 should be matched with the characteristic impedance of the clock traces on expansion motherboard 4. Moreover, the lengths of printed circuit board traces from the buffers 51 to their destinations should be as closely matched as possible, including the trace from the buffer driving the cable connection. This can be done by increasing the lengtii of all traces to match which ever trace has the longest length naturally. The most critical length match is between the clock going to the SEB 19 and the one driving the PEB 12 through the cable 16. Appropriately selecting delay 52 line value will improve this match.
The electrical connection scheme uses the bridge chips (i.e., PEB and SEB) to connect to the cable using series termination. This termination is external. The series termination value is equal to the impedance of the cable minus the impedance of the driver. The source end of the cable is driving with a 1/2 voltage incident waveform which doubles to a full voltage waveform due to the reflection coefficient of 1 it encounters at the destination end of the cable. When driving the cable the series termination forms a half wave incident waveform which encounters a reflection coefficient of one. In an embodiment employing a 6 foot cable, the characteristic impedance of such cable is 88 ± 5 ohms. Accordingly appropriate termination impedances can be selected with reference to the impedance of the selected driver.
It would also be possible to place the clock generator 18 on the expansions card 11. While the same rules discussed above would apply to such placement, maintaining the required coordination of the signals becomes more problematic as the number of remote signals to be coordinated increases. Nevertheless, such placement is within the scope and contemplation of the invention.
In the foregoing specification, the invention has been described with reference to specific embodiments thereof. It will however be evident that various modifications and changes made thereto without departing from the broader spirit and scope of the invention as set forth in the appended claims. The specification and drawings are accordingly, to be regarded in an illustrative rather than a restrictive sense. Therefore, the scope of the invention should be limited only by the appended claims.

Claims

CLAIMSWhat is claimed is:
1. An apparatus for providing PCI slot expansion comprising: an expansion card having disposed thereon an asynchronous PCI to PCI bridge with a host side and an expansion side for coupling to a host motherboard; an expansion motherboard having a plurality of PCI slots; a cabled PCI bus for coupling the expansion card to the expansion motherboard; a clock generator for providing a clock signal to the expansion motherboard and the expansion side of the asynchronous PCI to PCI bridge.
2. The apparatus of claim 1 wherein the clock generator is disposed on the expansion mother board.
3. The apparatus of claim 2 wherein the clock generator generates a 25 MHz signal.
4. The apparatus of claim 2 wherein the expansion mother board further comprises a secondary expansion bridge; and coupling the cabled signals to an expansion PCI bus having a plurality of slots.
5. The apparatus of claim 4 wherein the secondary expansion bridge further comprises an interrupt steering circuit and an VO APIC; and the expansion card further comprises an APIC interface.
6. The apparatus of claim 1 wherein the asynchronous bridge is an intelligent VO unit.
7. The apparatus of claim 4 wherein the secondary expansion bridge is an intelligent VO unit.
8. A modular computer system providing an expanded number of PCI slots comprising: a host module having a host motherboard with a CPU disposed thereon; a PCI bus disposed on the host motherboard responsive to a host clock and having a plurality of host PCI slots; an expansion card for coupling to one of the plurality of host PCI slots; an expansion module having an expansion motherboard, the expansion motherboard having an expansion PCI bus with a plurality of expansion PCI slots responsive to an expansion clock signal; and a cabled PCI bus for connecting the host and expansion modules.
9. The modular computer system of claim 8 further comprising a primary expansion bridge for providing an interface between the cabled bus and the host PCI bus; a secondary expansion bridge for providing an interface between the cabled bus and the expansion PCI bus; a clock generator disposed within the expansion module for generation of the expansion clock signal.
10. The modular computer system of claim 9 wherein the primary expansion bridge comprises an asynchronous PCI to PCI bridge and a demultiplexor; and the secondary expansion bridge comprises a PCI to PCI bridge and an interrupt steering unit.
11. The modular computer system of claim 9 wherein the expansion clock signal is 25 MHz.
12. The modular computer system of claim 9 wherein the cabled bus comprises a 100 conductor cable with a 100 pin connector at each end.
13. The modular computer system of claim 9 wherein the primary expansion bridge is an intelligent VO unit.
14. The modular computer system of claim 10 wherein the primary expansion bridge further comprises: an APIC interface unit; and the secondary expansion bridge further comprises an I/O APIC unit.
15. A method of providing modular expansion of PCI slots in a computer system comprising the steps of: installing an expansion card in a PCI slot of a host module; connecting the expansion card to an expansion module by a cable; generating an expansion clock signal independent of a host clock signal; segregating the host and expansion clock signals at the expansion card; and cabling PCI transmissions between the modules along the cable.
16. The method of claim 15 wherein the segregating step is performed by an asynchronous PCI to PCI bridge.
17. The method of claim 15 wherein the step of generating further comprises the step of coordinating arrival of the expansion clock signal at a plurality of local and remote interfaces.
18. The method of claim 15 wherein the cable is terminated and operates as a point to point PCI bus.
19. The method of claim 17 further comprising providing an APIC bus interface on the expansion card; disposing an I/O APIC unit within the expansion module; passing interrupts generated in the expansion module to a host APIC bus.
20. The method of claim 15 wherein an intelligent VO unit performs the segregating step.
21. An apparatus for providing PCI slot expansion comprising: means for segregating a host and an expansion time domain for installing in a host system PCI slot; means for transmitting PCI signals over a predetermined distance; means for generating a clock signal for the expansion time domain; an expansion PCI bus responsive to the clock of the expansion time domain, said expansion bus having a plurality of PCI slots; wherein the means for transmitting more PCI signals from the expansion bus to the means for segregating, and the means for segregating passes the signals between the time domains.
PCT/US1996/010460 1995-06-15 1996-06-17 An apparatus and method for providing remote pci slot expansion WO1997000481A1 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR1019970709312A KR100291051B1 (en) 1995-06-15 1996-06-17 An apparatus and method for providing remote pci slot expansion
EP96921651A EP0832458B1 (en) 1995-06-15 1996-06-17 An apparatus and method for providing remote pci slot expansion
DE69636519T DE69636519D1 (en) 1995-06-15 1996-06-17 DEVICE AND METHOD FOR EXTENDING REMOTE PCI SLOTS
JP9503396A JPH11514112A (en) 1995-06-15 1996-06-17 Apparatus and method for enabling remote PCI slot expansion
AU62818/96A AU6281896A (en) 1995-06-15 1996-06-17 An apparatus and method for providing remote pci slot expansion
HK98110832A HK1009866A1 (en) 1995-06-15 1998-09-22 An apparatus and method for providing remote pci slot expansion

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/490,778 1995-06-15
US08/490,778 US5696949A (en) 1995-06-15 1995-06-15 System for PCI slots expansion using asynchronous PCI-to-PCI bridge with clock generator for providing clock signal to the expansion mother board and expansion side of bridge

Publications (1)

Publication Number Publication Date
WO1997000481A1 true WO1997000481A1 (en) 1997-01-03

Family

ID=23949425

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1996/010460 WO1997000481A1 (en) 1995-06-15 1996-06-17 An apparatus and method for providing remote pci slot expansion

Country Status (9)

Country Link
US (3) US5696949A (en)
EP (1) EP0832458B1 (en)
JP (1) JPH11514112A (en)
KR (1) KR100291051B1 (en)
CN (1) CN1098492C (en)
AU (1) AU6281896A (en)
DE (1) DE69636519D1 (en)
HK (1) HK1009866A1 (en)
WO (1) WO1997000481A1 (en)

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1998048358A2 (en) * 1997-04-22 1998-10-29 Nokia Networks Oy Adding plug-in unit slots to a high capacity bus
WO2000058847A1 (en) * 1999-03-26 2000-10-05 Koninklijkje Philips Electronics N.V. System bus with serially connected pci interfaces
WO2001082090A2 (en) * 2000-04-19 2001-11-01 Mobility Electronics Extended cardbus/pc card controller with split-bridge technology
US6321335B1 (en) 1998-10-30 2001-11-20 Acqis Technology, Inc. Password protected modular computer method and device
AU751826B2 (en) * 2000-02-14 2002-08-29 Mobility Electronics, Inc. Linked Bridge
USRE42984E1 (en) 1999-05-14 2011-11-29 Acqis Technology, Inc. Data security method and device for computer modules
US9529769B2 (en) 1999-05-14 2016-12-27 Acqis Llc Computer system including CPU or peripheral bridge directly connected to a low voltage differential signal channel that communicates serial bits of a peripheral component interconnect bus transaction in opposite directions
USRE48365E1 (en) 2006-12-19 2020-12-22 Mobile Motherboard Inc. Mobile motherboard
CN113032317A (en) * 2021-03-30 2021-06-25 北京睿芯高通量科技有限公司 Method and device for PCIE (peripheral component interface express) signal expansion based on server

Families Citing this family (107)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5838935A (en) * 1995-06-15 1998-11-17 Intel Corporation Method and apparatus providing programmable decode modes for secondary PCI bus interfaces
US5933613A (en) * 1995-07-06 1999-08-03 Hitachi, Ltd. Computer system and inter-bus control circuit
US5684434A (en) * 1995-10-30 1997-11-04 Cypress Semiconductor Erasable and programmable single chip clock generator
US5819051A (en) * 1995-12-29 1998-10-06 Compaq Computer Corporation Low speed serial bus protocol and circuitry
IL126762A0 (en) * 1996-05-01 1999-08-17 Lilly Co Eli Halo-substituted protein kinase c inhibitors
GB9622684D0 (en) 1996-10-31 1997-01-08 Sgs Thomson Microelectronics An integrated circuit device and method of communication therwith
US5761461A (en) * 1996-12-13 1998-06-02 International Business Machines Corporation Method and system for preventing peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a data processing system
US5761462A (en) * 1996-12-13 1998-06-02 International Business Machines Corporation Method and system for supporting peripheral component interconnect (PCI) peer-to-peer access across multiple PCI host bridges within a data-processing system
US6434611B1 (en) * 1996-12-20 2002-08-13 Mci Communications Corporation System and method for message-based real-time reconfiguration of a network by broadcasting an activation signal to activate a new connection configuration
US5890015A (en) * 1996-12-20 1999-03-30 Intel Corporation Method and apparatus for implementing a wireless universal serial bus host controller by interfacing a universal serial bus hub as a universal serial bus device
US5952890A (en) 1997-02-05 1999-09-14 Fox Enterprises, Inc. Crystal oscillator programmable with frequency-defining parameters
US5960405A (en) 1997-02-05 1999-09-28 Fox Enterprises, Inc. Worldwide marketing logistics network including strategically located centers for frequency programming crystal oscillators to customer specification
JPH10254827A (en) * 1997-03-06 1998-09-25 Canon Inc Extension card, access control method for extension card and storage medium stored with computer-readable program
US5923858A (en) * 1997-05-01 1999-07-13 Cirrus Logic, Inc. Method and apparatus to interface a peripheral device operating in an internal clock domain to a PCI bus operating in a PCI clock domain
US6145098A (en) 1997-05-13 2000-11-07 Micron Electronics, Inc. System for displaying system status
US6192434B1 (en) 1997-05-13 2001-02-20 Micron Electronics, Inc System for hot swapping a programmable adapter by using a programmable processor to selectively disabling and enabling power thereto upon receiving respective control signals
US6243773B1 (en) 1997-05-13 2001-06-05 Micron Electronics, Inc. Configuration management system for hot adding and hot replacing devices
US6272648B1 (en) 1997-05-13 2001-08-07 Micron Electronics, Inc. System for communicating a software-generated pulse waveform between two servers in a network
US6170067B1 (en) 1997-05-13 2001-01-02 Micron Technology, Inc. System for automatically reporting a system failure in a server
US6249885B1 (en) 1997-05-13 2001-06-19 Karl S. Johnson Method for managing environmental conditions of a distributed processor system
US6247079B1 (en) 1997-05-13 2001-06-12 Micron Electronics, Inc Apparatus for computer implemented hot-swap and hot-add
US6202160B1 (en) 1997-05-13 2001-03-13 Micron Electronics, Inc. System for independent powering of a computer system
US6173346B1 (en) 1997-05-13 2001-01-09 Micron Electronics, Inc. Method for hot swapping a programmable storage adapter using a programmable processor for selectively enabling or disabling power to adapter slot in response to respective request signals
US6182180B1 (en) 1997-05-13 2001-01-30 Micron Electronics, Inc. Apparatus for interfacing buses
US6269417B1 (en) 1997-05-13 2001-07-31 Micron Technology, Inc. Method for determining and displaying the physical slot number of an expansion bus device
US6249828B1 (en) 1997-05-13 2001-06-19 Micron Electronics, Inc. Method for the hot swap of a mass storage adapter on a system including a statically loaded adapter driver
US6249834B1 (en) * 1997-05-13 2001-06-19 Micron Technology, Inc. System for expanding PCI bus loading capacity
US6134668A (en) 1997-05-13 2000-10-17 Micron Electronics, Inc. Method of selective independent powering of portion of computer system through remote interface from remote interface power supply
US6073255A (en) 1997-05-13 2000-06-06 Micron Electronics, Inc. Method of reading system log
US6304929B1 (en) 1997-05-13 2001-10-16 Micron Electronics, Inc. Method for hot swapping a programmable adapter by using a programmable processor to selectively disabling and enabling power thereto upon receiving respective control signals
US6195717B1 (en) 1997-05-13 2001-02-27 Micron Electronics, Inc. Method of expanding bus loading capacity
US6219734B1 (en) 1997-05-13 2001-04-17 Micron Electronics, Inc. Method for the hot add of a mass storage adapter on a system including a statically loaded adapter driver
US6324608B1 (en) 1997-05-13 2001-11-27 Micron Electronics Method for hot swapping of network components
US6338150B1 (en) 1997-05-13 2002-01-08 Micron Technology, Inc. Diagnostic and managing distributed processor system
US6253334B1 (en) 1997-05-13 2001-06-26 Micron Electronics, Inc. Three bus server architecture with a legacy PCI bus and mirrored I/O PCI buses
US6269412B1 (en) 1997-05-13 2001-07-31 Micron Technology, Inc. Apparatus for recording information system events
US6247080B1 (en) 1997-05-13 2001-06-12 Micron Electronics, Inc. Method for the hot add of devices
US6179486B1 (en) 1997-05-13 2001-01-30 Micron Electronics, Inc. Method for hot add of a mass storage adapter on a system including a dynamically loaded adapter driver
US6266721B1 (en) 1997-05-13 2001-07-24 Micron Electronics, Inc. System architecture for remote access and control of environmental management
US6363497B1 (en) 1997-05-13 2002-03-26 Micron Technology, Inc. System for clustering software applications
US6170028B1 (en) 1997-05-13 2001-01-02 Micron Electronics, Inc. Method for hot swapping a programmable network adapter by using a programmable processor to selectively disabling and enabling power thereto upon receiving respective control signals
US6134673A (en) 1997-05-13 2000-10-17 Micron Electronics, Inc. Method for clustering software applications
US6122758A (en) 1997-05-13 2000-09-19 Micron Electronics, Inc. System for mapping environmental resources to memory for program access
US6282673B1 (en) 1997-05-13 2001-08-28 Micron Technology, Inc. Method of recording information system events
US6202111B1 (en) 1997-05-13 2001-03-13 Micron Electronics, Inc. Method for the hot add of a network adapter on a system including a statically loaded adapter driver
US6418492B1 (en) 1997-05-13 2002-07-09 Micron Electronics Method for computer implemented hot-swap and hot-add
US6292905B1 (en) 1997-05-13 2001-09-18 Micron Technology, Inc. Method for providing a fault tolerant network using distributed server processes to remap clustered network resources to other servers during server failure
US6499073B1 (en) 1997-05-13 2002-12-24 Micron Electronics, Inc. System using programmable processor for selectively enabling or disabling power to adapter in response to respective request signals
US6163849A (en) 1997-05-13 2000-12-19 Micron Electronics, Inc. Method of powering up or powering down a server to a maintenance state
US6138250A (en) 1997-05-13 2000-10-24 Micron Electronics, Inc. System for reading system log
US6330690B1 (en) 1997-05-13 2001-12-11 Micron Electronics, Inc. Method of resetting a server
US5987554A (en) 1997-05-13 1999-11-16 Micron Electronics, Inc. Method of controlling the transfer of information across an interface between two buses
US6243838B1 (en) 1997-05-13 2001-06-05 Micron Electronics, Inc. Method for automatically reporting a system failure in a server
US20020052994A1 (en) * 1997-08-18 2002-05-02 Liaqat Y. Khan Section access for pc hard drive and the like
US6154835A (en) 1997-10-01 2000-11-28 Micron Electronics, Inc. Method for automatically configuring and formatting a computer system and installing software
US6199173B1 (en) 1997-10-01 2001-03-06 Micron Electronics, Inc. Method for mapping environmental resources to memory for program access
US6138179A (en) 1997-10-01 2000-10-24 Micron Electronics, Inc. System for automatically partitioning and formatting a primary hard disk for installing software in which selection of extended partition size is not related to size of hard disk
US6088816A (en) 1997-10-01 2000-07-11 Micron Electronics, Inc. Method of displaying system status
US6263387B1 (en) 1997-10-01 2001-07-17 Micron Electronics, Inc. System for automatically configuring a server after hot add of a device
US6065053A (en) 1997-10-01 2000-05-16 Micron Electronics, Inc. System for resetting a server
US6212585B1 (en) 1997-10-01 2001-04-03 Micron Electronics, Inc. Method of automatically configuring a server after hot add of a device
US6275950B1 (en) * 1997-10-28 2001-08-14 Twinhead International Corp. Adjustable PCI asynchronous clock device
US6233638B1 (en) * 1998-03-20 2001-05-15 Micron Electronics, Inc. System for configuring peer devices
US6122677A (en) 1998-03-20 2000-09-19 Micron Technology, Inc. Method of shortening boot uptime in a computer system
US6216224B1 (en) * 1998-06-05 2001-04-10 Micron Technology Inc. Method for read only memory shadowing
US6330667B1 (en) * 1998-06-05 2001-12-11 Micron Technology, Inc. System for read only memory shadowing circuit for copying a quantity of rom data to the ram prior to initialization of the computer system
TW382089B (en) * 1998-06-16 2000-02-11 Asustek Comp Inc System clock frequency switching device and method for computer motherboard
US6223234B1 (en) 1998-07-17 2001-04-24 Micron Electronics, Inc. Apparatus for the hot swap and add of input/output platforms and devices
US6205503B1 (en) 1998-07-17 2001-03-20 Mallikarjunan Mahalingam Method for the hot swap and add of input/output platforms and devices
US6088752A (en) * 1998-08-06 2000-07-11 Mobility Electronics, Inc. Method and apparatus for exchanging information between buses in a portable computer and docking station through a bridge employing a serial link
US7734852B1 (en) 1998-08-06 2010-06-08 Ahern Frank W Modular computer system
US6070214A (en) * 1998-08-06 2000-05-30 Mobility Electronics, Inc. Serially linked bus bridge for expanding access over a first bus to a second bus
US6188255B1 (en) 1998-09-28 2001-02-13 Cypress Semiconductor Corp. Configurable clock generator
US6584519B1 (en) * 1998-12-22 2003-06-24 Canon Kabushiki Kaisha Extender for universal serial bus
US6311247B1 (en) 1999-01-15 2001-10-30 Hewlett Packard Company System for bridging a system bus with multiple PCI buses
US6453426B1 (en) * 1999-03-26 2002-09-17 Microsoft Corporation Separately storing core boot data and cluster configuration data in a server cluster
US6401120B1 (en) * 1999-03-26 2002-06-04 Microsoft Corporation Method and system for consistent cluster operational data in a server cluster using a quorum of replicas
US7774469B2 (en) 1999-03-26 2010-08-10 Massa Michael T Consistent cluster operational data in a server cluster using a quorum of replicas
JP2001014269A (en) 1999-06-29 2001-01-19 Toshiba Corp Computer system
US6574691B1 (en) 1999-07-28 2003-06-03 Koninklijke Philips Electronics N.V. Apparatus and method for interfacing a non-sequential 486 interface burst interface to a sequential ASB interface
US6662219B1 (en) 1999-12-15 2003-12-09 Microsoft Corporation System for determining at subgroup of nodes relative weight to represent cluster by obtaining exclusive possession of quorum resource
US6788073B2 (en) * 1999-12-23 2004-09-07 Dell Products L.P. Data processing systems having mismatched impedance components
EP1653373B1 (en) 2000-02-14 2013-11-13 Tao Logic Systems LLC Bus bridge
AU751695B2 (en) 2000-02-14 2002-08-22 Mobility Electronics, Inc. Docking system and method
EP1158735A1 (en) * 2000-05-24 2001-11-28 Motorola, Inc. TDMA bus interface, system for communicating data, and method
US6963941B1 (en) * 2000-05-31 2005-11-08 Micron Technology, Inc. High speed bus topology for expandable systems
US6668300B1 (en) 2000-09-14 2003-12-23 Bae Systems Information And Electronic Systems Integration Inc. Computer device having multiple linked parallel busses and associated method
US7103696B2 (en) 2001-04-04 2006-09-05 Adaptec, Inc. Circuit and method for hiding peer devices in a computer bus
US6748458B2 (en) * 2001-08-31 2004-06-08 Hewlett-Packard Development Company, L.P. Modular input/output expansion system for an external computer
US6782463B2 (en) 2001-09-14 2004-08-24 Intel Corporation Shared memory array
US6829692B2 (en) 2001-09-14 2004-12-07 Intel Corporation System and method for providing data to multi-function memory
US7277952B2 (en) * 2001-09-28 2007-10-02 Microsoft Corporation Distributed system resource protection via arbitration and ownership
US6985990B2 (en) * 2002-03-29 2006-01-10 International Business Machines Corporation System and method for implementing private devices on a secondary peripheral component interface
US20040049618A1 (en) * 2002-09-10 2004-03-11 Schmisseur Mark A. Configuration of private devices and device functions
US7100034B2 (en) * 2003-05-23 2006-08-29 Hewlett-Packard Development Company, L.P. System for selecting another processor to be the boot strap processor when the default boot strap processor does not have local memory
US20050251609A1 (en) * 2004-05-04 2005-11-10 Horng-Yee Chou Removable peripheral device
US7356680B2 (en) * 2005-01-22 2008-04-08 Telefonaktiebolaget L M Ericsson (Publ) Method of loading information into a slave processor in a multi-processor system using an operating-system-friendly boot loader
US7404114B2 (en) * 2005-02-15 2008-07-22 International Business Machines Corporation System and method for balancing delay of signal communication paths through well voltage adjustment
US8073042B1 (en) 2005-04-13 2011-12-06 Cypress Semiconductor Corporation Recursive range controller
KR101430687B1 (en) * 2007-09-28 2014-08-18 삼성전자주식회사 Multi processor system having direct access booting operation and direct access booting method therefore
US8245024B2 (en) * 2009-08-21 2012-08-14 Micron Technology, Inc. Booting in systems having devices coupled in a chained configuration
US8429391B2 (en) 2010-04-16 2013-04-23 Micron Technology, Inc. Boot partitions in memory devices and systems
TWI606341B (en) 2016-03-23 2017-11-21 慧榮科技股份有限公司 Storage device and reset method thereof
US10289572B2 (en) * 2016-10-14 2019-05-14 General Electric Company Industrial control adjacent input-output modules and methods thereof
WO2019236057A1 (en) 2018-06-05 2019-12-12 Hewlett-Packard Development Company, L.P. Route demultiplexed signal pairs
US10915329B2 (en) * 2019-02-24 2021-02-09 Winbond Electronics Corporation Delayed reset for code execution from memory device
CN110457247A (en) * 2019-07-03 2019-11-15 天津市英贝特航天科技有限公司 A kind of high speed SRIO bus conversion module based on FMC standard interface

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4882702A (en) * 1986-03-31 1989-11-21 Allen-Bradley Company, Inc. Programmable controller with I/O expansion module located in one of I/O module positions for communication with outside I/O modules
US5191657A (en) * 1989-11-09 1993-03-02 Ast Research, Inc. Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry standard synchronous bus

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4413319A (en) * 1981-03-09 1983-11-01 Allen-Bradley Company Programmable controller for executing block transfer with remote I/O interface racks
US4679166A (en) * 1983-01-17 1987-07-07 Tandy Corporation Co-processor combination
DE3639571A1 (en) * 1986-11-20 1988-06-01 Standard Elektrik Lorenz Ag METHOD AND CIRCUIT ARRANGEMENT FOR CHARGING A SECONDARY COMPUTER
IT1228728B (en) * 1989-03-15 1991-07-03 Bull Hn Information Syst MULTIPROCESSOR SYSTEM WITH GLOBAL DATA REPLICATION AND TWO LEVELS OF ADDRESS TRANSLATION UNIT.
US5497497A (en) * 1989-11-03 1996-03-05 Compaq Computer Corp. Method and apparatus for resetting multiple processors using a common ROM
AU661016B2 (en) * 1991-06-26 1995-07-13 Samsung Electronics Co., Ltd. Multiprocessor distributed initialization and self-test system
US5335329A (en) * 1991-07-18 1994-08-02 Texas Microsystems, Inc. Apparatus for providing DMA functionality to devices located in a bus expansion chassis
US5371880A (en) * 1992-05-13 1994-12-06 Opti, Inc. Bus synchronization apparatus and method
US5542055A (en) * 1993-05-28 1996-07-30 International Business Machines Corp. System for counting the number of peripheral buses in each hierarch connected to primary bus for creating map of peripheral buses to locate peripheral devices
US5535417A (en) * 1993-09-27 1996-07-09 Hitachi America, Inc. On-chip DMA controller with host computer interface employing boot sequencing and address generation schemes
US5586297A (en) * 1994-03-24 1996-12-17 Hewlett-Packard Company Partial cache line write transactions in a computing system with a write back cache
US5548730A (en) * 1994-09-20 1996-08-20 Intel Corporation Intelligent bus bridge for input/output subsystems in a computer system
US5495569A (en) * 1994-12-30 1996-02-27 Compaq Computer Corp. Circuit for ensuring that a local interrupt controller in a microprocessor is powered up active
US5579277A (en) * 1995-05-01 1996-11-26 Apple Computer, Inc. System and method for interleaving memory banks
US5603051A (en) * 1995-06-06 1997-02-11 Hewlett-Packard Company Input/output processor with a local memory providing shared resources for a plurality of input/output interfaces on an I/O bus
US5590377A (en) * 1995-06-07 1996-12-31 Ast Research, Inc. Automatic control of distributed DMAs in a PCI bus system supporting dual ISA buses

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4882702A (en) * 1986-03-31 1989-11-21 Allen-Bradley Company, Inc. Programmable controller with I/O expansion module located in one of I/O module positions for communication with outside I/O modules
US5191657A (en) * 1989-11-09 1993-03-02 Ast Research, Inc. Microcomputer architecture utilizing an asynchronous bus between microprocessor and industry standard synchronous bus

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
PC SYSTEM ARCHITECHTURE SERIES, November 1995, SHANLEY et al., "PCI System Architechture", pages 381-387. *
See also references of EP0832458A4 *

Cited By (26)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6356967B1 (en) 1997-04-22 2002-03-12 Nokia Networks Oy Adding plug-in unit slots to a high capacity bus
WO1998048358A3 (en) * 1997-04-22 1999-02-11 Nokia Telecommunications Oy Adding plug-in unit slots to a high capacity bus
WO1998048358A2 (en) * 1997-04-22 1998-10-29 Nokia Networks Oy Adding plug-in unit slots to a high capacity bus
USRE41294E1 (en) 1998-10-30 2010-04-27 Acqis Techonology, Inc. Password protected modular computer method and device
USRE44933E1 (en) 1998-10-30 2014-06-03 Acqis Llc Password protected modular computer method and device
US6321335B1 (en) 1998-10-30 2001-11-20 Acqis Technology, Inc. Password protected modular computer method and device
USRE43119E1 (en) 1998-10-30 2012-01-17 Acqis Llc Password protected modular computer method and device
USRE42814E1 (en) 1998-10-30 2011-10-04 Acqis Technology, Inc. Password protected modular computer method and device
USRE41961E1 (en) 1998-10-30 2010-11-23 Acqis Technology, Inc. Password protected modular computer method and device
USRE41076E1 (en) * 1998-10-30 2010-01-12 Acqis Technology, Inc. Password protected modular computer method and device
WO2000058847A1 (en) * 1999-03-26 2000-10-05 Koninklijkje Philips Electronics N.V. System bus with serially connected pci interfaces
US6434654B1 (en) 1999-03-26 2002-08-13 Koninklijke Philips Electronics N.V. System bus with a variable width selectivity configurable at initialization
US9703750B2 (en) 1999-05-14 2017-07-11 Acqis Llc Computer system including CPU or peripheral bridge directly connected to a low voltage differential signal channel that communicates serial bits of a peripheral component interconnect bus transaction in opposite directions
US9529769B2 (en) 1999-05-14 2016-12-27 Acqis Llc Computer system including CPU or peripheral bridge directly connected to a low voltage differential signal channel that communicates serial bits of a peripheral component interconnect bus transaction in opposite directions
USRE46947E1 (en) 1999-05-14 2018-07-10 Acqis Llc Data security method and device for computer modules
USRE42984E1 (en) 1999-05-14 2011-11-29 Acqis Technology, Inc. Data security method and device for computer modules
US9529768B2 (en) 1999-05-14 2016-12-27 Acqis Llc Computer system including CPU or peripheral bridge directly connected to a low voltage differential signal channel that communicates serial bits of a peripheral component interconnect bus transaction in opposite directions
USRE43171E1 (en) 1999-05-14 2012-02-07 Acqis Llc Data security method and device for computer modules
AU751826B2 (en) * 2000-02-14 2002-08-29 Mobility Electronics, Inc. Linked Bridge
WO2001082090A3 (en) * 2000-04-19 2002-02-21 Mobility Electronics Extended cardbus/pc card controller with split-bridge technology
USRE41494E1 (en) 2000-04-19 2010-08-10 Ahern Frank W Extended cardbus/PC card controller with split-bridge technology
WO2001082090A2 (en) * 2000-04-19 2001-11-01 Mobility Electronics Extended cardbus/pc card controller with split-bridge technology
EP1801704A3 (en) * 2000-04-19 2008-10-29 Tao Logic Systems LLC Extended cardbus/PC card controller with split-bridge technology
EP1801704A2 (en) * 2000-04-19 2007-06-27 Tao Logic Systems LLC Extended cardbus/PC card controller with split-bridge technology
USRE48365E1 (en) 2006-12-19 2020-12-22 Mobile Motherboard Inc. Mobile motherboard
CN113032317A (en) * 2021-03-30 2021-06-25 北京睿芯高通量科技有限公司 Method and device for PCIE (peripheral component interface express) signal expansion based on server

Also Published As

Publication number Publication date
HK1009866A1 (en) 1999-06-11
JPH11514112A (en) 1999-11-30
US5835784A (en) 1998-11-10
CN1098492C (en) 2003-01-08
AU6281896A (en) 1997-01-15
KR100291051B1 (en) 2001-08-07
EP0832458B1 (en) 2006-09-06
CN1187890A (en) 1998-07-15
DE69636519D1 (en) 2006-10-19
EP0832458A4 (en) 2002-07-24
KR19990022843A (en) 1999-03-25
US5696949A (en) 1997-12-09
US5954821A (en) 1999-09-21
EP0832458A1 (en) 1998-04-01

Similar Documents

Publication Publication Date Title
EP0832458B1 (en) An apparatus and method for providing remote pci slot expansion
US6625687B1 (en) Memory module employing a junction circuit for point-to-point connection isolation, voltage translation, data synchronization, and multiplexing/demultiplexing
US6295568B1 (en) Method and system for supporting multiple local buses operating at different frequencies
US5781747A (en) Method and apparatus for extending the signal path of a peripheral component interconnect bus to a remote location
US5404460A (en) Method for configuring multiple identical serial I/O devices to unique addresses through a serial bus
US6317352B1 (en) Apparatus for implementing a buffered daisy chain connection between a memory controller and memory modules
US7818487B2 (en) Multiple module computer system and method using differential signal channel including unidirectional, serial bit channels
US5392407A (en) Multi-port processor with peripheral component interconnect port and rambus port
US5122691A (en) Integrated backplane interconnection architecture
US6061754A (en) Data bus having switch for selectively connecting and disconnecting devices to or from the bus
US6081863A (en) Method and system for supporting multiple peripheral component interconnect PCI buses by a single PCI host bridge within a computer system
US5502824A (en) Peripheral component interconnect &#34;always on&#34; protocol
WO1996017302A1 (en) Bridge between two buses
JPS6341918A (en) Ic clock bus system
US6473822B1 (en) Digital signal processing apparatus
US6067590A (en) Data bus agent including a storage medium between a data bus and the bus agent device
US5644734A (en) Method and apparatus for multiplexing bus connector signals with sideband signals
US20120223749A1 (en) Clock synchronization circuit and semiconductor integrated circuit
US6640277B1 (en) Input staging logic for latching source synchronous data
US6836810B1 (en) Backplane system using incident waveform switching
US5590130A (en) Bus protocol using separate clocks for arbitration and data transfer
KR100249337B1 (en) High speed pci utilizing ttl compatible signaling
US6606675B1 (en) Clock synchronization in systems with multi-channel high-speed bus subsystems
US6557064B1 (en) Set up time adjust
US6668300B1 (en) Computer device having multiple linked parallel busses and associated method

Legal Events

Date Code Title Description
WWE Wipo information: entry into national phase

Ref document number: 96194775.6

Country of ref document: CN

AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AT AU AZ BB BG BR BY CA CH CN CZ CZ DE DE DK DK EE EE ES FI FI GB GE HU IL IS JP KE KG KP KR KZ LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SK TJ TM TR TT UA UG US UZ VN AM AZ BY KG KZ MD RU TJ TM

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): KE LS MW SD SZ UG AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE

DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
121 Ep: the epo has been informed by wipo that ep was designated in this application
WWE Wipo information: entry into national phase

Ref document number: 1996921651

Country of ref document: EP

WWE Wipo information: entry into national phase

Ref document number: 1019970709312

Country of ref document: KR

ENP Entry into the national phase

Ref document number: 1997 503396

Country of ref document: JP

Kind code of ref document: A

WWP Wipo information: published in national office

Ref document number: 1996921651

Country of ref document: EP

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

NENP Non-entry into the national phase

Ref country code: CA

WWP Wipo information: published in national office

Ref document number: 1019970709312

Country of ref document: KR

WWG Wipo information: grant in national office

Ref document number: 1019970709312

Country of ref document: KR

WWG Wipo information: grant in national office

Ref document number: 1996921651

Country of ref document: EP