WO1997003549A3 - Prioritized access to shared buffers - Google Patents
Prioritized access to shared buffers Download PDFInfo
- Publication number
- WO1997003549A3 WO1997003549A3 PCT/US1996/011920 US9611920W WO9703549A3 WO 1997003549 A3 WO1997003549 A3 WO 1997003549A3 US 9611920 W US9611920 W US 9611920W WO 9703549 A3 WO9703549 A3 WO 9703549A3
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- WO
- WIPO (PCT)
- Prior art keywords
- link
- shared
- buffer resource
- priority
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- Prior art date
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
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- G06—COMPUTING; CALCULATING OR COUNTING
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- H04L7/041—Speed or phase control by synchronisation signals using special codes as synchronising signal
- H04L7/046—Speed or phase control by synchronisation signals using special codes as synchronising signal using a dotting sequence
Abstract
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50686597A JP2001519973A (en) | 1995-07-19 | 1996-07-18 | Prioritized access to shared buffers |
PCT/US1996/011920 WO1997003549A2 (en) | 1995-07-19 | 1996-07-18 | Prioritized access to shared buffers |
AU65010/96A AU6501096A (en) | 1995-07-19 | 1996-07-18 | Prioritized access to shared buffers |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US149895P | 1995-07-19 | 1995-07-19 | |
US60/001,498 | 1995-07-19 | ||
PCT/US1996/011920 WO1997003549A2 (en) | 1995-07-19 | 1996-07-18 | Prioritized access to shared buffers |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1997003549A2 WO1997003549A2 (en) | 1997-02-06 |
WO1997003549A3 true WO1997003549A3 (en) | 1997-04-03 |
Family
ID=38659668
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1996/011920 WO1997003549A2 (en) | 1995-07-19 | 1996-07-18 | Prioritized access to shared buffers |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP2001519973A (en) |
AU (1) | AU6501096A (en) |
WO (1) | WO1997003549A2 (en) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
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FI104603B (en) | 1997-11-04 | 2000-02-29 | Nokia Networks Oy | Control of buffer |
US6189035B1 (en) * | 1998-05-08 | 2001-02-13 | Motorola | Method for protecting a network from data packet overload |
US6377546B1 (en) | 1998-05-12 | 2002-04-23 | International Business Machines Corporation | Rate guarantees through buffer management |
DE19825541A1 (en) * | 1998-06-08 | 1999-12-09 | Bosch Gmbh Robert | Device and method for mapping object addresses |
WO2000011841A1 (en) * | 1998-08-18 | 2000-03-02 | Madge Networks Limited | Method and system for prioritised congestion control in a switching hub |
WO2001022689A1 (en) * | 1999-09-21 | 2001-03-29 | Touch Technologies, Inc. | Method and apparatus for receive or transmit data ordering |
US7007071B1 (en) | 2000-07-24 | 2006-02-28 | Mosaid Technologies, Inc. | Method and apparatus for reducing pool starvation in a shared memory switch |
JP2002374251A (en) * | 2001-06-14 | 2002-12-26 | Nec Corp | Network monitoring system, data amount count method used for the same, and program thereof |
US6513122B1 (en) | 2001-06-29 | 2003-01-28 | Networks Associates Technology, Inc. | Secure gateway for analyzing textual content to identify a harmful impact on computer systems with known vulnerabilities |
US7295563B2 (en) | 2001-10-01 | 2007-11-13 | Advanced Micro Devices, Inc. | Method and apparatus for routing packets that have ordering requirements |
US7221678B1 (en) | 2001-10-01 | 2007-05-22 | Advanced Micro Devices, Inc. | Method and apparatus for routing packets |
US7274692B1 (en) * | 2001-10-01 | 2007-09-25 | Advanced Micro Devices, Inc. | Method and apparatus for routing packets that have multiple destinations |
US20030223442A1 (en) * | 2002-05-29 | 2003-12-04 | Huang Anguo T. | Buffer memory reservation |
US7593409B2 (en) * | 2005-12-29 | 2009-09-22 | Honeywell International Inc. | Apparatus and methods for monitoring network traffic |
US9367487B1 (en) | 2009-06-10 | 2016-06-14 | Nvidia Corporation | Mitigating main crossbar load using dedicated connections for certain traffic types |
US8325194B1 (en) | 2009-06-10 | 2012-12-04 | Nvidia Corporation | Mitigating main crossbar load using dedicated connections for certain traffic types |
US8065465B1 (en) * | 2009-06-10 | 2011-11-22 | Nvidia Corporation | Mitigating main crossbar load using dedicated connections for certain traffic types |
EP2696536A1 (en) * | 2012-08-07 | 2014-02-12 | Broadcom Corporation | Buffer statistics tracking |
US9450916B2 (en) | 2014-08-22 | 2016-09-20 | Honeywell International Inc. | Hardware assist for redundant ethernet network |
US11275632B2 (en) | 2018-09-14 | 2022-03-15 | Advanced Micro Devices, Inc. | Broadcast command and response |
CN113010173A (en) | 2019-12-19 | 2021-06-22 | 超威半导体(上海)有限公司 | Method for matrix data broadcasting in parallel processing |
CN113094099A (en) | 2019-12-23 | 2021-07-09 | 超威半导体(上海)有限公司 | Matrix data broadcast architecture |
US11403221B2 (en) | 2020-09-24 | 2022-08-02 | Advanced Micro Devices, Inc. | Memory access response merging in a memory hierarchy |
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US4727537A (en) * | 1985-12-24 | 1988-02-23 | American Telephone And Telegraph Company | Flow control arrangement for the transmission of data packets to a communication network |
US5083269A (en) * | 1989-01-10 | 1992-01-21 | Kabushiki Kaisha Toshiba | Buffer device suitable for asynchronous transfer mode communication |
US5515359A (en) * | 1994-08-26 | 1996-05-07 | Mitsubishi Electric Research Laboratories, Inc. | Credit enhanced proportional rate control system |
US5528591A (en) * | 1995-01-31 | 1996-06-18 | Mitsubishi Electric Research Laboratories, Inc. | End-to-end credit-based flow control system in a digital communication network |
US5533020A (en) * | 1994-10-31 | 1996-07-02 | International Business Machines Corporation | ATM cell scheduler |
US5541912A (en) * | 1994-10-04 | 1996-07-30 | At&T Corp. | Dynamic queue length thresholds in a shared memory ATM switch |
-
1996
- 1996-07-18 AU AU65010/96A patent/AU6501096A/en not_active Abandoned
- 1996-07-18 JP JP50686597A patent/JP2001519973A/en active Pending
- 1996-07-18 WO PCT/US1996/011920 patent/WO1997003549A2/en active Application Filing
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
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US4727537A (en) * | 1985-12-24 | 1988-02-23 | American Telephone And Telegraph Company | Flow control arrangement for the transmission of data packets to a communication network |
US5083269A (en) * | 1989-01-10 | 1992-01-21 | Kabushiki Kaisha Toshiba | Buffer device suitable for asynchronous transfer mode communication |
US5515359A (en) * | 1994-08-26 | 1996-05-07 | Mitsubishi Electric Research Laboratories, Inc. | Credit enhanced proportional rate control system |
US5541912A (en) * | 1994-10-04 | 1996-07-30 | At&T Corp. | Dynamic queue length thresholds in a shared memory ATM switch |
US5533020A (en) * | 1994-10-31 | 1996-07-02 | International Business Machines Corporation | ATM cell scheduler |
US5528591A (en) * | 1995-01-31 | 1996-06-18 | Mitsubishi Electric Research Laboratories, Inc. | End-to-end credit-based flow control system in a digital communication network |
Also Published As
Publication number | Publication date |
---|---|
JP2001519973A (en) | 2001-10-23 |
AU6501096A (en) | 1997-02-18 |
WO1997003549A2 (en) | 1997-02-06 |
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