WO1997005655A1 - Three-dimensional non-volatile memory - Google Patents
Three-dimensional non-volatile memory Download PDFInfo
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- WO1997005655A1 WO1997005655A1 PCT/US1996/012527 US9612527W WO9705655A1 WO 1997005655 A1 WO1997005655 A1 WO 1997005655A1 US 9612527 W US9612527 W US 9612527W WO 9705655 A1 WO9705655 A1 WO 9705655A1
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- Prior art keywords
- strips
- depression
- layer
- sidewall
- oxide
- Prior art date
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- 230000015654 memory Effects 0.000 title claims description 44
- 239000000463 material Substances 0.000 claims abstract description 38
- 239000004065 semiconductor Substances 0.000 claims abstract description 35
- 238000001020 plasma etching Methods 0.000 claims abstract description 5
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- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 33
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- 238000005530 etching Methods 0.000 description 10
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- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 2
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Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
- H01L29/7881—Programmable transistors with only two possible levels of programmation
- H01L29/7884—Programmable transistors with only two possible levels of programmation charging by hot carrier injection
- H01L29/7885—Hot carrier injection from the channel
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
Definitions
- This invention relates to non-volatile memory structures. More particularly, this invention relates the flash memory structures.
- Figure 1 is a circuit diagram of a portion of a conventional non-volatile memory 1 called a "flash" memory.
- Figure 2 is a simplified top down diagram of the flash memory. Flash memory 1 has several bit transistors. The bit transistor 2 at the intersection of vertically extending metal bit line BL1 and horizontally extending word line WL2 is depicted in cross-section in Figures 3 and 4 (Prior Art) . As shown in Figures 3 and 4, bit transistor 2 has a floating gate FG which is insulated from the overlying word line L2 and metal bit line BL1. The rectangular cross-hatched features in Figure 2 represent floating gates.
- the second word of bits of flash memory 1 is read by driving word line WL2 with a positive voltage (for example, 5.0 volts) and by grounding the other word lines.
- bit transistors in the second word are then conductive whereas the other bit transistors in the second word are not conductive.
- Each one of the bit lines BL1 through BLX+1 is driven with a positive voltage (such as 1.0 volts) and the current flowing through the bit line is sensed. If the bit line current is greater than 10 microamperes (for example, 100 microamperes) , then the corresponding bit transistor in the selected word is determined to be conductive (i.e. "discharged"). If, on the other hand, the bit line current is less than 10 microamperes, then the corresponding bit transistor in the selected word is determined to be non-conductive (i.e. "charged").
- the information content of each bit of the second word is read in this manner.
- the flash memory 1 is "erased” of information by discharging all the floating gates at once (hence the term “flash”) . Flash memory 1 is then "programmed” with information by charging selected ones of the floating gates and thereby leaving the other floating gates discharged. Discharging occurs by a phenomenon called “Fowler-Nordheim tunneling” whereas charging occurs by a phenomenon called “hot electron injection”. See the following documents for further background information on Fowler-Nordheim tunneling, hot electron injection, and flash memory structures: U.S. Patent No. 5,077,691 entitled "Flash EEPROM Array With Negative Gate Voltage Erase Operation; U.S. Patent No.
- a strip of a semiconductor material for example, P type silicon
- a semiconductor material for example, P type silicon
- Floating gates are then formed over and along the steep sidewalls and corresponding word lines are formed over the floating gates.
- a conductive region for example, N type silicon
- a number of conductive regions for example, N type silicon
- Bit transistors are thereby formed having channel regions which extend in a vertical dimension under floating gates along the vertical surface of the depression sidewall from the conductive region at the bottom of the depression to respective ones of the conductive regions outside the depression.
- the length of the floating gates is determined by the depth and sidewall profile of the depression, and because the depth and profile of the depression is determined primarily by oxidation and processing and not by lithography, very small geometry bit transistors can be made. Moreover, the vertical orientation of the floating gates on the sidewalls of the depression conserves silicon area and therefore facilitates still greater memory densities.
- the semiconductor sidewall surface does not have significant ion impact damage.
- a high quality thin tunnel oxide can be grown on the sidewall surface so that the floating gates are well insulated from the underlying sidewall surface.
- Figures 5-38 illustrate methods of fabricating a
- flash memory structure in accordance with the present invention.
- Figure 39 is a cross-sectional diagram of another memory structure in accordance with the present invention.
- a thin oxide 100 is grown over the entire upper surface of a P- type semiconductor material 101 and a thin nitride layer 102 (referred to in the drawings as "nitride #1") is deposited on the thin oxide.
- the thin oxide has a thickness is the range of approximately 50-500 angstroms and the thin nitride layer has a thickness in the range of approximately 50- 1000 angstroms.
- the P- type semiconductor material may, for example, be either substrate silicon or epitaxial silicon.
- the P- type semiconductor material is substrate silicon having a doping concentration in the range of approximately 1E13 atoms/cm 3 to 1E16 atoms/cm 3 .
- a first source/drain mask 103 (referred to in the drawings as "S/D mask #1") of photoresist is then formed having elongated parallel openings as shown in Figure 5.
- An isotropic nitride etch is then performed to obtain 50° to 60° thin nitride side-edge profiles.
- Figure 6 is a cross-sectional diagram taken along line X ⁇ X ⁇ ' on Figure 5 showing the resulting openings in the thin nitride layer.
- An oxide dip is then performed to remove thin oxide from the exposed openings.
- the source/drain mask #1 is then removed.
- a layer of oxide 104 is then formed over the remaining thin nitride and the exposed surface of the semiconductor material.
- Any suitable oxidation step may be used including a TEOS deposition step, an LTO (low temperature oxide) deposition step or an HTO (high temperature oxide) deposition step.
- the layer of oxide has a thickness in the approximate range of 50-500 angstroms and preferably has a thickness of approximately 250 angstroms.
- nitride #2 A thick layer of nitride 105 (referred to in the drawings as "nitride #2") is then deposited over the entire structure.
- This thick layer of nitride has a thickness in the approximate range of 1000-3000 angstroms and has a preferred thickness of approximately 2000 angstroms.
- a second source/drain mask 106 (referred to in the drawings as "S/D mask #2") of photoresist is formed as is ⁇ hown in Figure 7.
- An isotropic nitride etch is then performed to remove those portions of the thick nitride layer 105 exposed by the openings of the second source/drain mask 106.
- Figures 8-10 are cross- sectional diagrams taken along lines y ⁇ -y ⁇ ', ⁇ - ⁇ ' and Yi'Yi' i n Figure 7, respectively.
- a third source/drain mask 107 (referred to in the drawings as "S/D mask #3") of photoresist is formed as is shown in Figure 11. All oxide and thin nitride which is not protected by either the second or third source/drain masks is then removed from the underlying semiconductor material. The result is two horizontally extending rectangular strips of exposed P- type silicon.
- Figure 12 is a cross-sectional diagram showing the resulting structure along line x 2 -x 2 ' of Figure 11. If anisotropic nitride etching is used, a slanted thin nitride side-edge profile is obtained. A silicon step may also be obtained as illustrated by arrows S in Figure 12 due to the finite nitride-to-silicon selectivity (20:1 to 50:1) of the nitride etch. Etching into the semiconductor material 101 occurs in areas which were not covered by nitride at the beginning of the nitride etching step. The silicon step may be between 5 and 100 angstroms and most likely is about 25 angstroms.
- a silicon etch can optionally also be performed here in the process to increase effective floating gate length in the final bit transistors.
- a photoresist removal step is performed to remove the second and third source/drain masks 106 and 107
- a high temperature thick oxidation step is performed to grow a thick oxide 108 on the elongated rectangular exposed strips of the upper surface of semiconductor material 101 which is not covered by nitride.
- a high temperature dry thermal oxidation process is used as set forth in U.S. Patent No. 5,155,381. The subject matter of U.S. Patent No. 5,155,381 is incorporated herein by reference.
- Thick oxide 108 has a thickness in a range of approximately 1500-6000 angstroms and has an preferred thickness of approximately 3000 angstroms.
- Figure 13 is a simplified cross-sectional diagram showing thick oxide 108 along the line x 2 -x 2 ' of Figure 11.
- Figure 14 is a simplified cross-sectional diagram showing thick oxide 108 along the line ' of Figure 11. Note the different shapes of the bird's beaks of thick oxide layer 108 in Figures 13 and 14.
- the long and thin beams 110 of thin nitride in regions 109 shown in cross-section in Figure 13 allow thick oxide 108 to lift and bend beams 110 so that a relatively gradually sloping oxide 108 to semiconductor 101 boundary 111 is formed.
- Making the beams 110 of thin nitride as opposed to thick nitride makes the beams easier to bend.
- Making the beams 110 longer as opposed to shorter gives the oxide an additional mechanical advantage in bending the beams.
- the relatively thick nitride layer 105 is more difficult to bend and lift. Consequently, the oxide 108 to semiconductor material 101 boundary 112 in Figure 14 is relatively steep as compared with the gradually sloping boundary ill of Figure 13.-
- a core implant step is performed as illustrated in Figure 15.
- boron is implanted with a dose in the range of approximately 1E13 atoms/cm 2 to 5E14 atoms/cm 2 and an implant energy in the approximate range of 50-300 KeV.
- a boron dose of approximately 5E13 atoms/cm 2 is implanted with an implant energy of approximately 100 KeV.
- a large angle twist and tilt implant technique is preferred and is illustrated in Figure 15.
- An optional source/drain implant step may then be performed as illustrated in Figure 16.
- Arsenic may be implanted with a dose in the range of approximately 1E15 atoms/cm 2 to 1E16 atoms/cm 2 with an implant energy in the range of approximately 300-500 KeV. Arsenic is preferably implanted with a dose of approximately 3E15 atoms/cm 2 with an implant energy of 400 KeV. If doubly ionized arsenic is used, an implant energy of 200 KeV is preferred. Performing this source/drain implant at this point in the process alleviates the need to perform a source/drain implant later in the process when the tunnel oxide is present. Accordingly, the tunnel oxide to be formed later in the process is not subjected to damage to which it otherwise would be subjected were a source/drain implant performed later.
- a thick oxide etch back step is then performed as illustrated in Figure 17.
- reactive ion etching of the oxide is used to achieve anisotropic etching.
- a typical oxide-to-nitride selectivity of 3:1 is used meaning that oxide is etched three times faster than nitride.
- Approximately 1000 angstroms of the thick oxide 108 is removed leaving approximately 300 angstroms of the thick oxide covering semiconductor material 101 in the bottom of the etch depression.
- a VSS source implant step is performed as illustrated in Figure 18 to dope the semiconductor material 101 at the bottom of the thick oxide etch depression.
- arsenic is implanted with a dose in the range of approximately 1E15 atoms/cm 2 to 1E16 atoms/cm 2 and an implant energy in the range of approximately 30-150 KeV. In a preferred embodiment, arsenic is implanted with a dose of approximately 5E15 atoms/cm 2 and an implant energy of approximately 80 KeV. In other embodiments, boron is implanted with a dose in the range of approximately 1E15 atoms/cm 2 to 1E16 atoms/cm 2 and an implant energy in the range of approximately 20-70 KeV.
- boron is implanted with a dose of approximately 5E15 atoms/cm 2 and an implant energy of approximately 50 KeV.
- a nitride etch is then performed to remove all remaining nitride.
- a nitride-to-oxide selectivity of 3:1 is used to stop etching on the oxide which overlies thin nitride 102.
- a wet oxide etch is then performed to remove all thin oxide 100 and thick oxide 108 which is not disposed underneath thin nitride.
- the result is two depressions.
- Each of the depressions has two opposing, long, parallel and steep sidewalls and two opposing, short, parallel and gradually sloping sidewalls.
- the depressions have long and relatively flat bottom surfaces.
- Figures 19-21 are cross-sectional diagrams of the resulting structure taken along lines yj-y t ' , y 2 - y 2 ' and x 2 -x 2 ' of Figure 11, respectively.
- the P type dopants which were implanted in the core implant step illustrated in Figure 15 form P type regions 113.
- the N type dopants which were implanted in the VSS source implant step illustrated in Figure 18 form elongated N+ type regions 114 extending into the semiconductor material in the bottom of the depressions.
- the sidewalls of the depressions do not have significant ion impact damage (the ion implant doping steps do not significantly damage the sidewalls like reactive ion etching of the semiconductor material would) . Accordingly, a high quality thin tunnel oxide can be grown on the sidewalls. An oxidation step is therefore performed to form a thin layer 115 of tunnel oxide on the sidewalls of the depressions and all other surfaces of semiconductor material 101 not covered by thin nitride 102.
- the tunnel oxide 115 may, for example, be 50-200 angstroms thick.
- a polysilicon layer (referred to as "polyl” in the drawings) is then deposited over the entire structure and is etched.
- the result is a spacer-like strip of polysilicon disposed over and along each corresponding steep sidewall 112 of the depressions over the tunnel oxide 115.
- the etching removes the polysilicon from the gradually sloping sidewalls 111 of the depressions.
- Figure 22 is a simplified top-down diagram of the resulting structure having two horizontally extending depressions 116 and 117.
- FIGS. 23-25 are cross-sectional diagrams taken along lines x 3 -x 3 ' , y 2 -y 2 ' and y ⁇ -y t ' of Figure 22, respectively. Note that the P type dopants from regions 113 have expanded by diffusion.
- a photoresist polysilicon mask 121 is then formed as illustrated in Figure 26 and a polysilicon etching performed «so that individual floating gates 123-132, ⁇ 132A and 132B of polysilicon remain over the steep sidewalls of the depressions.
- a wet polysilicon etch is preferred.
- Figure 27 is a cross-sectional diagram taken along line y 2 -y 2 ' of Figure 26 showing the removal of polysilicon from the steep sidewall between floating gates.
- P type dopants are implanted in a core isolation implant step as illustrated in Figures 28 and 29 using the polysilicon mask 122.
- Boron may be implanted with a dose in the range of approximately 5E12 atoms/cm 2 to 5E14 atoms/cm 2 with an implant energy in the range of approximately 10-100 KeV.
- a dose of approximately 5E13 atoms/cm 2 of boron is implanted with an implant energy of approximately 30 KeV.
- the polysilicon mask 122 is removed.
- an interpolydielectric formation step is performed.
- all exposed silicon surfaces including the polysilicon floating gates are oxidized to form an overlying oxide layer.
- a first oxide layer is then deposited over the entire structure, a nitride layer is then deposited over the first oxide layer, and a second oxide is 1 deposited over the nitride layer to form an ONO insulator structure.
- a gate oxidation step is performed to form an additional oxide layer having a thickness in the range of approximately 50-200 angstroms. In a preferred embodiment, about 2-100 angstroms of this additional gate oxide is formed.
- These insulator layers are hereafter referred to together as insulator layer 133.
- a conductive layer of polysilicon is deposited over the entire structure.
- This polysilicon layer can have a thickness in the range of approximately 500 to 3000 angstroms and preferably has a thickness of approximately 1000 angstroms.
- polycide may be used rather than mere polysilicon.
- a second polysilicon mask 133 of photoresist is formed. As illustrated in Figure 30, pad portions 134 and 135 of polysilicon are masked to form pads. A polysilicon etch is then performed. The result is that each steep sidewall has a polysilicon strip disposed over and along it (the polysilicon strip is of course separated from the sidewall by insulator layer 133) . Polysilicon strips 136 and 137 are disposed over and along the steep sidewalls of upper depression 116 whereas polysilicon strips 138 and 139 are disposed over and along the steep sidewalls of lower depression 117.
- Figure 31 is a simplified cross-sectional diagram taken along line yi-yi' of Figure 30.
- Figure 32 is an expanded view of polysilicon floating gate 130 and overlying polysilicon strip 138 over a steep sidewall of depression 117.
- oxide spacers are formed to cover the top side-edges of the floating gate and the conductive strips.
- Figure 33 is a cross-sectional diagram illustrating one such oxide spacer 140 which covers upper side-edge 141 of floating gate 130 and upper side-edge 142 of conductive strip 138.
- the oxide spacers can be formed by depositing approximately 500 to 3000 angstroms of oxide using LTO or TEOS deposition and then etching the oxide into spacers.
- arsenic is implanted with a dose in the range of approximately 1E15 atoms/cm 2 to 1E16 atoms/cm 2 with an implant energy in the range of approximately 20-100 KeV. In a preferred embodiment, arsenic is implanted with a dose of 5E15 atoms/cm 2 with an implant energy of approximately 60 KeV.
- the oxide spacers protect the upper portions of the tunnel oxide 115, floating gates 126-132B, insulator layer 133, and/or conductive strips 136-139 around upper side-edges 140 and 142 from damage during this implanting step.
- Figure 34 is a cross-sectional diagram taken along line yi-yi' of Figure 30 after the source/drain implant step.
- Relatively deep N+ type regions 143 and 144 are formed into semiconductor material 101 in the bottom of depressions 116 and 117, respectively.
- Relatively shallow N+ type regions 145 and 146 which are masked from the source/drain implant are therefore formed along the edges of deep region 143 and relatively shallow N+ type regions 147 and 148 which are masked from the source/drain implant are therefore formed along the edges of deep region 144.
- a relatively deep N+ type region is formed between each adjacent pair of depressions.
- N+ type regions 149-151 are such N+ type regions.
- the implanted dopants are activated in a source/drain anneal step.
- the anneal may be carried out in nitrogen or argon for approximately 15 minutes at approximately 900°C.
- Figure 35 is an expanded and simplified cross- sectional diagram of a bit transistor 152 of the structure illustrated in Figure 34.
- Oxide spacer 153 is similar to oxide spacer 140 of Figure 33.
- the distance “L” in Figure 35 is the length of the channel region (i.e., "gate length") of the bit transistor 152 having floating gate 132A.
- Region 144 is generally more heavily doped than region 148.
- Figure 36 is a cross-sectional diagram taken along line x 3 -x 3 ' of Figure 30 after the source/drain implant step.
- Distance A is approximately 1000 angstroms or greater (in a range of approximately 700 to 1300 angstroms) to prevent the source/drain implant from counterdoping P type regions 154 formed during the step illustrated in Figure 29.
- Distance B is approximately 200 angstroms or less (in a range of approximately 100 to 300 angstroms) so that region 150 will be implanted during the source/drain implant step.
- an overlying insulator layer is formed over the entire structure, contact openings are formed down to the N+ type regions 149-151 between depressions and down to the pad portions 134 and 135 of polysilicon. Overlying metal interconnect lines are then formed over the insulator layer to make contact to the underlying structure where appropriate through the contact openings.
- Figure 37 is a simplified top-down diagram showing metal bit lines BL1 and BL2 extending in the vertical dimension over the horizontally extending depressions 116 and 177. Portions of the memory structure are omitted to simplify the illustration.
- Contact 155 couples N+ type region 150 of Figure 34 to bit line BL1. Similar contacts are provided for the other bit lines. A contact is provided on each bit line in the space between each consecutive pair of adjacent depressions.
- horizontally extending conductive strip 137 is word line WL2.
- Contact 156 provides access to word line WL2 in depression 116. Each word line has a similar contact.
- FIG. 38 is a simplified circuit diagram in accordance with the present invention.
- the upper word including bit transistors 157 and 158 is read by driving the word line WL2 of the selected word with a relatively positive voltage (for example, 5.0 volts) and driving all other words lines with ground potential.
- bit transistor 157 If, for example, the floating gate 127 of bit transistor 157 were sufficiently discharged of electrons, then an adequately large electric field would be present on the channel region of bit transistor 157 that a conductive path would be formed from region 143 (see Figure 34) in the bottom of depression 116, through N+ type region 146, through the conductive channel region in P type region 113 , and to N+ type region 150. If, on the other hand, the floating gate 127 of bit transistor 157 were sufficiently charged with electrons, then bit transistor 157 would not be conductive and the conductive path would not be formed. Accordingly, each bit line is driven with a positive voltage (for example, 1.0 volts) and the current flowing through the bit line is sensed.
- a positive voltage for example, 1.0 volts
- bit line current is greater than a predetermined amount (for example, greater than 10 microamperes) , then the corresponding bit transistor in the selected word is determined to be conductive (the floating gate is discharged) . If, on the other hand, the bit line current is smaller than the predetermined amount (for example, less than 10 microamperes) , then the corresponding bit transistor in the selected word is determined to be nonconductive (the floating gate is charged) .
- a predetermined amount for example, greater than 10 microamperes
- bit transistors 159 and 160 are nonconductive and do not contribute significantly to the bit line currents. In this way, one selected word of bits of information stored on the floating gates of the bit transistors is read out in the form of bit line currents on bit lines BL1 and BL2.
- all the words of bit transistors of a memory are discharged simultaneously (i.e., "erased") .
- flash memory
- the floating gates of selected bit transistors of a selected word are charged (i.e., "programmed") by hot electron injection. If, for example, the floating gate 127 of bit transistor 157 were to be charged but the floating gates of all the other .bit transistors 158, 130 and 131 were to remain discharged, then the voltage conditions of Table 2 below would be supplied to the memory structure.
- Energetic electrons are made to move from VSS1 line 143 toward bit line BL1 by the potential difference between the VSS1 line and the bit line BL1.
- the positive voltage on the word line WL2 above floating gate 127 attracts these energetic electrons (i.e., "hot” electrons) upward so that some of the energetic electrons are redirected up into the floating gate 127 and become trapped in the floating gate 127.
- the floating gate of bit transistor 157 is charged with electrons but the floating gates of bit transistors 158, 159 and 160 are not.
- ALTERNATIVE STRUCTURE Figure 39 is a simplified cross-sectional diagram of an alternative structure in accordance with another embodiment of the present invention.
- a P- well 200 is disposed inside a deep N- well 206 to isolate an N+ buried layer 201 from the substrate 207.
- Fowler- Nordheim tunneling is used both for charging floating gates and for discharging floating gates.
- the PN junction between P- well 200 and N+ buried layer 201 is reverse biased as is the PN junction between P- well 200 and deep N- well 206.
- N+ Buried Layer 201 grounded or floating
- the structure of Figure 39 is fabricated in accordance with the above-described fabrication method by: 1) forming the N+ buried layer 201 before the thin nitride layer 102 is deposited, 2) omitting the thick oxide etch back step and the VSS source implant step (see Figures 17 and 18) , and 3) performing the optional source/drain implant step (see Figure 16) after the nitride etch step and before the step of removing the remaining thick oxide (between Figures 18 and 19) .
- the N+ buried layer 201 is formed by implanting arsenic or phosphorous with an implant energy in a range of approximately 400-800 KeV and a preferred implant energy of approximately 600 KeV.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP50787197A JP3821848B2 (en) | 1995-08-01 | 1996-07-31 | 3D non-volatile memory |
EP96926200A EP0784867B1 (en) | 1995-08-01 | 1996-07-31 | Method of manufacturing a vertical non-volatile memory cell |
KR1019970702104A KR970706609A (en) | 1995-08-01 | 1996-07-31 | Three-dimensional non-volatile memory (THREE-DIMENSIONAL NON-VOLATILE MEMORY) |
DE69637352T DE69637352T2 (en) | 1995-08-01 | 1996-07-31 | Method for producing a vertical nonvolatile memory cell |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/510,118 US5945705A (en) | 1995-08-01 | 1995-08-01 | Three-dimensional non-volatile memory |
US08/510,118 | 1995-08-01 |
Publications (1)
Publication Number | Publication Date |
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WO1997005655A1 true WO1997005655A1 (en) | 1997-02-13 |
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PCT/US1996/012527 WO1997005655A1 (en) | 1995-08-01 | 1996-07-31 | Three-dimensional non-volatile memory |
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US (2) | US5945705A (en) |
EP (1) | EP0784867B1 (en) |
JP (2) | JP3821848B2 (en) |
KR (1) | KR970706609A (en) |
DE (1) | DE69637352T2 (en) |
WO (1) | WO1997005655A1 (en) |
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Also Published As
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DE69637352T2 (en) | 2008-11-13 |
JP2006049926A (en) | 2006-02-16 |
US6043122A (en) | 2000-03-28 |
KR970706609A (en) | 1997-11-03 |
EP0784867B1 (en) | 2007-12-05 |
US5945705A (en) | 1999-08-31 |
EP0784867A1 (en) | 1997-07-23 |
JP3821848B2 (en) | 2006-09-13 |
JP3968107B2 (en) | 2007-08-29 |
JPH10507319A (en) | 1998-07-14 |
DE69637352D1 (en) | 2008-01-17 |
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