WO1997007466A1 - Re-configurable application specific device - Google Patents

Re-configurable application specific device Download PDF

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Publication number
WO1997007466A1
WO1997007466A1 PCT/GB1996/002013 GB9602013W WO9707466A1 WO 1997007466 A1 WO1997007466 A1 WO 1997007466A1 GB 9602013 W GB9602013 W GB 9602013W WO 9707466 A1 WO9707466 A1 WO 9707466A1
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WIPO (PCT)
Prior art keywords
data
micro
controller
input
programmable
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Application number
PCT/GB1996/002013
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French (fr)
Inventor
Kenneth Austin
Original Assignee
Kenneth Austin
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Kenneth Austin filed Critical Kenneth Austin
Priority to AU67504/96A priority Critical patent/AU6750496A/en
Publication of WO1997007466A1 publication Critical patent/WO1997007466A1/en

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    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00—Digital computers in general; Data processing equipment in general
    • G06F15/76—Architectures of general purpose stored program computers
    • G06F15/78—Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7867—Architectures of general purpose stored program computers comprising a single central processing unit with reconfigurable architecture

Definitions

  • the present invention relates to a re ⁇ configurable integrated circuit, with particular emphasis on a re-configurable application specific device, but without limitation to same.
  • U.K. Patent Application No. 9503003 describes a configurable semi-conductor integrated circuit, eg. a digital signal processor, in which an area thereof is formed with a plurality of cells each having at least one function and interconnections with at least some other said cells. At least some of the plurality of cells have interconnections which are electrically selectable as to their conduction state, and at least some of the plurality of cells have interconnections which are pre-wired. Each cell has two or more possible configurations, each configuration being defined by the cell function and/or its interconnection with other cells according to cell configuration data. Means is provided for storing configuration data for at least two cell configurations (per cell) and means is provided to enable one of the possible cell configurations according to the cell configuration data selected. A control circuit is utilised to pass configuration data, program data and coefficients to an array memory and memory caches.
  • a control circuit is utilised to pass configuration data, program data and coefficients to an array memory and memory caches.
  • the previou ⁇ architecture had fixed programming circuitry and the present invention aims to provide improvements in flexibility and efficiency.
  • the present invention provides a re ⁇ configurable semi-conductor integrated circuit device of the type which, as made, comprises a plurality of cells which have two or more possible configurations, means for storing configuration data for at least two cell configurations (per cell), data memory for the array and input/output channels for the device, the device further comprising a programmable micro-controller and a direct memory access engine controlled by the programmable micro-controller to control the transfer of data to and/or from:- the array memory; the input/output channels and the means storing configuration data.
  • the direct memory engine (hereinafter referred to as a DMA engine) directly generates internal and external addresses transferring a preselected number of data words.
  • the micro ⁇ controller directs data transfer, while the DMA engine is responsible for transferring data at high speed. It receives its instructions from the micro-controller and transfers data in the background.
  • a further advantageous feature is the provision of interrupt logic that can be used to interrupt the main flow of data and cause a new set of transfers to occur. Interrupts may be generated either by an off- chip signal, and on-chip signal or an on-chip event caused by an interrupt timer. It is preferred that the micro-controller ha ⁇ a dedicated interrupt circuit for each of the logic blocks. For this purpose each logic block feeds a control node of the micro-processor which can be used to signify the end of a task or request for more data etc. More preferably still, the micro ⁇ controller has a timer for each logic block and the timer can be used to time a process that the block is performing thereby freeing the block from dedicating some of its cells to this task. A further alternative is for external signals to be routed into the micro ⁇ controller from the input to replace or be used in conjunction with internally generated interrupts.
  • the device further comprise ⁇ a plurality of programmable sequencers which can be programmed individually or in combination to generate a sequence of configuration data storage addresses.
  • a further feature of the invention comprise ⁇ a programmable input/output by which the band width allocated for user input/output of configuration data and program data can be altered according to the application of the device.
  • Figure 1 is a schematic block diagram showing the principal element ⁇ of an integrated circuit device according to the present invention
  • FIG. 2 illustrates the device of Figure 1 in further detail
  • FIG. 3 is a schematic diagram showing in further detail one cell of the logic block for the device of Figures 1 and 2,
  • Figure 4 i ⁇ a ⁇ chematic illu ⁇ trating the logic blocks and the associated circuitry with address line and active cache selection
  • Figure 5 is a schematic of the logic blocks showing the details of the circuitry utilised for selecting and updating the memory caches
  • Figure 6 i ⁇ a block diagram illustrating a ⁇ ingle bit ⁇ equencer for use in the device of Figures 1 and 2
  • Figure 7 is a schematic circuit diagram for a programmable modulo counter as used in the single bit sequencer
  • FIG 8 i ⁇ a flow chart illustrating part of a normal program flow
  • the present invention is described in the context of an integrated circuit intended for an application specific device, one embodiment of which i ⁇ a reconfigurable signal processor (DSP).
  • a device according to Figure 1 comprises a plurality of logic function units or cells 2, programmable inputs and outputs 4 for the logic function units, and a configuration cache 3 storing configuration data for the logic function units.
  • the configuration cache 3 may be on-chip in immediate proximity to the logic function units as part of an array of logic blocks, as illu ⁇ trated in Figure ⁇ 3, 4 and 5.
  • the processor also comprise ⁇ a data memory 5, a micro-sequencer 7, a micro-controller 9, a direct memory acces ⁇ engine 11 and programmable input/output 13 for the DMA engine and micro-controller.
  • each logic block 21 comprises a matrix array of cells, for example an array of 8 x 8 cell.
  • Figure 3 illustrates schematically in further detail one of the logic cells of one of the logic blocks 21. It comprises a cell function unit 22 incorporating the desired logic circuitry, an 8 bit decoder 23, four-8 bit configuration caches 25(a-d), comprising programmable memory (RAM) , two-8 bit ROM configuration memories 27a, b representing two alternative boot-up configurations for the cell function unit.
  • the cells will be di ⁇ po ⁇ ed in group ⁇ , eg. columns which show the same boot up configuration - representing primary functions, eg.
  • decode cells eg. the row of cells at the bottom in Figures 4 and 5.
  • decoder 23 controls the input and output multiplexers and the cell function unit, either in terms of logic function or interconnect function by way of connection line ⁇ 30, 32, 34 and 36, according to which of the configuration cache ⁇ 25a-d, 27a, b is selected.
  • an instruction bus 35 connects into the logical unit from the decode cells and also serve ⁇ to control the function of the logic function unit.
  • caches 25 and 27 have four and two address lines respectively. Addressing of the logic block and transferring of data is described further with reference to Figure 2, 4 and 5.
  • the micro-controller 9 instructs the DMA engine 11 having taken its program instruction ⁇ from the programmable input 13 via multiplexer 41.
  • the program data is read in along program data bus 43.
  • Figure 6 illu ⁇ trates one of eight single bit sequencer ⁇ for the device which make up the micro- sequencer 7 of Figure 1.
  • Each comprise ⁇ , in the illustrated embodiment a four-input multiplexer 601 receiving global clock inputs - CLK1, CLK2, CLK3 and CLK4.
  • modulo counters there are two modulo counters, one, 100, operating on frequency and the other, 101, operating on ⁇ equence length. These are set from the icro- controller.
  • a sequence can be stored in each of RAM block ⁇ A and B.
  • Mean ⁇ i ⁇ provided for selecting which of the sequences is to be output on a global cache line.
  • Figure 6 illustrates the output for global cache-line Gl.
  • Gl there are eight po ⁇ sible outputs G1-G8 for the whole device.
  • the global lines G1-G8 are illustrated in Figure 4. Signals from the 8 global lines can be fed to each logic block 21.
  • the global lines connect with 3, 8 input multiplexer 105, 107 and 109.
  • the micro-controller controls the multiplexers 105, 107, 109 according to the selection of either RAM A or RAM B which has associated read enable, write enable, and data transmission lines 210, 212 and 214 respectively.
  • Outputs from the three multiplexers 105, 107, 109 feed to decoder 115.
  • decoder 115 Furthermore, there are node connections in each logic block and global connections with each logic block, x bu ⁇ es, these can provide a signal source for selection by the multiplexer as an alternative to or in addition to signal ⁇ on lines G1-G8.
  • Decoder 15 has six output lines which connect with the respective RAM and ROM memory cache ⁇ by horizontal connection line ⁇ .
  • Figure 5 illu ⁇ trates for one logic block the circuitry utilised for selecting and/or updating the cache ⁇ of the array of cells.
  • Co-ordinate selection of any of the caches 25a-d, 27a, b of a cell is possible utilising the two decoders 502, 504 by way of the DMA engine 11 under the instruction ⁇ from the micro ⁇ controller.
  • Transferring of data to the selected caches is by data bus 506 with data being passed by the DMA engine under instruction from the micro-controller. Where the data is to be written to the number of the caches is to be same, this can be written simultaneously to these caches.
  • the micro-controller has as ⁇ ociated interrupt logic which can be u ⁇ ed to interrupt the main flow of data and cau ⁇ e a new set of transfers to occur. Interrupts may be generated by either an off-chip signal, for example through the programmable input 13, an on-chip signal or an on-chip event caused by an interrupt timer.
  • the micro-controller 9 ha ⁇ a dedicated interrupt circuitry for each of the 32 array blocks. Furthermore each block can generate in interrupt by taking a control node on the micro-controller high, ⁇ ignalling the end of a task or request for more data. Alternatively, the micro-controller can use one of its 32 timers (not illustrated), ie.
  • External ⁇ ignal ⁇ can be routed into the micro-controller which can replace or be u ⁇ ed in conjunction with other generated interrupt ⁇ .
  • a further feature of the invention i ⁇ the u ⁇ e of programmable input/output which allow ⁇ the de ⁇ igner to allocate pins, ie. band width, to apportion user input/output for configuration data and program data.
  • a program addres ⁇ generator 150 is provided - ⁇ ee Figure 2.
  • a multiplexer 41 sets the band width for the configuration data and the program data under control of the micro-controller 9, in conjunction with the DMA engine and the respective address bus ⁇ es 154, 156 and 158.
  • the band width/number of pins allocated to configuration and program data re ⁇ pectively can be allocated according to the requirement ⁇ for the task to be performed.
  • the program input determines whether one of the prewired ROM configuration 27a, 27b is to be selected. If it is then the required control information is sent to the array as indicated by box 100. If not, then the required configuration data is written to say the first memory cache 25a and the fir ⁇ t logic block. The timer will be set for that logic block a ⁇ will the interrupts for that logic block. The process i ⁇ repeated for all the logic block ⁇ with the configuration data to be written to the blocks being determined by the architecture specification data, whilst the timers and interrupts are set according to control flow information.
  • FIG. 9 illustrates a interrupt service routine in more detail from which it will be seen that interrupts may be array interrupts 61 or timer interrupts 63. There is one for each logic block.

Abstract

In a re-configurable semi-conductor integrated circuit device which, as made, comprises a plurality of cells (2) which have two or more possible configurations, means (3) for storing configuration data for at least two cell configurations (per cell), data memory (5) for the array of cells, and input/output channels for the device, improvements in flexibility and efficiency are made possible by the provision of a programmable micro-controller (9) and a direct memory access engine (11) controlled by the programmable micro-controller to control the transfer of data to and/or from: the array memory; the input/output channels and the means storing configuration data. Re-configuration may be initiated by interrupt signals generated by an off-chip signal, an on-chip signal or an on-chip event. A plurality of programmable sequencers are used to generate a sequence of configuration data storage addresses.

Description

TITLE: Re-configurable application specific device
DESCRIPTION
The present invention relates to a re¬ configurable integrated circuit, with particular emphasis on a re-configurable application specific device, but without limitation to same.
U.K. Patent Application No. 9503003 describes a configurable semi-conductor integrated circuit, eg. a digital signal processor, in which an area thereof is formed with a plurality of cells each having at least one function and interconnections with at least some other said cells. At least some of the plurality of cells have interconnections which are electrically selectable as to their conduction state, and at least some of the plurality of cells have interconnections which are pre-wired. Each cell has two or more possible configurations, each configuration being defined by the cell function and/or its interconnection with other cells according to cell configuration data. Means is provided for storing configuration data for at least two cell configurations (per cell) and means is provided to enable one of the possible cell configurations according to the cell configuration data selected. A control circuit is utilised to pass configuration data, program data and coefficients to an array memory and memory caches.
The previouε architecture had fixed programming circuitry and the present invention aims to provide improvements in flexibility and efficiency.
Accordingly, the present invention provides a re¬ configurable semi-conductor integrated circuit device of the type which, as made, comprises a plurality of cells which have two or more possible configurations, means for storing configuration data for at least two cell configurations (per cell), data memory for the array and input/output channels for the device, the device further comprising a programmable micro-controller and a direct memory access engine controlled by the programmable micro-controller to control the transfer of data to and/or from:- the array memory; the input/output channels and the means storing configuration data.
More particularly, the direct memory engine (hereinafter referred to as a DMA engine) directly generates internal and external addresses transferring a preselected number of data words. Thus, the micro¬ controller directs data transfer, while the DMA engine is responsible for transferring data at high speed. It receives its instructions from the micro-controller and transfers data in the background.
A further advantageous feature is the provision of interrupt logic that can be used to interrupt the main flow of data and cause a new set of transfers to occur. Interrupts may be generated either by an off- chip signal, and on-chip signal or an on-chip event caused by an interrupt timer. It is preferred that the micro-controller haε a dedicated interrupt circuit for each of the logic blocks. For this purpose each logic block feeds a control node of the micro-processor which can be used to signify the end of a task or request for more data etc. More preferably still, the micro¬ controller has a timer for each logic block and the timer can be used to time a process that the block is performing thereby freeing the block from dedicating some of its cells to this task. A further alternative is for external signals to be routed into the micro¬ controller from the input to replace or be used in conjunction with internally generated interrupts.
More particularly the device further compriseε a plurality of programmable sequencers which can be programmed individually or in combination to generate a sequence of configuration data storage addresses.
A further feature of the invention compriseε a programmable input/output by which the band width allocated for user input/output of configuration data and program data can be altered according to the application of the device. The present invention will now be described further, by way of example only, with reference to the accompanying drawings; in which:-
Figure 1 is a schematic block diagram showing the principal elementε of an integrated circuit device according to the present invention,
Figure 2 illustrates the device of Figure 1 in further detail,
Figure 3 is a schematic diagram showing in further detail one cell of the logic block for the device of Figures 1 and 2,
Figure 4 iε a εchematic illuεtrating the logic blocks and the associated circuitry with address line and active cache selection, Figure 5 is a schematic of the logic blocks showing the details of the circuitry utilised for selecting and updating the memory caches,
Figure 6 iε a block diagram illustrating a εingle bit εequencer for use in the device of Figures 1 and 2, Figure 7 is a schematic circuit diagram for a programmable modulo counter as used in the single bit sequencer,
Figure 8 iε a flow chart illustrating part of a normal program flow, and Figure 9 iε a flow chart showing the interrupt service routine. The present invention is described in the context of an integrated circuit intended for an application specific device, one embodiment of which iε a reconfigurable signal processor (DSP). A device according to Figure 1 comprises a plurality of logic function units or cells 2, programmable inputs and outputs 4 for the logic function units, and a configuration cache 3 storing configuration data for the logic function units. In practice, the configuration cache 3 may be on-chip in immediate proximity to the logic function units as part of an array of logic blocks, as illuεtrated in Figureε 3, 4 and 5. The processor also compriseε a data memory 5, a micro-sequencer 7, a micro-controller 9, a direct memory accesε engine 11 and programmable input/output 13 for the DMA engine and micro-controller.
According to a preferred embodiment the logic block array compriεeε 32 logic blockε 21 as shown diagrammatically in Figure 2. Each logic block 21 comprises a matrix array of cells, for example an array of 8 x 8 cell. Figure 3 illustrates schematically in further detail one of the logic cells of one of the logic blocks 21. It comprises a cell function unit 22 incorporating the desired logic circuitry, an 8 bit decoder 23, four-8 bit configuration caches 25(a-d), comprising programmable memory (RAM) , two-8 bit ROM configuration memories 27a, b representing two alternative boot-up configurations for the cell function unit. Usually the cells will be diεpoεed in groupε, eg. columns which show the same boot up configuration - representing primary functions, eg. shifter, compare, adder etc. Also there are decode cells, eg. the row of cells at the bottom in Figures 4 and 5. Alεo illuεtrated are two 4-1 input multiplexers 28, 29 receiving signal inputs from other cells at 38 and 40, and a 1-4 output multiplexer 31 giving outputs to other cells at 42. The decoder 23 controls the input and output multiplexers and the cell function unit, either in terms of logic function or interconnect function by way of connection lineε 30, 32, 34 and 36, according to which of the configuration cacheε 25a-d, 27a, b is selected. In addition an instruction bus 35 connects into the logical unit from the decode cells and also serveε to control the function of the logic function unit. In the illustrated embodiment caches 25 and 27 have four and two address lines respectively. Addressing of the logic block and transferring of data is described further with reference to Figure 2, 4 and 5.
The micro-controller 9 instructs the DMA engine 11 having taken its program instructionε from the programmable input 13 via multiplexer 41. The program data is read in along program data bus 43.
Figure 6 illuεtrates one of eight single bit sequencerε for the device which make up the micro- sequencer 7 of Figure 1. Each compriseε, in the illustrated embodiment a four-input multiplexer 601 receiving global clock inputs - CLK1, CLK2, CLK3 and CLK4. There are two modulo counters, one, 100, operating on frequency and the other, 101, operating on εequence length. These are set from the icro- controller. A sequence can be stored in each of RAM blockε A and B. Meanε iε provided for selecting which of the sequences is to be output on a global cache line. Figure 6 illustrates the output for global cache-line Gl. Thus, there are eight poεsible outputs G1-G8 for the whole device. The global lines G1-G8 are illustrated in Figure 4. Signals from the 8 global lines can be fed to each logic block 21. The global lines connect with 3, 8 input multiplexer 105, 107 and 109. The micro-controller controls the multiplexers 105, 107, 109 according to the selection of either RAM A or RAM B which has associated read enable, write enable, and data transmission lines 210, 212 and 214 respectively. Outputs from the three multiplexers 105, 107, 109 feed to decoder 115. Furthermore, there are node connections in each logic block and global connections with each logic block, x buεεes, these can provide a signal source for selection by the multiplexer as an alternative to or in addition to signalε on lines G1-G8. Decoder 15 has six output lines which connect with the respective RAM and ROM memory cacheε by horizontal connection lineε.
Figure 5 illuεtrates for one logic block the circuitry utilised for selecting and/or updating the cacheε of the array of cells. Co-ordinate selection of any of the caches 25a-d, 27a, b of a cell is possible utilising the two decoders 502, 504 by way of the DMA engine 11 under the instructionε from the micro¬ controller. Transferring of data to the selected caches (in the case of the RAM caches 25a-d) is by data bus 506 with data being passed by the DMA engine under instruction from the micro-controller. Where the data is to be written to the number of the caches is to be same, this can be written simultaneously to these caches.
The micro-controller has asεociated interrupt logic which can be uεed to interrupt the main flow of data and cauεe a new set of transfers to occur. Interrupts may be generated by either an off-chip signal, for example through the programmable input 13, an on-chip signal or an on-chip event caused by an interrupt timer. The micro-controller 9 haε a dedicated interrupt circuitry for each of the 32 array blocks. Furthermore each block can generate in interrupt by taking a control node on the micro-controller high, εignalling the end of a task or request for more data. Alternatively, the micro-controller can use one of its 32 timers (not illustrated), ie. one for each logic block, to time a procesε that the block iε performing thereby freeing the block from dedicating some of its cells to thiε task. External εignalε can be routed into the micro-controller which can replace or be uεed in conjunction with other generated interruptε.
A further feature of the invention iε the uεe of programmable input/output which allowε the deεigner to allocate pins, ie. band width, to apportion user input/output for configuration data and program data. Accordingly, a program addresε generator 150 is provided - εee Figure 2. A multiplexer 41 sets the band width for the configuration data and the program data under control of the micro-controller 9, in conjunction with the DMA engine and the respective address busεes 154, 156 and 158. Thus, the band width/number of pins allocated to configuration and program data reεpectively can be allocated according to the requirementε for the task to be performed.
The operation of the circuit will now be described with reference to the flow chart of Figure 8. On powering up the device to configure a specific application, the program input determines whether one of the prewired ROM configuration 27a, 27b is to be selected. If it is then the required control information is sent to the array as indicated by box 100. If not, then the required configuration data is written to say the first memory cache 25a and the firεt logic block. The timer will be set for that logic block aε will the interrupts for that logic block. The process iε repeated for all the logic blockε with the configuration data to be written to the blocks being determined by the architecture specification data, whilst the timers and interrupts are set according to control flow information. This all serveε to initialiεe the array with the required start-up configuration if it is not to be one of the prewired boot configurations. In the normal program flow the micro-controller is programmed to monitor a node in each logic block εo that when an event occurs which turns it high or low a corresponding instruction will be carried out. In the example given for a false signal, instructions are sent to a decode cell to set a desired function for one column of cells. That selection will remain, for example until the allocated time has been completed or until an interrupt εignal iε received from one or more of the variouε sources. Where the signal is true then an alternative configuration cache iε adopted. The program continues to run with that configuration cache until it is instructed to change caches as part of the program run or according to interrupts.
Figure 9 illustrates a interrupt service routine in more detail from which it will be seen that interrupts may be array interrupts 61 or timer interrupts 63. There is one for each logic block.

Claims

1. A re-configurable semi-conductor integrated circuit device of the type which, as made, compriseε a plurality of cellε (2) which have two or more poεsible configurations, means (3) for storing configuration data for at least two cell configurations (per cell), data memory (5) for the array and input/output channels for the device, characterised in that the device further comprises a programmable micro-controller (9) and a direct memory access engine (11) controlled by the programmable micro-controller to control the transfer of data to and/or from:- the array memory; the input/output channelε and the means storing configuration data.
2. A device aε claimed in claim 1 in which the direct memory engine directly generateε internal and external addresεes tranεferring a preselected number of data wordε.
3. A device as claimed in claim 1 or 2 in which the micro-controller directs data transfer, while the DMA engine is responsible for tranεferring data at high speed.
4. A device aε claimed in any one of claims 1, 2 or 3 in which interrupt logic is provided to interrupt the main flow of data and cause a new set of transfers to occur .
5. A device as claimed in claim 4 in which interrupts are generated either by an off-chip signal, an on-chip signal or an on-chip event cauεed by an interrupt timer.
6. A device aε claimed in claim 4 or 5 in which the micro-controller has a dedicated interrupt circuit for each of the logic blocks.
7. A device as claimed in claim 6 in which each logic block feedε a control node of the micro-processor which can be used to signify the end of a task or request for more data etc.
8. A device as claimed in any one of claims 4, 5, 6 or 7 in which the micro-controller haε a timer for each logic block and the timer can be uεed to time a proceεε that the block iε performing.
9. A device as claimed in any one of claims 4 to 8 in which external interrupt signalε are routed into the micro-controller from the input to replace or be uεed in conjunction with internally generated interruptε.
10. A device aε claimed in any one of the preceding claimε further comprising a plurality of programmable sequencers which can be programmed individually or in combination to generate a sequence of configuration data storage addresses.
11. A device as claimed in any one of the preceding claims further comprising a programmable input/output by which the band width allocated for user input/output of configuration data and program data can be altered according to the application of the device.
12. A device constructed and arranged substantially as hereinbefore described with reference to and as illustrated in the accompanying drawings.
PCT/GB1996/002013 1995-08-17 1996-08-19 Re-configurable application specific device WO1997007466A1 (en)

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