WO1997012371A1

WO1997012371A1 - Charge transfer device including charge domain analog sample-and-hold circuit

Info

Publication number: WO1997012371A1
Application number: PCT/US1996/015207
Authority: WO
Inventors: Scott C. Munroe
Original assignee: Analog Devices, Inc.
Priority date: 1995-09-29
Filing date: 1996-09-20
Publication date: 1997-04-03
Also published as: AU7116196A

Abstract

A charge transfer device which includes a reference charge generator that generates a reference charge signal in response to receiving a control signal, first and second charge signal channels arranged to receive portions of the reference charge signal, and a charge distributor which distributes the reference charge signal between the first and second charge signal channels in accordance with a ratio determined by a differential input signal. The reference charge generator includes a source diffusion and a pair of gates each having respective potential wells electrically coupled to one another. The pair of gates generate the reference charge signal by extracting a charge packet from the source diffusion in response to having the control signal applied thereto, the charge packet being divided between the wells. The potential wells each include high conductivity regions defined by selected diffusions. The charge distributor includes a pair of barrier gates which are driven with the differential input signal. In exemplary embodiments of the invention, the charge transfer device is configured as a charge domain sample-and-hold circuit, a discrete-time amplifier circuit, a comparator circuit for discrete-time inputs and a magnetic field sensor circuit.

Description

CHARGE TRANSFER DEVICE INCLUDING CHARGE DOMAIN ANALOG SAMPLE-AND-HOLD CIRCUIT

BACKGROUND OF THE INVENTION

The present invention relates to charge transfer devices, and including charge domain analog sample and hold circuits.

A conventional sample and hold circuit 10, as shown in Fig. 1, takes a signal 12 and routes it through a switch 14 to a hold capacitor 16 and a buffer/amplifying element 18, which generates an output 19. The switch 14 is the cause of almost all of the problems with conventional sample and hold circuits. In fact, the resistance associated with this type of switch is critical to the circuit operation, because it directly affects the RC time constants, and thus how fast the signal is placed onto a holding node 17 with the required accuracy.

The switch 14 is typically very non-ideal, such as a MOSFET transistor, a diode bridge type of switch, etc., and in every case, the switch is a problem. The clock that controls the switch inevitably has some impact on the signal being held. For example, assume that the switch is closed so as to capture the input signal on the hold node to the accuracy required. It will be appreciated that the primary operations are done during the clock edges, such as closing the switch on the rising edge and opening on the falling edge. Now when the switch is opened, there will inevitably be stray capacitance between the switch and the control node (not shown) of the switch and the hold node 17. A charge dump occurs onto the hold node, which unfortunately is usually nonlinearly dependent upon signal amplitude, thereby causing distortion.

There is also a noise issue in that any noise on the switch ends up affecting the noise on the hold node. Another thing that typically happens with MOSFET type switches is that when the transistor is turned on hard, a lot of charge is forced into the transistor channel. However, this channel charge has to get out of that channel when the MOSFET is turned off. Some of the charge will go back to the source, some of it will go to the hold node, but it causes something called "partition noise". Exactly how that channel charge splits is very dependent upon signal values, on clock waveforms, and so on, so it is an additional source of noise and offsets on the hold node.

Accordingly, these factors lead designers to use diode bridge type switches rather than MOSFET type switches in very high speed applications. However, the exact nature of the switch is not as critical as the fact that a switch is used in conventional sample-and-hold circuits, the available switches are very non-ideal, and the higher the required acquisition speed, the more non-ideal the switches become.

Even if the capacitive parasitics and the charge partitioning problem could be completely eliminated, the switch related resistance and capacitance are real problems to the high speed operation of such circuits. In FET applications, in order to get the switch resistance down, a very wide FET channel is necessary, yet the wider the channel, the worse the parasitic capacitances become.

However, even with the best silicon switches conventionally available at present, these structures can only achieve a total acquisition time to one percent of the final value of about 7 nanoseconds. This limits the use of this technology in sub-sampling applications, wherein the goal is to strip off a signal that has been superimposed on a much higher frequency carrier. To do so requires a sample and hold circuit which operates fast relative to a cycle of the carrier, not just relative to the much lower frequency modulation that is being detected.

In a conventional radio frequency receiving circuit 20, as shown in Fig. 2, there is included an antenna 22 feeding into a low noise amplifier 23 and a bandpass filter 24, followed by a set of mixers with local oscillators. Quite often, there will be a stage of filtering integrated with the mixers, in the illustrated example mixer 25 at a first intermediate frequency IF1 and mixer 26 at a second intermediate frequency IF2. This stage is followed by a further signal processing operation 28, which results in an output corresponding to a baseband signal no longer riding on a carrier. This type of signal processing involves a large amount of circuitry which utilizes a large amount of power.

It would be desirable to avoid the need for most of the signal processing components and sample the carrier, for example, immediately following the low noise amplifier and bandpass filter with sample or track and hold elements. By sampling correctly on the carrier, the signal is dropped immediately to baseband. For instance, if a high frequency carrier is sampled at the same point at every other cycle, the result is a DC output. The carrier may be a gigahertz signal and the modulation may be in megahertz range, so it is possible to require a sampling only every hundredth cycle, for example.

By immediately dropping to the baseband, there is a decrease in the need for much of the conventional circuitry and associated power consumption, but the requirements for the sampling acquisition time are phenomenally short. If a one gigahertz carrier is being processed, the circuit needs to be able to sample a small fraction of the 1 nanosecond cycle length. In other words, it will be necessary to capture the carrier in a small fraction of one nanosecond, or roughly 100 picoseconds or less for a one gigahertz carrier. This represents a challenge to conventional sample and hold circuits which at present typically can subsample at low IFs of up to 20 to 30 megahertz.

It is an object of the present invention to provide a charge transfer device structure which can be utilized as a sample-and-hold circuit, a discrete time amplifier circuit, a comparator circuit with discrete time inputs and a magnetic field sensor circuit.

It is another object of the present invention to provide a sample-and-hold technology that is capable of far higher bandwidths and shorter acquisition times at far lower power dissipation and smaller circuit area than conventional techniques. - 4 -

It is a further object of the present invention to provide a sample-and -hold circuit which reduces the undesirable effects of switches by eliminating switches in the signal path.

SUMMARY OF THE INVENTION

BRIEF DESCRIPTION OF THE DRAWINGS

Fig. 1 illustrates a conventional sample and hold circuit;

Fig. 2 illustrates a conventional radio frequency receiving circuit;

Fig. 3 illustrates a charge domain analog sample-and- hold circuit in accordance with an exemplary embodiment of the present invention;

Fig. 4 illustrates a charge transfer device configured as a charge domain analog sample-and-hold circuit in accordance with an alternative exemplary embodiment of the present invention;

Figs. 5A-B and 6A-B illustrate the differential channels of the charge transfer device of Fig. 4 and associated potential diagrams, respectively; and

Figs. 7A-D illustrates an alternative exemplary embodiment of the differential barrier gates in accordance with the present invention.

DETAILED DESCRIPTION OF THE ILLUSTRATED EMBODIMENTS

With reference now to Fig. 3, a charge domain analog sample and hold circuit 30 in accordance with an exemplary embodiment of the present invention is shown. The circuit 30 includes a differential pair of MOSFET transistors 32, 34 in a common source arrangement. The gates of each of the transistors is driven by a differential voltage V™⁺, VIM-. The drain of transistor 32 is, for example, coupled to a voltage source V_DD while the drain of transistor 34 is coupled to a CCD shift register for further processing the captured charge signal or other configurations utilizing MESFETS or HBTs.

Alternatively, a fully-differential circuit can be realized by having both drains coupled to CCD shift registers. It will also be appreciated by those skilled in the art that the circuit 30 can alternatively be configured with bipolar transistors having a common emitter with each base driven by the differential signal.

The circuit 30 includes a charge source 35 which drives the common source (common emitter) node 37 of the differential pair. In typical differential pair configurations in analog applications, there is a continuous time signal applied to the common source node in the form of a constant current I. With respect to circuit 30, the current I is going to divide through the transistors under control of the differential signal. Now, instead of applying a continuous time current to node 37, a train of extremely sharp spikes of current are applied. Accordingly, when a current spike occurs, the current is going to divide under control of whatever differential signal was present on the gates at the time that the current spike existed. Therefore, if the current exists for only 100 picoseconds, for example, then the circuit has basically captured a snapshot of the differential signal during that time, without any switching in the signal path. However, conventional circuitry has difficulty generating current pulses of such short duration, and then processing the resulting charge packets. In contrast, within the charge domain this signal can be processed, because charge is simply the integral of current. In this case, the current spike can be equated to a certain Q₀. Thus, in accordance with the differential signal applied to the gates, KQ₀ is directed to transistor 32, while (1-K)Q₀ is directed to transistor 34.

In the exemplary embodiment illustrated, the charge source 35 includes a capacitor 38 coupled between the common source node 37 and an input for applying a sample and hold control pulse, and a transistor 36 having a gate coupled to the control pulse input, a source coupled to a reference voltage V_rβf, and a drain coupled to the common source node. In an exemplary 5V system, V_DD=5V, input common mode »2.5V, V_rβf=2.5V, and the S/H control signal goes from OV to 5V. In operation, with the S/H pulse high (5V), the transistors 32 and 34 are off and transistor 36 is on. Accordingly, the common source node 37 is pinned to V_rβ£, and the capacitor has V_DD-V_rβf applied across it. Once the S/H pulse goes low (OV), the displacement current through the capacitor tries to pull the common source node low. Also, the transistor 36 tries to clamp the node initially, but shuts off when the S/H pulse drops below ^β2.5V. The common source node thereafter continues to be pulled down until at least one of the differential pair of transistors turns on. At this point, all remaining charge on the capacitor is routed to transistor 32 and/or transistor 34, under control of the differential input signal.

For the shortest sampling time, the gain of the differential pair should be high enough to pass the charge completely in a time less than the desired acquisition time. The resultant charge packets can then be processed through CCD shift registers as is well known. However, this embodiment may suffer from poor acquisition time because the settling time constant increases exponentially as the FET conductances peak and then decrease. This "diode-capacitor" problem is unavoidable with this architecture.

In accordance with the present invention, it has been found that it is actually easier to carry out the previously described operation using CCDs. Accordingly, with reference to Fig. 4, a top view of a diagrammatic representation of a charge transfer device 400 configured as a CCD analog sample-and-hold circuit in accordance with an exemplary embodiment of the present invention is shown. The circuit 400 is configured from a series of contiguous gates which define first 402 and second 404 charge signal channels. The circuit includes an input source n⁺ diffusion 406 and an input terminal 407 for receiving an input signal. The source diffusion is followed by a series of gates, including a first barrier gate 410 and associated storage gates 412a, 412b which are driven by potential _{1 E} . The aforementioned gates are provided on an insulating layer, which in turn lies atop a semiconductor region including lightly doped n^" layer and a lightly doped p^" substrate.

The gates 412a and 412b each include respective integrated n⁺ diffusions 430a, 430b which are conductively tied to one another by a conductor 431 in order to reduce lateral time constants and keep the potentials in the two wells equivalent, in essence shorting the storage wells together. The operation of the n⁺ diffusions are described in more detail in a copending patent application filed by the Applicant on September 29, 1995 as U.S. Pat. Appl. Ser. NO. 08/536,688, entitled "SEMICONDUCTOR CHARGE POTENTIAL WELLS WITH INTEGRATED DIFFUSIONS", incorporated herein by reference.

The circuit further includes differential barrier gates 414a, 414b which are driven respectively by V_™ ⁺ and VIN-, storage gates 416a, 416b driven by φ^., and barrier and storage gate pairs 418a, 420a and 418b, 420b which are driven by φ_τ . The circuit also includes output barrier gates 422a, 422b driven by potential φ_x, a drain diffusion 424 for 5 receiving the output of channel 402 and a CCD shift register 426 for receiving the output of channel 404. While the illustrated electrode gates 412a-b, 416a-b, 418a-b, 420a-b and 422a-b are respectively tied together, it will be appreciated that the underlying channels are isolated from

10 one another.

In brief, the input diffusion 406, barrier gate 410 and storage gates 412a, 412b operate as a "charge scooper" by providing the charge packet source. With reference to Figs. 5A-B and 6A-B, a full well of charge is extracted from the

15 source diffusion when φ_I/E is high in voltage (low in electron potential) and split into the storage wells of gates 412a and 412b, respectively associated with the channels 402 and 404. When φ_I/ε goes low (i.e. to a high potential), the charge is dumped over the signal-modulated barrier gates

20 414a, 414b. The shorted storage wells of gates 414a, 414b act as a virtual source, and the division of the source charge into the channels 402 and 404 is determined in part by the potential difference between the two signal- controlled barrier gates 414a, 414b. Injection of the

25 charge across the signal-controlled barriers must be very fast or else the lower barrier will acquire most or all of the charge, thereby causing the structure to act as a comparator.

While the charge transfer device of the present

30 invention normally operates with an extremely short duration current pulse to create a comparator function. By slowing down the rate at which charge flows over the signal controlled barriers, the lower barrier accumulates a larger fraction of the total charge. In the limit of an extremely

35 slow transfer of charge, all of the charge would go over the lower barrier no matter how small the difference is between the lower and higher barriers. Although this limit cannot be achieved in practice, the concept shows that the gain of the comparator increases as the charge transfer rate decreases.

Due to the fact that the signal inputs must remain constant during this compare period, this type of comparator is best suited for comparing discrete-time signals that are fixed during the time of interest. A typical application would be the comparators used in many types of analog-to- digital converters, particularly the successive approximation class. When operating correctly, the charge transfer device of the present invention has gain (transconductance) during the injection of the charge across the signal barriers, just as the typical differential transistor pair exhibits gain (transconductance) when their common sources are loaded with a current source. The gain is yet another feature of the invention because the sampling and amplification functions are merged in one compact, low-power structure. Due to the fact that the charge transfer device of the present invention dissipates no DC power, the total power dissipation can be very low even for modest sample rates. This is very useful in situations where the input signal needs to be examined only at low duty cycles. An example of this scenario is battery powered equipment with an input from a low frequency transducer, such as a temperature sensor.

It will be appreciated by those of skill in the art that the source diffusion and gates 412a-b and 414a-b operate similarly to the charge source 35 of the 30 circuit, and that the differential barrier gates 414a-b operate comparatively to the transistors 32 and 34 with the storage gates 416a-b serving as virtual drains. The use of n⁺ diffusions which are shorted together similarly serves as a common source node with respect to common node 37 of the circuit 30. In operation, in light of the fact that the n^* diffusions of gates 412a and 412b are tied together, when the voltage φ_τ/_ goes low (i.e. to a high charge potential), the charge that is in the potential well of gates 412a and 412b are forced forward to the two barrier gates 414a and 414b, which are under control of the differential input signal. Accordingly, more charge will go over the lower signal barrier, hence the more positive signal as far as voltage/currents are concerned. If the differential input signal is non-zero, the charge actually experiences a lateral shift during this operation. A charge of Q₀ at gate 410 is split into packets of approximately Q₀/2 at gates 412a and 412b, but as soon as φ_τ/_ goes low and tries to push the charge packets forward, the lower of the two differential barriers (more positive electrode signal) is going to have more charge going over it. Because of this, the diffusion potential gets pulled down, which in turn draws charge across the conductor 431. Accordingly, following the differential gates 414a and 414b, the channel 402 has a charge packet K(Q₀/2), and the channel 404 has a charge packet (2-K)(Q₀/2), where K varies from 0 to 2. The current steering which is occurring at this point is analogous to that occurring in the transistor pair 32 and 34 of circuit 30. After the charge packets are captured in the subsequent storage wells of gates 420a and 420b, the output can be configured as single-ended with the charge packet of channel 402 feeding to a drain, and the charge packet of channel 404 feeding to a continuing CCD channel including shift registers. In the alternative, the outputs from the channels 402 and 404 can be fed to continuing CCD channels as differential signals.

The charge transfer device 400 of the present invention does not suffer from the long settling times and resulting poor acquisition times inherent in the circuit of Fig. 3. In fact, the CCD sample-and-hold circuit configuration has very fast acquisition times because the clocking action creates very strong electric fringing fields in the channel that quickly push all charge over the barriers controlled by the input signals. This is in contrast to the circuit of Fig. 3, wherein the electric fields necessary to move the charge through the FET channels decrease as the remaining charge decreases. This behavior leads to the exponentially increasing settling times noted earlier.

The aforementioned configuration is extremely fast and obviates the need for switches in series with the signals as is conventionally required. In addition, there is reduced power dissipation associated with the structure, primarily because the necessary clock circuitry would require power only on the order of a milliwatt, as compared with the conventional circuits which require on the order of a watt for processing speeds which are far slower than the exemplary circuit 400 of the present invention. Also, the circuit can be constructed on a semiconductor wafer using only a couple hundred square microns of silicon as opposed to thousands of square microns for conventional techniques.

It will be appreciated by those of skill in the art that at the front end of the circuit 400, the initial charge packet Q₀ can be generated, for example, by conventional fill and spill techniques in order to achieve a low noise charge packet. In addition, an exact splitting of the charge packet Q₀ is not paramount because the charge packets split into channels 402 and 404 are going to have time to equilibrate due to the n⁺ diffusions which are tied together. A unique advantage of the above described sub-sampling technique is that, instead of using multiple oscillators and mixers operating at hundreds of megahertz and sometimes gigahertz, or having an operating frequency near the carrier frequency, the present invention accommodates the use of clock frequencies that are only a few times the data rate. In fact, the differential structure of the present invention lends itself to forwarding the sampled charge to a CCD analog-to-digital converter for further processing.

With reference now to Figs. 7A-D, an alternative embodiment of the present invention is shown. Fig. 7A shows an alternative CCD circuit 740 in accordance with the present invention which includes storage gates 741 and 742 having isolated potential wells with electrode gates tied to a potential Q_{I E}. The storage gates each include n⁺ diffusions 743 and 744 which are tied together via a conductor 745. Differential barrier gates 746 and 747 are constructed as earlier described with the exception that a continuous polysilicon (or other conductive material) region which acts as a shorting link 748 is used to connect the gates together. In Fig. 7B, a potential well diagram for the differential gates 414a and 414b of the previously described circuit 40 are shown with the shorting link open. The wells 700, 710 include respective barriers 720, 730 that are set by the applied differential signal V_™*, V_™-. The field oxides between the gate provide the large potential barrier between the wells. In Fig. 7C, the potential wells 750 and 752 of the storage gates 741 and 742 are shown with Q₀/2 charge packets for the condition when Q_I/E is high and the shorting link closed. Fig. 7D shows the charge in the potential wells prior to injection over the signal barrier. When the Q_I/E clock goes low, the charge will be drawn to the side with the lower barrier.

Accordingly, the connection of the differential gates provides a controlled impedance between the signal channels. With the continuous polysilicon region 748, the potentials Vm⁺, VIN⁺ serve to pin the opposite ends of the gate, and because of the resistance of the gate material, a continuous ramped barrier 760 results which in effect provides a lower impedance between the two differential inputs. This lower input impedance can be advantageous in applications where impedance matching or low noise are important.

It will be appreciated by those of skill in the art that while the exemplary embodiments described herein refer to the use of a n⁺ diffusion in a buried n-channel structure, other channel structures can be configured in accordance with the present invention. For example, the n⁺ diffusion can be provided in a p-type substrate to form a surface n- channel device. Alternatively, a p⁺ diffusion can be provided in a n-type substrate as part of a surface p- channel device, or the p⁺ diffusion can be provided in a p- type layer of a buried p-channel device. Accordingly, the p⁺ diffusion provides the same functions and advantages as described for the n⁺ diffusion. In addition, while the illustrated exemplary embodiments were described using a uniphase clocking scheme, it is well known in the art to use multiphase clocking schemes as well.

It will be further appreciate that the charge transfer device of the present invention can also be configured as a magnetic field sensor. In the sampling mode, the device structure transfers charge forward at very high speeds. In the presence of a magnetic field, the charge experiences a Lorentz force that causes a lateral movement of charge even if the differential voltage input is zero. Hence, an imbalance occurs in the two output charge packets that is proportional to the magnetic field strength. The operation of charge domain magnetic field sensors are described in more detail in a copending patent application filed by the Applicant on May 30, 1995 as U.S. Pat. Appl. Ser. No. 08/409,809, entitled "RECIRCULATING CHARGE TRANSFER MAGNETIC FIELD SENSOR", incorporated herein by reference.

Although the sensitivity of a single charge transfer device of the present invention configured as a magnetic field sensor may be relatively low, multiple sensor stages are cascaded to increase gain. For example, the outputs of one stage are coupled to the voltage inputs of the next stage in such a manner that the second stage is amplifying the differential output of the first stage, while simultaneously contributing its own magnetic field sensitivity. Therefore, a cascade of multiple stages would tend to yield very high sensitivity.

The foregoing description has been set forth to illustrate the invention and is not intended to be limiting. Since modifications of the described embodiments incorporating the spirit and substance of the invention may occur to persons skilled in the art, the scope of the invention should be limited solely with reference to the appended claims and equivalents thereof.

What is claimed is:

Claims

I. A charge transfer device comprising: a reference charge signal generator which generates a reference charge signal in response to receiving a control signal; first and second charge signal channels arranged to receive portions of said reference charge signal; and a reference charge signal distributor which distributes said reference charge signal between said first and second charge signal channels in accordance with a ratio determined by a differential input signal.

2. The device of claim 1, wherein said device is constructed as a charge-coupled device (CCD).

3. The device of claim 2, wherein said generator comprises a source diffusion and at least a first pair of gates each having respective first potential wells electrically coupled to one another.

4. The device of claim 3, wherein said first pair of gates generate said reference charge signal by extracting a charge packet from said source diffusion in response to having said control signal applied thereto, said charge packet being divided between said first potential wells.

5. The device of claim 3, wherein said first potential wells each include high conductivity regions which are electrically coupled to one another.

6. The device of claim 5, wherein said high conductivity regions each comprise a diffusion of a material of a predetermined conductivity type.

7. The device of claim 6, wherein said diffusion comprises an n⁺ diffusion disposed proximate to openings in said first pair of gates.

8. The device of claim 3, wherein said first and second charge signal channels comprise respective first and second sets of gates and associated isolated charge potential wells.

9. The device of claim 3, wherein said distributor comprises a pair of barrier gates which are driven with said differential input signal.

10. The device of claim 9, wherein said barrier gates are conductively coupled to one another so as to provide a low input impedance to said first and second charge signal channels.

11. The device of claim 1, wherein said distributor comprises first and second FET transistors, respectively, configured with a common source node and having gates driven by said differential input signal.

12. The device of claim 1, wherein said generator comprises a capacitor having a first node coupled to said common source node and a second node coupled to an input node which receives said control signal, said generating means further comprising a third FET transistor having a source coupled to a reference signal, a gate coupled to said input node, and a drain coupled to said common source node.

13. The device of claim 1, wherein said distributor comprises first and second bipolar transistors, respectively, configured with a common emitter node and having bases driven by said differential input signal.

14. The device of claim 1, wherein said device is configured as a charge domain sample and hold circuit.

15. The device of claim 1, wherein said device is configured as a charge domain comparator circuit.

16. The device of claim 1, wherein said device is configured as a charge domain amplifier circuit.

17. The device of claim 1, wherein said device is configured as a charge domain magnetic field sensor.

18. A charge transfer device comprising: a reference charge packet source which generates a reference charge packet in response to receiving a control pulse; first and second signal channels arranged to receive portions of said reference charge packet, said signal channels including respective first and second sets of gates having isolated potential wells; and first and second barrier gates having a differential input signal applied thereto, said first and second barrier gates operable for steering portions of said reference charge packet to said first and second signal channels in accordance with a ratio corresponding to said differential signal.

19. The device of claim 18, wherein said charge packet generator comprises a source diffusion and a first and second storage gates which are driven by said control pulse, and having first and second isolated storage wells which are conductively coupled to one another.

20. The device of claim 19, wherein each of said first and second storage wells include high conductivity regions which are electrically tied together.

21. The device of claim 20, wherein said high conductivity regions are defined by n⁺ diffusions.

22. The device of claim 20, wherein said first and second storage gates generate said reference charge packet by extracting charge from said source diffusion in response to said control pulse, said charge packet being divided between said storage wells so as to maintain equivalent potentials.

23. The device of claim 18, wherein said barrier gates are conductively coupled to one another so as to define a low input impedance between said first and second signal channels.

24. The device of claim 18, wherein said device is configured as a charge domain sample and hold circuit.

25. The device of claim 18, wherein said device is configured as a charge domain comparator circuit.

26. The device of claim 18, wherein said device is configured as a charge domain amplifier circuit.

27. The device of claim 18, wherein said device is configured as a charge domain magnetic field sensor circuit.

28. A method of transferring charge within a circuit, said method comprising: generating a reference charge signal in response to receiving a control signal; providing first and second charge signal channels arranged to receive portions of said reference charge signal; and distributing said reference charge signal between said first and second charge signal channels in accordance with a ratio determined by a differential input signal.