WO1997013320A1 - Amplificateur de puissance et dispositif de telecommunications - Google Patents
Amplificateur de puissance et dispositif de telecommunications Download PDFInfo
- Publication number
- WO1997013320A1 WO1997013320A1 PCT/JP1996/002770 JP9602770W WO9713320A1 WO 1997013320 A1 WO1997013320 A1 WO 1997013320A1 JP 9602770 W JP9602770 W JP 9602770W WO 9713320 A1 WO9713320 A1 WO 9713320A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- switch
- terminal
- amplifier
- power amplifier
- passive circuit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
- H03F3/602—Combinations of several amplifiers
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
- H03F3/72—Gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/294—Indexing scheme relating to amplifiers the amplifier being a low noise amplifier [LNA]
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2200/00—Indexing scheme relating to amplifiers
- H03F2200/372—Noise reduction and elimination in amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03F2203/7215—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by a switch at the input of the amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03F2203/7221—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by a switch at the output of the amplifier
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03F2203/7231—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by putting into cascade or not, by choosing between amplifiers by one or more switch(es)
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03F2203/7233—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier, switched on or off by putting into parallel or not, by choosing between amplifiers by one or more switch(es), being impedance adapted by switching an adapted passive network
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03F—AMPLIFIERS
- H03F2203/00—Indexing scheme relating to amplifiers with only discharge tubes or only semiconductor devices as amplifying elements covered by H03F3/00
- H03F2203/72—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal
- H03F2203/7236—Indexing scheme relating to gated amplifiers, i.e. amplifiers which are rendered operative or inoperative by means of a control signal the gated amplifier being switched on or off by putting into parallel or not, by choosing between amplifiers by (a ) switch(es)
Definitions
- the present invention relates to a power amplifier and a communication device that handle signals having at least one of different frequencies, output powers, and modulation schemes, and particularly to a power amplifier and a communication device having at least one switch.
- Japanese automobile telephones ⁇ Bandy telephones have analog communication method, F (Frequency Modulation) modulation method and digital method, and ⁇ 4 shift DQP SK (Differential Quadrature Phase Shift Keying) modulation method.800 MHz frequency band
- the analog and digital methods are assigned to the z band, and the digital method is assigned to the 1.5 GHz band.
- the simplified mobile phone PHS Personal Handy-phone System
- the output power is about 1W for mobile phones and mobile phones, and 1 OmW for simple mobile phones.
- the former has a cell radius of several kilometers and has a handover function, so communication is possible even when moving by car, etc.
- the latter has a cell radius of several hundred meters, and is positioned to use conventional indoor cordless phones outdoors.
- the 2.4 GHz band of the ISM (Industrial Scientific Medical) band which is allocated worldwide for industrial, scientific, and medical uses, is used as a wireless LAN (Local Area Network) for offices, factories, and premises, as a spread spectrum (SS) ) It is being considered to use the output power of 1 OmW in MHz (frequency range 26MHz). in this way,
- FIG. 35 is a block diagram of a conventional example.
- the conventional example is a multi-stage power amplifier that transmits two types of high-frequency signals having different frequencies ⁇ and output power, and uses two groups of power amplifiers corresponding to each frequency band.
- the first power amplifier PA1 includes a first input matching circuit PA104, a first GaAs MESFET PA101, a first interstage matching circuit PA105, a second GaAsMESFET PA102, and a second interstage matching. Circuit PA106, third GaAs ME SFET PA103, and first output matching circuit PA107.
- the second power amplifier PA2 includes a second input matching circuit PA204, a fourth GaAs ME SFET PA201, a third interstage matching circuit PA205, a fifth GaAsM ESFET PA202, a fourth interstage matching circuit PA206, It comprises a sixth GaAsME SFET PA203 and a second output matching circuit PA207.
- this conventional power amplifier when configuring a power amplifier that can handle different output powers, modulation methods, and frequency bands, the number of components increases, which goes against miniaturization of terminals and increases costs. Has problems.
- FIG. 36 is a simplified diagram of a high-frequency integrated circuit disclosed in Japanese Patent Application Laid-Open No. 8-88524 (publication date: April 2, 1996) published after the priority date of the present application. It is.
- the above publication relates to a high-frequency integrated circuit provided with an amplifier operating in an analog system and a digital system.
- the drain 3604 of the FET 3601 at the last stage of the amplifier is connected to the input terminal of the analog output matching circuit PC 1 and the input terminal of the digital output matching circuit PC 2 via the switch SW 1.
- Be closely related to The output terminal of the analog output matching circuit PC 1 and the output terminal of the digital output matching circuit PC 2 are connected to the output terminal 3605 via the switch SW 2.
- Fig. 37 is a graph (a) showing the change in distortion D and power added efficiency (the ratio of the difference between the input and output high-frequency power to the DC input power of the amplifier) and the input power P in the circuit of Fig. 36.
- Graph (b) showing the change in output power Pout with respect to in.
- FIG. 38 is a graph showing the input power dependence of the output matching circuits PC1 and PC2.
- the horizontal axis indicates the input power P in
- the vertical axis indicates the output power P out.
- Pn indicates the rated output power.
- the distortion and power added efficiency are low when the output power is linear with respect to the input power, and the distortion and power added efficiency increase when the input power increases and becomes nonlinear.
- PC1 for the analog system and PC2 for the digital system of the power amplifier are configured so as to have input / output characteristics of high-frequency power as shown in FIG. That is, the PC 1 for the analog system is configured so that the output power does not need to be linear with respect to the input power during operation, and the power added efficiency is high (that is, efficiency matching).
- the PC 2 for the digital system is configured so that the output power is linear with respect to the input power so that the high-frequency signal passing through the amplifier is not distorted during operation (ie, distortion matching). At this time, the power added efficiency is lower than that of the analog type.
- the integrated circuit described in the above-mentioned Japanese Patent Application Laid-Open No. 8-88524 is compatible with an analog Z-digital signal with the same frequency band (900 MHz band) and the same output power. Therefore, in the above-described integrated circuit, the output matching circuits PC1 and PC2 are impedance-matched so as to minimize the loss of the transmission signal in the same frequency band.
- the output power is different, for example, when 1 W class and 10 OmW class power are handled by PC 1 and PC 2, respectively, 10 OmW class power is output using an active element that can output 1 W class power.
- a mechanism that controls the input power of the FET is essential. If the input power is reduced under such a control mechanism to operate in the 10 OmW class, the power added efficiency is extremely lower than that in the 1 W class operation, which leads to an increase in power consumption. As a result, there is a problem that the battery life is shortened when the information communication device is driven by a battery.
- a tortoise amplifier of the present invention includes a first amplifier having an input terminal and an output terminal, a passive circuit having an input terminal and an output terminal, a single-pole terminal, and two multi-throw terminals.
- a power switch comprising: a first switch; and a multi-throw terminal of the first switch, wherein one of the multi-throw terminals of the first switch is connected to the input terminal of the first switch.
- the apparatus further comprises a second switch having a single pole terminal and two multi-throw terminals, wherein one of the multi-throw terminals of the second switch is the output terminal of the first amplifier.
- the other of the multiple throw terminals of the second switch is connected to the output terminal of the passive circuit.
- the first amplifier is constituted by discrete components.
- the device further comprises a second amplifier having an input terminal and an output terminal, wherein the single-pole terminal of the first switch is connected to the output terminal of the second amplifier.
- the 3 dB bandwidth of the second amplifier includes a range from about 800 MHz to about 2.5 GHz.
- the gain characteristic of the second amplifier includes at least two peaks.
- the first band which is a frequency range of 13 dB from the first gain at the first peak of the gain characteristic of the second amplifier includes 1.5 GHz
- the gain characteristic of the second amplifier is The second band, which is a frequency range of ⁇ 3 dB from the second gain at the second peak of, includes 1.9 GHz.
- the first band which is a frequency range of ⁇ 3 dB from the first gain at the first peak of the gain characteristic of the second amplifier, includes 900 MHz, and the second band of the gain characteristic of the second amplifier.
- the second band which is a frequency range of 3 dB from the second gain at the peak, includes 1.9 GHz.
- the first switch and the second amplifier are formed on the same semiconductor substrate.
- the passive circuit is formed on the semiconductor substrate.
- the power supply control circuit further includes a power supply control circuit that controls power supplied to the first amplifier in accordance with switching of the first switch.
- the first amplifier receives an analog signal and amplifies it.
- the passive circuit receives and outputs a digital signal.
- the first amplifier receives and outputs a first digital signal
- the passive circuit receives and outputs a second digital signal.
- the first amplifier receives and outputs a signal of a first frequency
- the passive circuit receives and outputs a signal of a second frequency, wherein the first frequency and the second frequency are different from each other. .
- the first frequency is higher than the second frequency.
- the first amplifier outputs a signal of a first output power
- the receiving circuit outputs a signal of a second output power, and the first output power with respect to the second output power.
- the communication device of the present invention comprises: a first amplifier having an input terminal and an output terminal; a passive circuit having an input terminal and an output terminal; a single-pole terminal; and two multi-throw terminals.
- a first switch having a single pole terminal, a second switch having two multi-throw terminals, a single switch terminal, a third switch having two multi-throw terminals, a front end circuit,
- a communication device comprising: an antenna; and one of the multi-throw terminals of the first switch is connected to the input terminal of the first amplifier; and the other of the multi-throw terminals of the first switch is Connected to the input terminal of the passive circuit, and connected to the input terminal of the second switch.
- One of the throw terminals is connected to the output terminal of the first amplifier, the other of the multiple throw terminals of the second switch is connected to the output terminal of the passive circuit, and the third switch One of the multi-throw terminals of the third switch is connected to the single pole terminal of the second switch, and the other of the multi-throw terminals of the third switch is connected to the front-end circuit.
- the single pole terminal of the three switches is connected to the antenna, thereby achieving the above object.
- a communication device includes a first amplifier having an input terminal and an output terminal, a passive circuit having an input terminal and an output terminal, a single switch having a single pole terminal, and two multi-throw terminals.
- a communication device comprising a first antenna and a second antenna, wherein one of the multiple throw terminals of the first switch is connected to the input terminal of the first amplifier; The other of the multiple throw terminals of the switch is connected to the input terminal of the passive circuit, the output terminal of the first amplifier is connected to the first antenna, and the other end of the second amplifier is connected to the input terminal of the passive circuit.
- the output terminal is connected to the second antenna, thereby achieving the above object.
- a power amplifier includes: a first amplifier having an input terminal and an output terminal; a second amplifier having an input terminal and an output terminal; a single switch having a single pole terminal; and a first switch having two multi-throw terminals.
- One of the multi-throw terminals of the first switch is connected to the input terminal of the first amplifier, and the other of the multi-throw terminals of the first switch is the multi-throw terminal.
- the input terminal of the second amplifier is connected to the input terminal, thereby achieving the above object.
- the apparatus further comprises a second switch having a single pole terminal and two multi-throw terminals, wherein one of the multi-throw terminals of the second switch is the output terminal of the first amplifier.
- the other of the multiple throw terminals of the second switch is connected to the output terminal of the second amplifier.
- the first amplifier and the second amplifier are configured by discrete components.
- the unipolar terminal of the first switch is connected to an output terminal of a third amplifier.
- the 3 dB bandwidth of the third amplifier includes a range from about 800 MHz to about 2.5 GHz.
- a gain characteristic of the third amplifier includes at least two peaks.
- the first band, which is a frequency range of 13 dB from the first gain at the first peak of the gain characteristic of the third amplifier includes 1.5 GHz
- the third amplifier includes:
- the second band, which is a frequency range of 13 dB from the second gain at the second peak of the gain characteristic of the second characteristic includes 1.9 GHz.
- the first band, which is a frequency range of 13 dB from the first gain at the first peak of the gain characteristic of the third amplifier includes 900 MHz
- the second band, which is a frequency range of 13 dB from the second gain at the second peak of the gain characteristic includes 1.9 GHz.
- the power supply control device further includes a power supply control circuit that controls power supplied to at least one of the first amplifier and the second amplifier in accordance with the switching of the first switch.
- the first amplifier receives and amplifies and outputs an analog signal
- the second amplifier receives and amplifies and outputs a digital signal.
- the first amplifier receives a first digital signal and outputs
- the second amplifier receives and outputs a second digital signal.
- the first amplifier receives and outputs a signal of a first frequency
- the second amplifier receives and outputs a signal of a second frequency, wherein the first frequency and the second frequency are mutually related. different.
- the first frequency is higher than the second frequency.
- the first amplifier outputs a signal of a first output power
- the second amplifier outputs a signal of a second output power, and a ratio of the first output power to the second output power. Is 5 or more.
- a communication device includes: a first amplifier having an input terminal and an output terminal; a second amplifier having an input terminal and an output terminal; a first switch having a single-pole terminal; and two multi-throw terminals;
- a communication device comprising: a second switch having a single-pole terminal, two multi-throw terminals; a third switch having a single-pole terminal, two multi-throw terminals; a front-end circuit; and an antenna.
- One of the multi-throw terminals of the first switch is connected to the input terminal of the first amplifier, and the other end of the multi-throw terminal of the first switch is connected to the input of the second amplifier.
- One of the multi-throw terminals of the second switch is connected to the output terminal of the first amplifier, and the other of the multi-throw terminals of the second switch is connected to the multi-throw terminal.
- One of the multi-throw terminals of the third switch is connected to the single pole terminal of the second switch, the other of the multiple throw terminals of the third switch is connected to the front end circuit, and the single pole terminal of the third switch is connected to the single pole terminal of the third switch.
- the child is connected to the antenna, thereby achieving the above object.
- a communication device includes: a first amplifier having an input terminal and an output terminal; a second amplifier having an input terminal and an output terminal; a first switch having a single-pole terminal; and two multi-throw terminals; A communication device having a first antenna and a second antenna
- a communication device includes a first switch having an input terminal and an output terminal, a second passive circuit having an input terminal and an output terminal, a single pole terminal, and a first switch having two multi-throw terminals.
- An amplifier having an input terminal and an output terminal, wherein one of the multiple throw terminals of the first switch is connected to the input terminal of the first passive circuit; The other of the multi-throw terminals of one switch is connected to the input terminal of the second passive circuit, and the output terminal of the amplifier is connected to the single pole terminal of the first switch.
- a second switch having a single-pole terminal and two multi-throw terminals is further provided, and one of the multi-throw terminals of the second switch is the same as that of the first passive circuit.
- the other of the multiple throw terminals of the second switch is connected to the output terminal of the second passive circuit.
- the amplifier is constituted by discrete components.
- the 3 dB bandwidth of the amplifier includes a range from about 800 MHz to about 2.5 GHz.
- the gain characteristic of the amplifier includes at least two peaks.
- the first band, which is a frequency range of 13 dB from the first gain at the first peak of the gain characteristic of the amplifier includes 1.5 GHz
- the second band of the gain characteristic of the amplifier is The second band, which is a frequency range of 13 dB from the second gain at the peak
- the 10 Replacement form (Rule 26) Includes 1.9 GHz.
- the first band which is a frequency range of 13 dB from the first gain at the first peak of the gain characteristic of the amplifier, includes 900 MHz
- the gain characteristic of the second amplifier is The second band, which is a frequency range of 13 dB from the second gain at the second peak, includes 1.9 GHz.
- the first switch and the amplifier are formed on the same semiconductor substrate.
- at least one of the first passive circuit and the second passive circuit is formed on the semiconductor substrate.
- the first passive circuit receives and outputs an analog signal
- the second passive circuit receives and outputs a digital signal.
- the first passive circuit receives and outputs a first digital signal
- the second passive circuit receives and outputs a second digital signal.
- the first passive circuit receives and outputs a signal at a first frequency
- the second passive circuit receives and outputs a signal at a second frequency, the first frequency and the second frequency.
- the first frequency is higher than the second frequency.
- a communication device includes a first switch having an input terminal and an output terminal, a second passive circuit having an input terminal and an output terminal, a single pole terminal, and a first switch having two multi-throw terminals.
- a second switch having a single pole terminal, two multi-throw terminals, a third switch having a single pole terminal, and two multi-throw terminals, and a front end.
- a communication device comprising: a circuit; an antenna; and one of the multi-throw terminals of the first switch is connected to the input terminal of the first passive circuit, and the multi-throw terminal of the first switch.
- the other of the terminals is connected to the input terminal of the second passive circuit, and one of the multiple throw terminals of the second switch is connected to the output terminal of the first passive circuit;
- the other of the multiple throw terminals of the second switch is connected to the output terminal of the second passive circuit, and one of the multiple throw terminals of the third switch is connected to the single pole of the second switch.
- the other of the multiple throw terminals of the third switch is connected to the front end circuit, and the single pole terminal of the third switch is connected to the antenna.
- a communication device includes a first switch having an input terminal and an output terminal, a second passive circuit having an input terminal and an output terminal, a single pole terminal, and a first switch having two multi-throw terminals.
- a communication device comprising: a first antenna; and a second antenna, wherein one of the multiple throw terminals of the first switch is connected to the input terminal of the first passive circuit. The other of the multiple throw terminals of one switch is connected to the input terminal of the second passive circuit, the output terminal of the first amplifier is connected to the first antenna, and The output terminals of the two amplifiers are connected to the second antenna, thereby achieving the above object.
- a third passive circuit having an input terminal and an output terminal, a fourth passive circuit having an input terminal and an output terminal, a second switch having a single pole terminal, and two multi-throw terminals are provided.
- a third switch having a single pole terminal and two multi-throw terminals, one of the multi-throw terminals of the second switch being connected to the input terminal of the third passive circuit.
- the other of the multiple throw terminals of the second switch is connected to the input terminal of the fourth passive circuit, and one of the multiple throw terminals of the third switch is coupled to the third passive circuit.
- the other of the multiple throw terminals of the third switch is connected to the output terminal of the fourth passive circuit.
- a fourth switch having a single pole terminal and two multiple throw terminals,
- One of the multiple throw terminals of the fourth switch is connected to the output terminal of the first passive circuit, and the other of the multiple throw terminals of the fourth switch is connected to the second throw terminal. It is connected to the output terminal of the passive circuit.
- a communication device includes: a first passive circuit having an input terminal and an output terminal; a second passive circuit having an input terminal and an output terminal; a third passive circuit having an input terminal and an output terminal; A fourth passive circuit having an output terminal, a single pole, a first switch having two multi-throw terminals, a single pole terminal, a second switch having two multi-throw terminals, and a single pole terminal; A third switch having two multi-throw terminals; a fourth switch having a single-pole terminal; two multi-throw terminals; a fifth switch having a single-pole terminal; and two multi-throw terminals.
- a power amplifier comprising: an amplifier having an input terminal and an output terminal; a front end circuit; and an antenna, wherein one of the multiple throw terminals of the first switch is connected to the input of the first passive circuit. Connected to the first switch. The other of the multi-throw terminals is connected to the input terminal of the second passive circuit, the output terminal of the amplifier is connected to the single-pole terminal of the first switch, and the second One of the multiple throw terminals of the switch is connected to the input terminal of the third passive circuit, and the other of the multiple throw terminal of the second switch is connected to the input terminal of the fourth passive circuit.
- a power amplifier according to the present invention has a first passive circuit having an input terminal and an output terminal, a second passive circuit having an input terminal and an output terminal, and an input terminal and an output terminal.
- a fourth passive circuit having an input terminal and an output terminal, a single switch, a first switch having two multi-throw terminals, a single pole terminal, and two multi-throw terminals.
- a second switch having a single pole terminal, a third switch having two multi-throw terminals, an amplifier having an input terminal and an output terminal, a first antenna, and a second antenna.
- One of the multi-throw terminals of the first switch is connected to the input terminal of the first passive circuit, and the other end of the multi-throw terminal of the first switch is connected to the second throw terminal.
- the input terminal of the passive circuit is connected to the input terminal of the amplifier, the output terminal of the amplifier is connected to the single pole terminal of the first switch, and the negative terminal of the multi-throw terminal of the second switch is connected to The other of the multi-throw terminals of the second switch, which is connected to the input terminal of the third passive circuit.
- One of the multi-throw terminals of the third switch is connected to the output terminal of the third passive circuit, and the third input terminal of the third switch is connected to the output terminal of the third passive circuit.
- the other of the multi-throw terminals of the switch is connected to the output terminal of the fourth passive circuit, the output terminal of the first passive circuit is connected to the first antenna, and (2) The output terminal of the passive circuit is connected to the second antenna by gun, thereby achieving the above object.
- a power amplifier that can share different types of systems, that is, different types of frequency bands, transmission output powers, and modulation systems, and that can be reduced in size and cost by the above configuration, and has a high additional load by using the same. A valuable communication device can be provided.
- FIG. 1 is a configuration diagram showing a first embodiment of a power amplifier with a switch according to the present invention.
- FIG. 2 is a diagram for explaining the impedance of the matching circuit.
- FIG. 3 is a diagram showing an equivalent circuit of the input matching circuit PC1 or PC2 and the first GaAs MESFETPA101.
- FIG. 4 is a diagram showing a specific configuration example of the power amplifier with switch of the present embodiment.
- Figure 5 shows a configuration example of a power amplifier with a switch having a feedback control unit.
- FIG. 6 is a diagram illustrating another configuration example of a power amplifier with a switch having a feedback control unit.
- FIG. 7 is a block diagram of a general information communication device.
- FIG. 8 is a configuration diagram of an information communication device using the power amplifier with a switch according to the present invention.
- FIG. 9 is a configuration diagram of a first DPDT switch 152 that combines the first single-pole two-throw switch 1339 and the second single-pole two-throw switch 140 of FIG.
- FIG. 10 is a configuration diagram of a transmission / reception switch for performing diversity transmission / reception using two mode 2 antennas and two filters in FIG.
- FIG. 11 is a configuration diagram of a communication device using the power amplifier with a switch according to the present invention.
- FIG. 12 is a diagram showing a portion of the power amplifier according to the present invention that is converted to MMIC.
- FIG. 13 is a configuration diagram in which the switch-equipped power amplifier 109 of this embodiment is realized by MMIC and hybrid IC.
- FIG. 14 is a configuration diagram of a second embodiment of the switchable power amplifier according to the present invention.
- FIG. 15 is a circuit diagram of the switches SW1 and SW2.
- FIG. 16 is a circuit diagram of the switch 3 and the SW 4.
- FIG. 17 is a configuration diagram of a power amplifier with a switch according to the second embodiment.
- FIG. 18 is a diagram showing the range of the MMIC conversion part of the present embodiment.
- FIG. 19 is a diagram for explaining the 3 dB bandwidth.
- FIG. 20 is a diagram for explaining a 3 dB bandwidth of an amplifier having two peaks.
- FIG. 21 is a configuration diagram of a third embodiment of the switchable power amplifier according to the present invention.
- FIG. 22 is a diagram for explaining an increase in the bandwidth of the power amplifier.
- FIG. 23 is a configuration diagram of a power amplifier with a switch according to the third embodiment.
- FIG. 24 is a diagram illustrating a part to be converted to MMIC according to the third embodiment.
- FIG. 25 is a configuration diagram of a fourth embodiment of the switchable power amplifier according to the present invention.
- FIG. 26 is a configuration diagram of a power amplifier with a switch according to the fourth embodiment.
- FIG. 27 is a diagram showing a part to be converted into an MM IC according to the fourth embodiment.
- FIG. 28 is a configuration diagram of a power amplifier with a switch according to a fifth embodiment of the present invention.
- FIG. 29 is a configuration diagram of a power amplifier with a switch according to the fifth embodiment.
- FIG. 30 is a diagram showing an MMIC-converted part of the fifth embodiment.
- FIG. 31 is a configuration diagram of a power amplifier with a switch according to a sixth embodiment of the present invention.
- FIG. 32 is a configuration diagram of a power amplifier with a switch of the sixth embodiment.
- FIG. 33 is a diagram showing a part to be converted to MMIC according to the sixth embodiment.
- FIG. 34 shows the output of each of the first passive circuit PC1 and the second passive circuit PC2 connected to the two throw terminals of the first single pole two throw switch SW1 in the power amplifier of Fig. 31.
- FIG. 4 is a configuration diagram in which a second single-pole, two-throw switch SW2 is connected to a terminal.
- FIG. 35 is a block diagram of a conventional example.
- FIG. 36 is a simplified diagram of the circuit diagram of the ffi frequency integrated circuit described in Japanese Patent Application Laid-Open No. H8-88524.
- FIG. 37 is a graph showing a change in distortion and power added efficiency with respect to the input torque in the circuit of FIG. 36, and a graph showing a change in output power with respect to the input power.
- FIG. 38 is a graph showing the input power dependence of the output matching circuits PC1 and PC2.
- FIG. 39 is a block diagram of a power amplifier and a communication device according to the present invention.
- switch means “single-pole multi-throw switch J.”
- a switch in this specification refers to a single-pole terminal and two multi-throw terminals unless otherwise specified.
- Power amplifier and “communication device” in this specification include a power amplifier with a switch and an information communication device, which will be described later.
- the switched power amplifier according to the invention has two switches synchronized in time.
- the switch-equipped power amplifier of this embodiment can output high-frequency signals of mode 1 and mode 2 shown in the following table.
- the output power is Pout-Pout1
- the output power Pout2.
- the communication method and modulation method in mode 1 and mode 2 are as shown in the table.
- FIG. 1 is a configuration diagram showing a first embodiment of a power amplifier with a switch according to the present invention.
- a first single-pole two-throw switch SW1, a first input matching circuit PC1 for mode 1 and a second input matching circuit PC2 for mode 2 are connected to the input side of the first power amplifier PA1.
- the second power amplifier PA 2 for mode 1 and the second power amplifier PA 3 for mode 2 are connected to the output side of the first power amplifier PA 1 Have been.
- switch SW1 connects the output terminal of input matching circuit PC1 to the input terminal of power amplifier PA1
- switch SW2 connects the output terminal of power amplifier PA1 to the input terminal of power amplifier PA2.
- switch SW1 connects the output terminal of input matching circuit PC2 to the input terminal of power amplifier PA1
- switch SW2 connects the output terminal of power amplifier PA1 to the input terminal of power amplifier PA3.
- the high-frequency signal of mode 1 is received at the input terminal P in 1 and output from the output terminal Pout 1
- the high-frequency signal of mode 2 is received at the input terminal P in 2 and the output terminal Pout 2 Output from
- the first power amplifier PA1 has a first GaAs MESFET (Gas Metal-Semiconductor torFET) PA101.
- the second power amplifier PA2 has a second GaAs MESFET PA201, a first interstage matching circuit PA202, and a first output matching circuit PA203.
- the third power amplifier PA3 has a third GaAs MESFET PA301, a second inter-stage matching circuit PA302, and a second output matching circuit PA303.
- the first, second, and third GaAs MESFETs PA 101, PA 201, and PA 301 that constitute the first power amplifier PA1, the second power amplifier PA2, and the third power amplifier PA 3, respectively, are of a depletion type.
- the gate width (Wg) is 1 mm, 4 mm, and 8 mm, respectively.
- the first and second GaAs MESFETs PA101 and PA201 having Wg of 1 mm and 4 mm are mounted on a resin mold package.
- the third GaAsMESFET PA301 with a Wg of 8 mm is mounted on a ceramic package (that is, mounted on a ceramic carrier and sealed with a resin).
- the first and second single-pole, two-throw switches SW1 and SW2 are circuits that use PIN diodes (resin-molded PIN diodes, DC cut capacitors used as peripheral circuits for PIN diodes, and resistance components). And a circuit including a choke coil with an inductance component) or an integrated circuit using a GaAs MESFET (a circuit in which GaAs MESFET and its peripheral elements are integrated and resin-molded). Good.
- the first, second, and third GaAs MESFETs PA101, PA201, and PA301 have an operating power supply voltage of about 3.5 V for the drain voltage and a negative voltage (about 2.0 V to about 3.0 V for the gate voltage). ).
- the first GaAsMESFET PA101 emphasizes gain, and the second and third GaAsMESFETs PA201 and PA301 operate in class AB with emphasis on linearity of input / output characteristics and digital distortion characteristics (approx. % Idle current).
- I ds s refers to the drain-source current when the gate and source are short-circuited (that is, at zero bias).
- the Idss of the first, second, and third GaAs MESFETs are about 250 mA, 900 mA, and 1.7 A, respectively.
- the input matching circuit, interstage matching circuit, and output matching circuit that constitute the first, second, and third power amplifiers PA1, PA2, and PA3 have desired characteristics according to the frequency, output power, and modulation method. It has functions and configurations that satisfy the following.
- FIG. 2 is a diagram for explaining the impedance of the matching circuit.
- the input impedances of GaAsMESFET at frequencies f1 and f2 are different from each other. Therefore, the first and second input matching circuits PC 1 and PC 2 have the signal source impedance (here, externally connected at frequency f 1 (1.9 GHz) and frequency ⁇ 2 (2.4 GHz), respectively).
- the transmission RF section such as the transmission mixer section, is assumed to have an impedance as viewed from the power amplifier with a switch.)
- ⁇ and the input impedance Z II of the first GaAs MESFET PA 101 are made equal (that is, impedance matching is performed). This optimizes the input return loss.
- the return loss is preferably at least 6 dB.
- the first inter-stage matching circuit PA 202 matches at a frequency of 1 such that the output impedance Z 01 of the first GaAs MESFET PA101 and the input impedance Z 12 of the second GaAs MESFET PA 201 become equal.
- the first output matching circuit PA203 performs matching so that the output impedance Z02 of the second GaAs MESFET PA201 is equal to the load impedance ZL on the antenna side at the frequency f1.
- the second interstage matching circuit PA302 and the second output matching circuit PA303 also perform the same matching at the frequency f2.
- the first interstage matching circuit PA202 and the first output matching circuit PA203 are loads of the first and second GaAsMESFETs PA101 and PA201 at the frequency f1.
- the second interstage matching circuit PA302 and the second output matching circuit PA303 are loads of the first and third GaAs MESFETs PA101 and PA301 at the frequency f2, respectively. These loads consist of the first GaAs MESFET PA101, the second GaA
- the interstage matching circuit ⁇ 202 provides sufficient output power (that is, gain) for the GaAsMESFE PA101 to drive the GaAsMESFET PA201. Make alignment so that it can be secured.
- IMD adjacent channel leakage power and mutual modulation distortion
- IMD mutual modulation distortion
- the interstage matching circuit and the output matching circuit of the power amplifier of the present invention can be configured to satisfy desired characteristics according to the frequency, output power, and modulation method of the high-frequency signal.
- FIG. 3 is a diagram showing an equivalent circuit of the input matching circuit PC1 or PC2 and the first GaAs MESFET PA101.
- the first GaAs MESFET PA 101 has a drain 101, a source 102, and a gate 103. Drain 101 is connected to power supply terminal 101 1 via choke inductor 104. Seo
- Source 102 is connected to ground via source inductor 105.
- the high frequency signal is input to terminal 1031 and output at terminal 1012.
- the input matching circuit PC 1 can be represented by a series inductance 106, a series capacitance 107 and a parallel capacitance 108, which are lumped element components.
- the equivalent circuits of the interstage matching circuit and the output matching circuit can also be represented by lumped element components. Therefore, the input matching circuit, the interstage matching circuit, and the output matching circuit are not limited to the circuit illustrated in FIG. 3 and can be configured by a combination of lumped constant elements.
- the lumped constant element constituting the above-described matching circuit is realized using a chip component, a chip inductor, a chip capacitor, and a chip resistor.
- FIG. 4 is a diagram showing a specific configuration example of the power amplifier with switch of the present embodiment.
- the components of the switchable power amplifier 109 include drain voltages to the first, second, and third GaAs MESFETs PA101, PA201, and PA301, gate voltage supply units 110, 111, and 112, and first and second It is mounted on the printed circuit board 115 together with the control voltage supply units 113 and 114 of the single-pole two-throw switches SW1 and SW2.
- VddlZVggl, Vdd2ZVgg2, and Vdd3ZVgg3 are drain voltages and gate voltages supplied to the first GaAs MESFET PA 101, the second GaAs MESFET P A201, and the third GaAs MESFET PA301, respectively.
- ⁇ (: 1 and 2 are the control voltages supplied to the first and second single pole double throw switches SW1 and SW2, respectively.
- the drain voltage / gate voltage supply unit 110 controls the power consumption of the PA 101 when the operation of the PA 101 is unnecessary. Is reduced.
- the drain voltage gate voltage supply units 11 1 and 1 12 are also connected to the drain voltage and gate voltage of PA201 and PA301, respectively. Control at least one of them to reduce power consumption.
- the drain voltage is usually
- the drain current Id is reduced by lowering from approximately 3.5 V during operation to approximately 0.0 V during non-operation. Alternatively, the drain current Id is reduced by lowering the gate voltage to about -2.5 V during normal operation to about -5.0 V.
- the drain voltage / gate voltage supply unit 110 includes a drain voltage Vd d1 (for example, 3.5 V) for normal operation and a gate voltage Vg g1 (for example, one-2.5 V) for normal operation. At least one of which is received from an external power supply and the first 03 8 51 ⁇ £ 5 £ PA PA 01 01 operation ⁇ Depending on the non-operation, changing the voltage of Vdd 1 or Vg g 1 PA Output to 101.
- the drain voltage Z gate voltage supply units 111 and 112 also function similarly to the drain voltage nogate voltage supply unit 110.
- the power supply control of the drain voltage Z gate voltage supply units 110, 111, and 112 and the control voltage supply units 113 and 114 of the first and second single-pole two-throw switches SW1 and SW2 are performed in conjunction with each other. It is. More specifically, in mode 1, that is, in a mode in which a high-frequency signal is received at the input terminal P in 1 and output at the output terminal P out 1, the control voltage supply units 113 and 114 receive the control voltage Vc 1 and the control voltage Vc 1 respectively. Upon receiving Vc2, SW1 controls SW1 and SW2 so that SW1 selects Pinl and SW2 selects Pout1. Also, in this mode 1, the PA 301 does not need to operate, so that low power consumption is realized by reducing the drain current Id.
- the drain voltage no-gate voltage supply unit is configured using a chip inductor and a bypass capacitor as a choke, or a microstrip line and a bypass capacitor on a print substrate for mounting a power amplifier with a switch.
- a gain control function to maintain and stabilize a constant output power is indispensable as a function of the transmission power amplifier, and in Athens, automatic gain control (AGC: Auto Gain Control or ALC: It incorporates a power amplifier with an Auto Level Control function and feedbacks and controls the monitored output power.
- the output power is monitored by a capacitor coupling or a directional coupler.
- Fig. 5 shows a configuration example of a power amplifier with a switch having a feedback control unit.
- the first power amplifier PA 1 of the present embodiment has an input terminal 117 at the input side of the first attenuator, or the switch-equipped power amplifier 109 has a second input terminal at the external input side thereof. Athens overnight 118 is provided, and these controls are performed by a feedback control unit 116 that monitors the output power and outputs a control signal.
- Athens fixed-type Attenuators using chip resistors ( ⁇ -type, ⁇ -type Athens) are used, and in electronic attenuators, analog PI- PI diodes, ICs using GaASMESFET, etc., and digital types are used. Unit of Athens overnight (GaAsM
- a unit of Athens J is an element that uses the impedance between the drain and source of one GaAs MESFET to attenuate the signal. Controlling the gate voltage of a unit of Athens changes the amount of attenuation. Is, for example, about
- FIG. 6 is a diagram illustrating another configuration example of a power amplifier with a switch having a feedback control unit. As shown in FIG. 6, according to the output power monitor, the first power amplifier PA1 of the present embodiment or the automatic gain control power amplifier 110 provided on the external input side of the switchable power amplifier 109 of the present embodiment. Adjust the gain and output power by changing the power supply voltage (for example, lowering the drain voltage or reducing the gate voltage).
- FIG. 7 is a block diagram of a general information communication device. The part related to transmission and reception of high-frequency signals and signal processing is divided into a high-frequency (RF) section 120, an intermediate-frequency (IF) signal processing section 121, and a baseband section 122.
- RF high-frequency
- IF intermediate-frequency
- the high-frequency section 120 includes an antenna 123 used for transmission and reception, an antenna duplexer (duplexer) or switch 124, and a front-end section 125.
- the front-end section 125 further includes a transmission section 126 and a reception section 127. Yes.
- the “front-end unit” may refer to a receiving unit, but in this specification, a transmitting unit is also included.
- the transmission unit 126 includes a transmission mixer (up-converter) that converts an intermediate frequency (IF) signal transmitted from the modulator into a high-frequency signal, a voltage-controlled oscillator (VC ⁇ ),
- a transmission mixer up-converter
- IF intermediate frequency
- VC ⁇ voltage-controlled oscillator
- Replacement form (Rule 26) It mainly consists of a power amplifier that amplifies high-frequency signals (including small-signal high-frequency amplifiers here). This portion corresponds to the power amplifier 109 with a switch of the present embodiment.
- the receiver 127 is a low-noise amplifier (LNA) that amplifies the high-frequency signal sent from the antenna 123 and converts the high-frequency signal to a low-frequency IF signal so that the signal can be processed by the IC. It mainly consists of a receiving mixer (down converter).
- LNA low-noise amplifier
- the IF signal processing section 122 is mainly composed of a baseband signal modulation section of the transmission section and a section (mixer, IF amplifier) for further converting and amplifying the IF signal from the front end section of the reception section.
- the baseband unit performs codec for decoding and decoding audio, data, and video signals, and selects channels for transmission multiplexing systems (time division, frequency division, code division), etc. Codec, baseband signal (voice, data), etc.
- a modulator for evening (video signal) (transformation to IF signal on the transmitting side) and a demodulator for IF signal (demodulation to baseband signal on the receiving side). It mainly consists of a frequency discriminator: a discriminator, a modulator, a voice, and a signal processor.
- the baseband section handles either analog signals or digital signals depending on the communication method, and uses analog-only processing ICs and digital-only processing ICs separately, or performs both analog Z digital signal processing according to the communication method. Use an integrated IC.
- a CPU for controlling the above-mentioned units, a memory unit 128, and a power supply unit 129.
- the CPU and the memory unit 128 control the high frequency unit 120, the intermediate frequency signal processing unit 121, and the baseband unit 122 according to a desired communication system.
- the power supply uses a DC-DC converter or a regulator from a battery or commercial power supply to generate a positive or negative power supply according to the operating voltage of each circuit.
- High frequency section 120, intermediate frequency (IF) signal processing section 121, baseband section 122 At least one or more printed circuit boards (such as dielectric boards) are integrated, and these are used for information communication. High-value-added information that can be reduced in size and cost compared to the conventional example, and can be shared with different frequency bands, transmission output power, and modulation methods by mounting them together in a device housing A communication device terminal is obtained.
- FIG. 8 is a configuration diagram of an information communication device using the power amplifier with a switch according to the present invention.
- the information communication device shown in FIG. 8 includes a switch for switching between transmission and reception in each of mode 1 and mode 2.
- a second single-pole double-throw switch 140 and a third single-pole double-throw switch 141 corresponding to mode 1 and mode 2, respectively, are connected to the output side of the switchable power amplifier 138 of the present invention.
- the switches 140 and 141 serve to switch between transmission and reception (mode 1: switching between TX1 and RXI, mode2; switching between TX2 and RX2).
- the first antenna (for mode 1) 142 and the first filter 144 are on the monopole side of the second single-pole, double-throw switch 140, and the single-pole side of the third single-pole, double-throw switch 141 is on the monopole side.
- Second antenna (for mode 2) 143 and second filter 145 1 are connected.
- the first low-noise amplifier 146, the first local amplifier 147, and the first mixer 148 are located on the RX1 side of the mode 1 receiver, and the second mouth noise amplifier is located on the RX2 side of the mode 2 receiver.
- 149, the second local amplifier 150, and the second mixer 151 are connected.
- FIGS. 9 (a) and 9 (b) show the first DP DT in FIG. 8 in which the two single-pole, double-throw switches 139 and 140 are combined.
- FIG. 4 is a diagram showing a specific configuration example of a switch 152 (Du a 1 -Po 1 ed ua 1 -throw).
- 1st single pole 2 throw switch 1 39 single pole P1, 2nd single pole 2 throw switch 140 single pole P2, 1st single pole 2 throw switch 1 39 tip (mode 2 transmit Side) T l, second single-pole two-throw switch 140 Throw end (mode 1 receiving side) ⁇ 2 corresponds to each port of first DPDT switch 152, and first to fourth switching between each port 5th to 8th switching transistors (TSW5 to TSW8) are connected in parallel with the transistor for switching (TSW1 to TSW4) and each port terminal. (The connection may or may not be made according to the basic configuration.) Each port is connected by an SPST (Singl 1 e-po 1 e-sing 1 e-thr ow) switch.
- the transmission / reception switching switch can be constituted by the second DPDT switch 153, and P 1 ′ (second antenna side: for mode 2), P 2 ′ (third antenna side: T1 '(mode 2 transmission side) and T2' (mode 2 reception side) correspond to each port of the second DPDT switch 153, and are used for ninth to 12th switching between each port.
- the 13th to 16th switching transistors are connected in parallel with the transistor (TSW9 to DSW12) and each port terminal.
- the connection may or may not be connected according to one ration, and each port is connected by a SP ST (Sing 1 ep o 1 e s i ng l et hr ow) switch. .
- SP ST Send 1 ep o 1 e s i ng l et hr ow
- FIG. 11 is a configuration diagram of a communication device using the power amplifier with a switch according to the present invention. Unlike Fig. 8, the antenna section is shared between mode 1 and mode 2. A switch 155 for switching the output of mode 1 and mode 2 of the power amplifier with a switch and a switch 156 for switching between transmission and reception are used.
- a first single-pole, two-throw switch 155 for switching between mode 1 and mode 2 is connected to the output side of the switchable power amplifier 138 of the present invention, and then switches between transmission and reception (mode 1: ⁇ XI
- mode 1 mode 1: ⁇ XI
- a second single-pole, two-throw switch 156 is connected, which performs the switching between R XI and R XI, mode 2; switching between ⁇ ⁇ 2 and R ⁇ 2).
- a filter 157 (for both mode 1 and mode 2) and an antenna 158 (for both mode 1 and mode 2) are connected to the single pole side of the second single pole and two throw switch 156.
- Hybrids In order to realize a GaAs MESFET, a single-pole, two-throw switch, an input, an interstage, and an output matching circuit, a configuration using a hybrid IC or MMIC other than the method described above may be used. In the following, including the method explained above (1) Hybrids
- discrete component means a component constituting the hybrid IC described in the following (1).
- discrete components include chip components such as a chip capacitor, a chip inductor, a chip resistor, and a chip FET, and components packaged in an MMIC. This is also true for the following embodiments.
- blind board means a board on which a high-frequency section, an intermediate-frequency signal processing section, or a baseband section is mounted (also referred to as a “mother-to-board board”).
- Hybridization is divided into the following combinations: (1. 1) Ga AsMESFET, (1. 2) Single-pole, double-throw switch, (1. 3) Passive circuit, and (1. 4) 1.1 to 1.3. Will be explained.
- Passive circuit Passive circuit including input, interstage, output matching circuit
- a lumped element is placed on a semiconductor substrate (compound semiconductor such as Si or GaAs).
- the inductance component is microstrip line (high impedance line, etc.), spiral inductor, etc., and the capacitance component is MIM (Metal
- the resistance component is formed by using a thin film resistor (such as NiCr), an ion implantation resistor, or a resistor using an active element.
- a thin film resistor such as NiCr
- an ion implantation resistor such as a ion implantation resistor
- a resistor using an active element such as a resistor using an active element.
- an open-end stub and a short-circuited stub are patterned and used to realize the inductance component and the capacitance component.
- These devices are mounted on a printed circuit board by packaging them with a multi-chip including a GaAs MESFET chip in addition to being mounted on a bare chip.
- the glass epoxy board is used as a mother board on which the high frequency part, intermediate frequency signal processing part, and baseband part are mounted.
- a glass thermoset PPO resin substrate can be used as a multi-layer substrate by creating strip lines and thin film resistors between each layer.
- the ceramic substrate can be patterned on the carrier of the ceramic package and mounted with other components in a multi-chip manner.
- a passive circuit including a matching circuit it is divided into a part to be fabricated on a semiconductor substrate, a part to use chip components, and a part to be patterned and used on a printed circuit board.
- the passive circuit fabricated on the semiconductor substrate described above can be made into a multi-chip with other components such as a GaAs MES FET chip, or integrated as MMIC described later.
- FIG. 12 is a diagram showing a portion of the power amplifier according to the present invention that is converted to MMIC. The following description corresponds to the symbols (A) and (B) — 1 to (B) — 9 in FIG. In Fig. 12, the dotted line
- the enclosed part is the part to be converted into an MM IC.
- the entire power amplifier with switch of the present embodiment is converted to MMIC.
- Input matching circuits PC1, PC2, first and second inter-stage matching circuits PA202, PA302, first and second output matching circuits PA202, PA303 are all MMICs.
- MMIC is selectively performed.
- the second single-pole multi-throw switch SW2, the power amplifier PA1 connected to the single-pole terminal of the second single-pole multi-throw switch SW2, and the multi-throw terminal of the second single-pole multi-throw switch SW2 From the second and third power amplifiers PA2 and PA3, select the components to be converted to MM ICs and combine them on the same semiconductor substrate.
- the main combinations are shown below, but are not limited to them.
- (B) 1 Combine the second single-pole multi-throw switch SW2 and the first power amplifier PA1.
- (B) — 3 Components other than the second single-pole multi-throw switch SW2 and the first power amplifier PA1 (the second and third power amplifiers PA2, PA3, the first and second inputs) At least one of the matching circuits PC1, PC2, etc.).
- (B) -4 Combine the first single pole multi throw switch SW1 and the first power amplifier P A1.
- (B) 1-5 B—The components of (4) and components other than this (second and third power amplifiers PA2, PA3, first and second input matching circuits PC1, PC2, etc.) Combine with at least one of
- (B) 16 Components excluding the first single-pole multi-throw switch SW1 and the first power amplifier PA1 (the second and third power amplifiers PA2 and PA3, the first and second input matching (PCB, PC2, etc.) (except for the overlap with (B) -3).
- (B) -8 The components of (B) -7 and the other components (the second and third power amplifiers PA2, PA3, the first and second input matching circuits PC1, PC2, etc.) Combine with at least one of
- (B) -9 The first power amplifier PA1, and the components excluding the first and second single-pole multi-throw switches SW1 and SW2 (the second and third power amplifiers PA2, PA3, Second input matching circuit PC1, PC2, etc.).
- the second and third power amplifiers PA2 and PA3 are converted to ⁇ ICs
- the second and third power amplifiers ⁇ 2 and ⁇ 3 are converted to MM ICs except for the output matching circuits.
- it also includes selecting the constituent elements (active elements, passive circuits, and the like) of each of the above power amplifiers to form an MMIC.
- one :! ⁇ (B)-The chip converted to MMIC in 9 may be sealed in a resin mold package or mounted with a bare chip.
- (A) and (B) components that are not converted to MMIC are individually mounted on the printed circuit board as described in (1).
- the use of MMIC and hybrid IC is used from the viewpoint of practical low cost and high performance.
- the advantages and disadvantages of MMIC and hybrid IC are inversely related and are interpolated.
- the use of MMIC has the advantage that higher performance, smaller size and lower cost can be achieved by integrating and integrating each functioning component, and high added value can be obtained.
- disadvantages include high cost due to reduced yield in the pre-process and post-process, performance degradation due to the inability to adjust individual components, and heat dissipation of the semiconductor substrate when the output power to be handled is increased to 1 W or more. Due to the limit of radiation, there may be degradation of characteristics (eg, loss of gain) and reliability problems (eg, thermal runaway of the device, device destruction). The reverse of these points is the advantage and disadvantage of hybrid IC.
- FIG. 13 is a diagram illustrating a configuration in which the switch-equipped power amplifier 109 of the present embodiment is realized by MMIC and hybrid IC.
- the power amplifier with switch 109 is a switch-integrated power amplifier in which the above (B)-1, that is, the second single-pole multi-throw switch SW2 and the first power amplifier PA1 are formed on the same semiconductor substrate. 13
- active elements such as enhancement type GaAs MESFETs and transistors (MOSFETs, HBTs, HEMTs, etc.) formed on other semiconductor substrates can also be used. Good.
- the operation requirement of the mobile device assumes a voltage of 3.0 to 3.4 V, which is equivalent to three Ni Cd batteries or one Li ion battery.
- the operating power supply voltage of aAsMESFET is 3.5 V, the operating voltage of other logic I, or other power supply voltage can be set depending on the type of information and communication equipment.
- This embodiment can be realized with an operating voltage other than 3.5 V by using an optimal active element that operates at the specified turtle pressure.
- the gate voltage of the GaAs ME SFET uses the negative voltage generated by the DC-DC converter, but if an active element that operates with a single positive power supply is selected, the negative power supply
- the present embodiment can be realized.
- the first power amplifier PA1, the second power amplifier PA2, and the third power amplifier PA3 of the present embodiment are single-stage amplifiers, multi-stage amplifiers may be used.
- the first power amplifier PA1 A driving power amplifier may be added to the input side.
- the matching circuit constituting the power amplifier has been described as a passive circuit.
- the present invention is not limited to the passive element that plays the role of matching, but also includes a choke inductor of a power supply line, a bypass capacitor, a split resistor for bias application, It also includes passive circuits such as filters, harmonic trap circuits, and Athens.
- the power supply line choke inductor, bypass capacitor, and split resistor for noise application may be included in the MMIC power amplifier. If the frequency of high-frequency signal transmission / reception differs for the filter, output matching is performed.
- a band-pass filter having a predetermined pass bandwidth may be inserted, and a harmonic trap circuit may be inserted into the output matching circuit.
- a single-pole, two-throw switch is used to transmit high-frequency signals corresponding to the two types. However, as the switch for switching, a multi-throw terminal of three or more throws is used.
- the desired power amplifier and information communication device can be configured even with a single-pole / multi-throw switch or a multi-pole / double-throw switch having two or more multi-pole terminals.
- the first and second single-pole two-throw switches SW1 and SW2 are synchronously switched according to the desired transmission frequencies f1 and f2, that is, the frequency is changed to each frequency.
- the first and second input matching circuits PC 1 and PC 2 and the second and third power amplifiers PA 2 and PA 3, fl, f 2, Pout 1 and Pout 2 are respectively different
- the ability to transmit high frequency signals there is a high-frequency signal in which the frequencies f l and f 2 are almost the same and the output powers Pout 1 and Pout 2 of the fl and f 2 are different from each other.
- An example is shown in the table below.
- Mode 2 FM modulation method
- a non-linear or saturated power amplifier can be used as a power amplifier.
- Matching is performed so that a high power added efficiency and a high harmonic component suppression ratio can be obtained at an output power of 31 dBm.
- adjacent channel leakage power and intermodulation distortion IMD: mfa soil nfb [m, n generated when a plurality of different signals are amplified
- IMD intermodulation distortion
- FIGS. 14 to 18 are diagrams for explaining a second embodiment of the switchable power amplifier according to the present invention.
- This power amplifier with a switch has a function of transmitting a high-frequency signal of two types of frequencies and two types of output power by switching the four switches in time synchronization.
- a high-frequency signal having a frequency f and an output power Pout as shown in the following table can be transmitted.
- FIG. 14 is a configuration diagram of a second embodiment of the switchable power amplifier according to the present invention.
- a first single-pole two-throw switch SW1 On the input side of the first power amplifier PA1, a first single-pole two-throw switch SW1, a first input matching circuit PC1 for mode 1, and a second input matching circuit PC2 for mode 2 are provided.
- the output side of the first power amplifier PA 1 has a second single-pole two-throw switch SW2, a first output matching circuit PC 3 for mode 1, and a second output matching circuit PC 3 for mode 2.
- Power amplifier PA2 is connected.
- the second power amplifier PA2 is connected to the third GaA
- the first and second GaAs MESFETs PA101, PA102, and PA201 which constitute the first power amplifier PA1 and the second power amplifier PA2, respectively, are of a depression type, and have a gate width (Wg) of lmm, They are 4 mm and 30 mm.
- "Integrate PA101 and first single-pole, double-throw switch SW1 on GaAs substrate with the first 038.5 ⁇ 5? £ 5, where ⁇ 8 is 1111111 (with first switch The power amplifier SWPA1), and the GaAsMESFET PA102 with Wg of 4 mm and the second single-pole two-throw switch SW2 are integrated on the GaAs substrate (the second power amplifier with switch SWPA2).
- the third GaAs MESFET PA201 with a Wg of 30 mm is mounted in a ceramic package (mounted on a ceramic carrier and sealed with resin) First and second single poles 2
- An integrated circuit using GaAs MESFETs is used for the throw switches SW1 and SW2, and Fig.
- FIG. 15 is a circuit diagram of the switches SW1 and SW2
- An integrated circuit using the GaAs MESFETs is a first parallel GaAs ME SFET 1516 , A first series GaAs MESFET 1517, a second parallel GaAs MES FET 1518, a second series GaAs MESFET 1519, a first resistor 1520, a second It has a resistor 1521, a third resistor 1522, and a fourth resistor 1523.
- control voltages VC 1 and VC 2 By applying control voltages VC 1 and VC 2, the third terminal 1 503, the first terminal 1501, and the second And the terminal 1502.
- the Wg of the above GaAsMES FET is 1.2 mm.
- the third and fourth single-pole, two-throw switches SW3 and SW4 are connected to circuits using PIN diodes (resin-molded PIN diodes and their peripheral circuits, DC cut C, R or L for thyroids), or GaAs MESFETs.
- the integrated circuit used (resin-molded circuit that integrates the GaAs MES FET and its peripheral elements) is used.
- FIG. 16 is a circuit diagram of the switches 3 and SW4. Circuits using PIN diodes include a first parallel PIN diode 1604, a first series PIN diode 1605, a second parallel PIN diode 1606, a second series PIN diode 1607, a first choke inductor 1608, a second Chalk Indak Evening 16
- the first, second, and third GaAs MESFETs PA101, PA102, and PA201 have an operating power supply voltage of about 3.5 V drain voltage and a gate voltage of negative voltage (about 1.
- the first GaAs MESFET PA101 focuses on gain, while the second and third GaAs MESFET PA 102, PA201 focus on linearity of input / output characteristics and digital distortion characteristics. Flow).
- 1 d s s is about 250 mA, 900 mA, and 7.OA, respectively.
- the first and second single-pole double-throw switches SW1 and SW2 are controlled by 0.0VZ-4.7V control voltage, and the third and fourth single-pole double-throw switches SW3 and SW4 are circuits using PIN diodes Then, a control voltage of 0 VZ12 V is used, and a control voltage of 0 V / -4.7 V is used in the harvesting circuit using GaAs MESFET.
- This satisfies the distortion characteristics required in the ⁇ 4 shift DQP SK modulation scheme of the present embodiment.
- the output power of the first power amplifier PA 1 is about 22.5 dBm for input power of about 0 dBm, and about 0.5 in the first output matching circuit PC 3 in mode 1 In the mode 2, the power is finally lost to 31 dBm by the second power amplifier PA2.
- the equivalent circuit is represented by a combination of lumped element components, and the first and second input matching circuits PC 1 and PC 2 and the third interstage matching circuit PA
- the first and second output matching circuits PC3 and PA203 are implemented using chip components such as chip inductors, chip capacitors, and chip resistors.
- FIG. 17 is a configuration diagram of a power amplifier with a switch according to the second embodiment. The theory above
- Vddl / Vggl, Vdd2 / Vgg2, Vcld3 / Vgg3 are drain voltage gate voltages supplied to the first, second, and third GaAs MESFETs
- PA101, PA102, PA201, and Vcl, Vc 2, Vc3, and Vc4 are control voltages supplied to the first, second, third, and fourth single-pole two-throw switches SW1, SW2, SW3, and SW4.
- drain voltage / gate voltage supply units 125, 126, and 127 power control circuit
- the power control of 128, 129, 130, 131 is configured to be linked. For example, if the output selection is Pout 1, SW1 controls the power supply circuit to select Pin1, SW3, SW4 to PC4, and SW2 to Pout1, and the unused PA201 reduces power consumption. Therefore, the drain voltage / gate voltage supply unit 127 is controlled so as not to operate.
- the drain voltage Z gate voltage supply section is configured by using a chip inductor and a bypass capacitor as a choke, or a microstrip line and a bypass capacitor on a print substrate for mounting a power amplifier with a switch.
- a power supply with automatic gain control (AGC, ALC) function in Athens It incorporates an amplifier and controls the output power monitor by feedback.
- the output power is monitored by a capacitor coupling or a directional coupler (for configuration examples, see Figs. 5 and 6 in the first embodiment).
- a power amplifier with a switch is connected to a switch for switching between transmission and reception for modes 1 and 2, and a switch is connected to a switch for performing diversity transmission and reception. Transmission and reception for mode 2 can be performed.
- the antenna unit is shared between mode 1 and mode 2, and the switch for switching the output of mode 1 and mode 2 of the power amplifier with switch and the switch for switching between transmission and reception are connected. By doing so, transmission and reception in mode 1 and mode 2 can be performed.
- FIG. 18 is a diagram showing the range of the MMIC conversion part of the present embodiment. (182) to (185) in the following description correspond to the reference numerals attached to the dotted line portions in FIG. For MMIC conversion shown below (182) and later, only practical ones are shown from the viewpoints of cost, chip manufacturing yield, and so on.
- the present invention is not limited to this, and the configuration and implementation of the hybrid IC and MMIC shown in the first embodiment may be used.
- the first single-pole power amplifier SWP A1 is connected to the third single-pole two-throw switch SW3, the first and second input matching circuits PC1, PC2, the first and second stages. At least one of the matching circuits PC 4 and PC 5 is incorporated and resin-molded.
- the second single-pole two-throw switch SW2 and the second power amplifier PA2 are integrated on a GaAs substrate and molded with resin.
- the second GaAs MIS FET PA102 and the second power amplifier PA2 are integrated on a GaAs substrate and molded with resin.
- the matching circuit converted into an MM IC is composed of a microstrip line on a Ga As substrate, a spiral inductor, a metal insulator metal (MIM) capacitor, a comb capacitor, and a thin film resistor ( NiCr, etc.), and components that are not converted to MM ICs are individually mounted on a printed circuit board.
- MIM metal insulator metal
- NiCr thin film resistor
- the second power amplifier PA2 uses MM ICs for components other than the output matching circuits. As described above, it also includes selecting the constituent elements (active elements, passive circuits, and the like) of each of the above power amplifiers to form an MMIC.
- an enhancement-type GaAs MES FET or a transistor (MOSFET) formed on another semiconductor substrate may be used. , ⁇ , ⁇ , etc.).
- the operation requirement of the mobile device assumes a voltage of 3.0 to 3.4 V, which is equivalent to three Ni Cd batteries or one Li ion battery.
- the operating power supply voltage of aAsMESFET is 3.5V, but other power supply voltages can be set depending on the operating voltage of other logic ICs or the type of information and communication equipment.
- This embodiment can be realized with an operating voltage other than 3.5 V by using an optimal active device that operates at a specified voltage.
- the gate voltage of the GaAs MESFET is a negative voltage generated by a DC-DC converter, but if an active element that operates with a single positive power supply is selected, the negative power supply is eliminated.
- An example is feasible.
- first power amplifier PA1, the second power amplifier PA2, and the third power amplifier PA3 of the present embodiment are single-stage amplifiers, multi-stage amplifiers may be used.
- a driving power amplifier may be added to the input side of the power amplifier.
- the matching circuit constituting the power amplifier has been described as a passive circuit.
- the present invention is not limited to the passive element that plays the role of matching, but also includes a choke inductor of a power supply line, a bypass capacitor, a split resistor for bias application, It also includes passive circuits such as filters, harmonic trap circuits, and Athens.
- a choke inductor, a bypass capacitor, and a bias application split resistor for the power supply line may be included in the power amplifier that has been converted into an MMIC.
- a band-pass filter having a predetermined pass bandwidth may be inserted, or a harmonic trap circuit may be inserted into the output matching circuit.
- a single-pole, two-throw switch is used to transmit high-frequency signals corresponding to the two types, but the switch for switching is a single-pole, multiple-throw terminal having three or more throws.
- a desired power amplifier and information communication equipment can be configured even with a throw switch or a multi-pole two-throw switch having two or more multi-pole terminals.
- Mode 1 ⁇ / 4 shift DQPSK modulation method
- the analog FM modulation method of mode 2 can be used as a non-linear and saturated power amplifier as the power amplifier, and the specified output power 31 d for the second output matching circuit PA203.
- Matching is performed so that a high power added efficiency and a high harmonic component suppression ratio can be obtained in Bm.
- the first output matching circuit PC3 matching is performed so as to obtain high power added efficiency while suppressing adjacent channel leakage power at a specified output power of 22 dBm.
- FIGS. 21 to 24 are diagrams for explaining a third embodiment of the switchable power amplifier according to the present invention.
- This power amplifier with a switch uses a wide-area power amplifier as the driving power amplifier (driver amplifier) for the final output stage power amplifier, and switches two types of frequencies and two types by switching the switches in time. It has the function of transmitting high frequency signals of output power.
- the above-mentioned broadband power amplifier generally has a flat characteristic in a frequency range covering two or more kinds of desired frequencies, and satisfies the desired characteristics.
- FIG. 19 the 3 dB bandwidth ( ⁇ ⁇ ) of the gain is defined as including the desired frequency range (frequency fl to f2), and thereafter, the gain 3 (18 bandwidth) is approximately 800 MHz. Including the frequency of about 2.5 GHz If there is a fluctuation in the flat part of the frequency characteristic in Fig.
- Fig. 20 is a diagram for explaining the 3 dB bandwidth of an amplifier having two peaks. As shown in Fig. 20, the gain is obtained in the case of a two-frequency matched power amplifier. Characteristics to gain at two peaks (first peak P1 and second peak P2) The 3 dB band (mm f 1 and 2) is defined as including the two desired frequencies (f 1 and ⁇ 2).
- the input matching circuit and unnecessary switches required in the first and second embodiments are eliminated, and further miniaturization and higher performance are realized.
- FIG. 21 is a configuration diagram of a third embodiment of the switchable power amplifier according to the present invention.
- a first single-pole two-throw switch SW1 At the output of the first power amplifier PA1, a first single-pole two-throw switch SW1, a second power amplifier PA2 for mode 1 and a third power amplifier PA3 for mode 2 And are connected.
- the first power amplifier PA2 has a second GaAs MESFET PA201, a first interstage matching circuit PA202, and a first output matching.
- the circuit includes a circuit PA203, and the third power amplifier PA3 includes a third GaAs MESFET PA301, a second interstage matching circuit PA302, and a second output matching circuit PA303.
- the first, second, and third GaAs MESFETs PA101, PA201, and PA301 that constitute the first power amplifier PA1, the second power amplifier PA2, and the third power amplifier PA3 are depletion-type gates, respectively.
- the width (Wg) is 1 mm, 4 mm, 8 mm.
- the first GaAs MESFET-101 with Wg of lmm and the first single-pole double-throw switch SW1 are integrated on a GaAs substrate (first power amplifier with switch SWPA1), and the first with a Wg of 4 mm GaAsMESFET PA201, the first interstage matching circuit PA202, and the first output matching circuit PA203 are integrated on a GaAs substrate (first integrated power amplifier MMP A1),
- the third GaAs MESFET PA 301 whose ⁇ is 811 11, the second interstage matching circuit PA302, and the second output matching circuit PA303 are integrated on the GaAs substrate (the second integrated type).
- the first single-pole two-throw switch SW1 uses an integrated circuit using GaAs MESFET (refer to FIG. 15 of the second embodiment for a circuit example).
- the operating power supply voltage of the first, second, and third GaAs MESFETs PA101, PA201, and PA301 is 3.5 V for the drain voltage, and the gate voltage is about 12.0 to about 3.0 V of the negative voltage. It is.
- the first GaAsMESFET PA101 emphasizes gain, and the second and third GaAsMESFET PA201 and PA301 emphasize the linearity of input / output characteristics and digital distortion characteristics.
- Class AB about 10% idle of Idss
- the I d ss of the first, second, and third GaAs MESFEs are about 250 mA, about 900 mA, and about 1.7 A, respectively.
- the first single-pole two-throw switch SW1 is used with a control voltage of 0 V and 4.7 V.
- the input matching circuit and the input matching circuit required in the first and second embodiments are switched by using a wide-area power amplifier as the first power amplifier PA1. Eliminates the need for switches. Generally, the following methods are mainly used to realize such a wide-range operation of the power amplifier.
- (A) to (d) of FIG. 22 are diagrams for explaining the widening of the bandwidth of the power amplifier.
- reference numeral 2201 denotes an active element MESFET
- 2202 denotes an output terminal
- 2203 denotes an input terminal.
- Attachment 2206 such as ⁇ -type or ⁇ -type (first, second, and third resistors R1, R2, and R3) is inserted into the input side of active element 2201 (see FIG. 22). (B)).
- Insert first and second impedance conversion circuits 2208 and 2209 capable of matching in a wide band on the input side and output side of the active element. It may be a constant resistance circuit.
- the broadband power amplifier shown in FIG. 22A is used.
- the first and second inter-stage matching circuits PA202 and PA302 are used to determine the first 0 & 8 at the frequencies ⁇ 1 and 2 Output impedance of the second and third GaAs MESFET PA2
- the equivalent circuit is represented by a combination of lumped element components, and the first and second interstage matching circuits ⁇ 202, ⁇ 302, the first and second output matching circuits ⁇ 203, ⁇ 303 are G a Use a combination of microstrip lines, spiral inductors, MI-M (Metal Insulator Metal) capacitors, comb-shaped capacitors, and thin film resistors (such as NiCr) on an As substrate.
- the first and second interstage matching circuits ⁇ 202, ⁇ 302 the first and second output matching circuits ⁇ 203, ⁇ 303 are G a Use a combination of microstrip lines, spiral inductors, MI-M (Metal Insulator Metal) capacitors, comb-shaped capacitors, and thin film resistors (such as NiCr) on an As substrate.
- MI-M Metal Insulator Metal
- FIG. 23 is a configuration diagram of a power amplifier with a switch of the third embodiment.
- the components of the switch-equipped power amplifier 110 of the present embodiment described above, and the first, second, and third GaAs MESFETs PA101, PA201, and the drain voltage to the PA301 Z gate voltage supply units 111, 112 , 113 and the control voltage supply unit 114 of the first single-pole two-throw switch SW1 are mounted on a printed circuit board 115.
- Vdd lZVgg l Vd d 2 / Vg g 2, Vdd 3 / Vgg 3
- the third GaAs MESFET is the drain voltage / gate voltage supplied to PA101, PA201, # 301, and Vc1 is the control voltage supplied to the first single-pole, double-throw switch SW1.
- the power supply control of these drain voltage / gate voltage supply units 1 1 1, 1 12, 1 13 (power supply control circuit) and the control voltage supply unit 1 14 (power supply circuit) of the first single-pole, 2-throw switch SW1 are linked. It is configured to For example, if the output selection is Pout 1, SW1 controls the feed circuit to select Pout 1, and the unused PA301
- the drain voltage Z gate voltage supply unit 113 is controlled so that it does not operate for low power consumption.
- the drain voltage no-gate voltage supply unit is configured using a chip inductor and a bypass capacitor as a choke, or a microstrip line and a bypass capacitor on a printed circuit board for mounting a power amplifier with a switch.
- a gain control function to maintain and stabilize a constant output power is indispensable as a power amplifier function for transmission, and a power amplifier with automatic gain control (AGC, ALC) function is required.
- the output power monitor is fed back and controlled. The output power is monitored by a capacitor coupling or a directional coupler. (Refer to Fig. 5 and Fig. 6 in Example 1 for a configuration example).
- the parts 122 are integrated on at least one or more printed circuit boards (such as dielectric substrates), and by mounting these on the body of information and communication equipment, miniaturization and cost reduction can be achieved compared to conventional examples. High-value-added information and communication equipment terminals that can use different frequency bands, transmission output powers, and different modulation methods can be obtained.
- FIGS. 8 to 10 of the first embodiment As the specific configuration of the information communication device, the configurations shown in FIGS. 8 to 10 of the first embodiment can be considered.
- a power amplifier with a switch is connected to a switch for switching transmission and reception for mode 1 and mode 2, and a switch for diversity transmission and reception is connected. 1. Mode 2 transmission / reception is possible.
- the antenna section is shared between mode 1 and mode 2, and the switch for switching the output of mode 1 and mode 2 of the power amplifier with switch and the switch for switching between transmission and reception are connected. In this way, transmission and reception in mode 1 and mode 2 can be performed.
- the specific configuration example of the power amplifier with switch of this embodiment is as follows.
- FIGS. 24 (a) to (d) are views showing a part of the third embodiment which is formed into an MMIC.
- Reference numerals 242 to 245 in the following description correspond to reference numerals 242 to 245 indicated by dotted lines in FIG. (242)
- MM ICs shown below only those that are practical from the viewpoints of cost, chip manufacturing yield, etc. are shown.
- the present invention is not limited to this, and the configuration and implementation of the hybrid IC and the MM IC shown in the first embodiment may be used.
- GaAsMESFET single-pole, two-throw switch, matching circuit, and other peripheral circuits are composed of hybrid ICs.
- 0385 1 £ SFET with Wg of lmm and 4111111 is sealed in a resin mold package, and G a AsME SF ET with Wg of 8 mm is mounted in a ceramic package (mounted on a ceramic carrier and sealed with resin. ).
- the matching circuit uses chip inductors, chip capacitors, and chip resistors.
- At least one of the first integrated power amplifier MMPA1 or the second integrated power amplifier MMP A2 is incorporated in the first switched power amplifier SWP A1.
- At least one of the first single-pole two-throw switch SW1 and the second power amplifier PA2 or the third power amplifier PA3 is integrated on the GaAs substrate.
- At least one of the first power amplifier PA1, the second power amplifier PA2, or the third power amplifier PA3 is integrated on a GaAs substrate.
- the chip formed into the MM IC is sealed in a resin mold package or has a configuration such as bare chip mounting, and the matching circuit formed into the MM IC is mounted on a GaAs substrate.
- Components such as microstrip lines, spiral inductors, MIM (Metal Insulator Metal) capacitors, comb-shaped capacitors, and thin-film resistors (such as NiCr). The components are mounted on the printed circuit board.
- the output of the first and second power amplifiers PA1 and PA2, for example, is added to the MM IC.
- the method includes selecting the constituent elements (active elements, passive circuits, etc.) of each of the above power amplifiers and converting them into MMICs.
- GaAs MESFET used as the active element of the power amplifier above, enhancement type GaAs ME SFETs and transistors formed on other semiconductor substrates (MOSFETs, HBTs, HEMTs, etc.)
- An active element such as
- the operation requirement of the portable device is assumed to be a voltage of 3.0 to 3.4 V corresponding to three Ni Cd batteries or one Li ion battery.
- the operating power supply voltage of the MES FET is 3.5 V.
- this embodiment can be realized with an operating voltage other than 3.5 V by using an optimal active device that operates at a specified voltage.
- the negative voltage generated by the DC-DC converter is used as the gate voltage of the GaAs MESFET.
- the negative power supply is eliminated. This embodiment can be realized.
- first power amplifier PA1, the second power amplifier PA2, and the third power amplifier PA3 of the present embodiment are single-stage amplifiers, multi-stage amplifiers may be used.
- a driving power amplifier may be added to the input side.
- the matching circuit constituting the power amplifier is described as a passive circuit.
- passive circuits such as harmonic trap circuits and Athens.
- the power supply line inductor, bypass capacitor, and split resistor for bias application may be included in the MM-IC power amplifier. If the frequency of high-frequency signal transmission / reception differs for the filter, output matching is performed. After the circuit, a band-pass filter having a predetermined pass bandwidth may be inserted, or a harmonic trap circuit may be inserted into the output matching circuit.
- a single-pole, two-throw switch is used to transmit high-frequency signals corresponding to the two types, but the switch for switching is a single-pole, multiple-throw terminal having three or more throws.
- a desired power amplifier and information communication device can be configured even with a throw switch or a multi-pole two-throw switch having two or more poles.
- FIGS. 25 and 26 are diagrams for explaining a fourth embodiment of the switchable power amplifier according to the present invention.
- This power amplifier with a switch uses a broadband power amplifier as the driving power amplifier (driver amplifier) for the final output stage power amplifier and the pre-driving power amplifier (pre-driving amplifier), and switches are switched in time synchronization.
- the broadband power amplifier including the above-mentioned multi-frequency matched power amplifier
- the broadband power amplifier including the above-mentioned multi-frequency matched power amplifier
- the broadband power amplifier including the above-mentioned multi-frequency matched power amplifier
- the power amplifier of this embodiment transmits a high-frequency signal having a frequency f and an output power Pout as shown in the table below.
- FIG. 25 is a configuration diagram of a fourth embodiment of the switchable power amplifier according to the present invention.
- the output of the first power amplifier PA 1 is connected via a first single-pole two-throw switch SW 1 to a second power amplifier PA 2 for mode 1 and a third power amplifier PA 3 for mode 2
- the first power amplifier PA 1 has a first GaAs MESFET PA 101, a first interstage matching circuit PA 103, a second GaAs MESFET PA 102, and the second power amplifier PA 2 has a third power amplifier PA 2.
- the first power amplifier? The first and second ⁇ 38.5 5 ⁇ 1 £ 5? £ ⁇ PA10 1 and PA102, the second power amplifier PA2 the third GaAs MESFET PA201, and the third power amplifier PA3
- the fourth GaAs MESFET PA301 is a depletion type with gate widths (Wg) of 0.6 mm, 2 mm, 4 mm, and 8 mm, respectively.
- the first power amplifier PAl and the first single-pole two-throw switch SW1 are integrated on the GaAs substrate (the first switch-equipped power amplifier SWPA1) to form the second power amplifier PA2.
- the third GaAs MESFET PA201, the second interstage matching circuit PA202, and the first output matching circuit PA203, which are elements, are integrated on a GaAs substrate (first integrated power amplifier MMPA1).
- the fourth GaAs MESFET PA301, which constitutes the power amplifier PA3, the third interstage matching circuit PA302, and the second output matching circuit PA303 are integrated on a GaAs substrate (second The integrated power amplifier MMP A 2) and each is sealed in a resin mold package.
- the first single-pole, double-throw switch SW1 uses an integrated circuit using GaAsMESFET (for a circuit example, see FIG. 15 of the second embodiment).
- the operating power supply voltage of the first, second, third, and fourth GaAs MESFETs PA101, PAl02, PA201, and PA301 has a drain voltage of about 3.5 V and a gate voltage of about 2.0 V -3.0 yen.
- a drain voltage of about 3.5 V For the first ⁇ 3 5! ⁇ £ 5? £ cho PA 101 and PAl 02, gain is emphasized, and for the second and third GaAs MESFET PA201 and PA301, the linearity of input / output characteristics and digital distortion characteristics are emphasized. It is operated in class AB (idle current of about 10% of I dss).
- the Idss of sMESFET PA101, 102, 201 and 301 are about 160 mA, about 550 mA, about 900 mA, and about 1. 1., respectively.
- the first single-pole, double-throw switch SW1 is used with a control voltage of 0VZ-4.7V.
- the input matching circuit and the first and second power amplifiers are required by using the wide band power amplifiers as the first and second power amplifiers PA1 and PA2. This eliminates the need for a switch for switching the input matching circuit.
- four types of methods shown in FIGS. 22A to 22D of the embodiment are used. In this embodiment, a method is used in which a negative feedback circuit composed of a series circuit of a resistor and a capacitor is inserted between the input and output of the GaAs MES ET shown in FIG.
- the resistance and capacity of the negative feedback circuit of the first and second GaAs MESFETs PA101 and PA102 are integrated with the first switch-equipped power amplifier SWP A1 and sealed in a resin mold package.
- the second and third interstage matching circuits PA2 02 and PA302 determine the output impedance of the second GaAs MESFET PA 102 at the frequencies f1 and f2 and the third and fourth GaAs MESFETs. Match the input impedance of PA201 and PA301.
- the first inter-stage matching circuit PA 103 in the first switch-equipped power amplifier SWP A 1 is composed of a coupling capacity and performs high-frequency coupling of each stage (blocks a DC component).
- the first inter-stage matching circuit PA 103 may be a passive circuit composed of lumped constant elements.
- the parameters of the first and second output matching circuits PA 203 and PA 303 are determined in accordance with the matching circuit method described in the first embodiment. This satisfies the distortion characteristics required by the -NO 4 shift DQPSK modulation scheme and the spread spectrum ZQPSK modulation scheme of the present embodiment.
- each of the above matching circuits its equivalent circuit is represented by a combination of lumped element components, and the first and second interstage matching circuits PA202, PA302, the first and second output matching circuits PA203, PA303 , A microstrip line on a GaAs substrate, a spiral inductor, a MIM (Metal Insulator Metal) capacitor, a comb-shaped capacitor, and a thin film resistor (such as NiCr).
- a MIM Metal Insulator Metal
- FIG. 26 is a configuration diagram of a power amplifier with a switch according to the fourth embodiment.
- Vdd l / Vgg l is the drain pressure Z gate voltage supplied to the first and second GaAs MESFETs PA 101 and PA 102
- Vdd SZVgg Z, Vdd 3 Vgg 3 is the third and fourth GaAs MESFET PA 201
- PA1 is a drain voltage / gate voltage supplied to the PA 301
- VC1 is a control voltage supplied to the first single-pole, double-throw switch SW1.
- the power supply control of the drain voltage Z gate voltage supply units 102, 103, 104 (power supply control circuit) and the control voltage supply unit 105 (power supply circuit) of the first single-pole, two-throw switch SW1 is configured to be linked. For example, when the output selection is Pout 1, SW1 controls the power supply circuit to select Pout1, and unused PA301 supplies drain voltage and gate voltage so that it does not operate for low power consumption.
- the unit 104 is controlled.
- the drain voltage gate voltage supply section is configured by using a chip inductor and a bypass capacitor as a choke, or a microstrip line and a bypass capacitor on a printed board for mounting a power amplifier with a switch.
- a power supply with automatic gain control (AGC, ALC) function in Athens It incorporates an amplifier and controls the output power monitor by feedback. The output power is monitored by a capacitor coupling or a directional coupler. (Refer to Fig. 5 and Fig. 6 in Example 1 for a configuration example.) 0
- FIG. 1 Including the switch-equipped power amplifier 101 of the present embodiment, FIG. 1
- the high frequency section 120, intermediate frequency signal processing section 121, and baseband section 122 shown in the block diagram of the information communication device are integrated on at least one printed circuit board (such as a dielectric substrate). By mounting it on a portable device, it is possible to obtain a high-value-added communication device that can be reduced in size and cost as compared with the conventional example, and that can share a different frequency band, transmission output power, and modulation method.
- Modes 1 and 2 are connected to a power amplifier with a switch. * A switch for switching between reception and a connection is used, and a switch for diversity transmission / reception is connected. Transmission and reception for mode 2 can be performed.
- the antenna section is shared between mode 1 and mode 2, and the switch for switching the output of mode 1 and mode 2 of the power amplifier with switch and the switch for switching between transmission and reception are connected. In this way, transmission and reception in mode 1 and mode 2 can be performed.
- FIGS. 27 (a) to (d) are views showing a part to be converted to MMIC in the fourth embodiment. (272) to (276) in the following description correspond to the reference numerals given by the dotted lines in FIG.
- GaAs MESFETs, switches, matching circuits, and other peripheral circuits are composed of hybrid ICs.
- the GaAs ME SFE with Wg of lmm and 4 mm is sealed in a resin mold package, and the GaAs ⁇ ESFET with Wg of 8 mm is mounted in a ceramic package (mounted on a ceramic carrier, Resin sealing).
- the matching circuit uses chip components such as chip inductors, chip capacitors, and chip resistors.
- At least one of the first integrated power amplifier MMPA1 or the second integrated power amplifier ⁇ 2 is connected to the first switched power amplifier SWPA1.
- the first single-pole two-throw switch SW1 and at least one of the second power amplifier PA2 and the third power amplifier PA3 are integrated on a GaAs substrate.
- At least one of the first power amplifier PA1 and the second power amplifier PA2 or the third power amplifier PA3 is integrated on a GaAs substrate.
- the chip formed into the MM IC can be sealed in a resin mold package or mounted as a bare chip, and the matching circuit formed into the MM IC is mounted on the GaAs substrate.
- the first and second power amplifiers PA 1, PA 2, and PA 3 MM ICs for example, the first and second power amplifiers PA 1, PA 1, As in the case of using an MM IC for components other than the output matching circuits in the PA2, this also includes selecting the components (active elements, passive circuits, etc.) of each of the above power amplifiers and converting them to MM ICs.
- this also includes selecting the components (active elements, passive circuits, etc.) of each of the above power amplifiers and converting them to MM ICs.
- GaAs MIS FET used as an active element of the power amplifier described above, enhancement-type GaAs MESFET and transistors formed on other semiconductor substrates (MOSFE, HBT Active devices such as HEMT) may be used.
- the operation requirement of the mobile device assumes a voltage of 3.0 to 3.4 V, which is equivalent to three Ni Cd batteries or one Li ion battery.
- the operating power supply voltage of aAsMESFET is 3.5 V.
- the operating voltage of other logic ICs or other power supply voltages depending on the type of information and communication equipment can be set. This embodiment can be realized with an operating voltage other than 3.5 V by using an optimal active device that operates at a specified voltage.
- the negative voltage generated by the DC-DC converter is used as the gate voltage of the GaAs MESFET.
- the negative power supply is eliminated. Embodiments can be implemented.
- the second power amplifier PA2 and the third power amplifier PA3 of this embodiment are single-stage amplifiers, multi-stage amplifiers such as the first power amplifier PA1 may be used.
- the matching circuit constituting the power amplifier is taken up as the passive circuit.
- the present invention is not limited to the passive element that plays the role of force matching.
- passive circuits such as harmonic trap circuits and Athens.
- choke inductors, bypass capacitors, and split resistors for bias application of the power supply line may be included in the power amplifier that has been converted into MMICs. Later, a bandpass filter having a predetermined pass bandwidth may be inserted, and a harmonic trap circuit may be inserted into the output matching circuit.
- a single-pole, two-throw switch is used to transmit high-frequency signals corresponding to the two types, but the switch for switching is a single-pole, multiple-throw terminal having three or more throws.
- a desired power amplifier and information communication device can be configured even with a throw switch or a multi-pole two-throw switch having a multi-pole terminal of two or more poles.
- Mode 2 :: 4 shift DQP SK modulation method
- high frequency signals having almost the same P0ut1 and Pout2 but different ff2, for example, the following high frequency signals can be transmitted.
- FIG. 28 to FIG. 30 are diagrams for explaining a fifth embodiment of the switcher with a switch according to the present invention.
- This power amplifier with a switch uses a wide-privileged area power amplifier as the driving power amplifier (driver amplifier), pre-driving power amplifier (pre-driver amplifier), and first-stage pre-driving power amplifier of the final output stage power amplifier. It has the function of transmitting high-frequency signals with two types of frequency and two types of nod output power when the switches are switched synchronously in time.
- the broadband power amplifier including the multi-frequency matched power amplifier
- the broadband power amplifier including the multi-frequency matched power amplifier
- This embodiment transmits a high-frequency signal having a frequency output power Pout as shown in the table below.
- FIG. 28 is a configuration diagram of a power amplifier with a switch according to a fifth embodiment of the present invention.
- a first single-pole two-throw switch SW1 On the output side of the first power amplifier PA1, a first single-pole two-throw switch SW1, a first output matching circuit PC1 for mode 1, and a second power amplifier PA2 for mode 2 are provided. Is connected.
- the first power amplifier PA 1 is composed of a first GaAs MESFE PA 101, a first inter-stage matching circuit PA 104, a second GaAs MESFET PA 102, and a second inter-stage matching circuit.
- a PA 105 and a third GaAs MESFET PA 103; a second power amplifier PA 2 includes a fourth GaAs MESF ET PA 201, a third inter-stage matching circuit PA 202, and a second output matching circuit PA 203 have.
- the first, second, and third GaAs MESFETs PA101, PA102, and PA103 of the first power amplifier PA1 and the PA201 of the second power amplifier PA2 are of a depletion type and have a gate width (Wg ) Are 6mm, 2.0mm, 6.0mm. 30mm, respectively.
- the matching circuit PA105 and the first single-pole two-throw switch SW1 are integrated on the GaAs substrate (the first switch-equipped power amplifier SWPA1) to form the second power amplifier PA2.
- the fourth P A201 in which ⁇ is 30111111 is mounted on a ceramic package (mounted on a ceramic carrier and sealed with a resin).
- the first single-pole two-throw switch SW1 uses an integrated circuit using a GaAs MESFET (for a circuit example, see FIG. 15 of the second embodiment).
- the first, second, third, and fourth GaAs MES FETs PA 101 PA 102, PA 103, and # 201 have an operating power supply voltage of about 3.5 V for the drain voltage and about 2.0 V to about 2.0 V for the gate voltage of the negative voltage. One 3.0 V).
- the first and second GaAs MESFETs PA101 and PA102 emphasize gain.
- the third and fourth GaAs MESFETs PA103 and PA201 are operated in class AB (idle current of about 10% of Idss) with emphasis on the linearity of input / output characteristics and digital distortion characteristics. Ids of GaAs MESFET PA101, PA102.
- PA103 and PA201 are about 16 OmA, 55 OmA, 1.3 A and 7. OA, respectively.
- the first single-pole, double-throw switch SW1 is used with a control voltage of 0V to 4.7V.
- the input matching circuit the first and second embodiments are realized by using the wide-range power amplifier as the first, second, and third power amplifiers PA1, PA2, and PA3. This eliminates the need for a switch for switching the input matching circuit, which was required in the above.
- First and second GaAs MESFET PA 101 The resistance and capacity of the negative feedback circuit of PA 102 are integrated with the first switch-equipped power amplifier SWP A1 and sealed in a resin mold package.
- the resistor and capacity of the negative feedback circuit 101 of the third P & A PA 103 are external circuits using chip components.
- the third inter-stage matching circuit PA 202 is configured such that, at the frequency f2, the output impedance of the third GaAs MESFE.PA 103 and the input impedance of the fourth GaAs MESFET PA 201 Decide to match.
- first and second interstage matching circuits PA104 and PA105 in the first switch-type power amplifier SWPA1 are configured with coupling capacities, and perform high-frequency coupling of each stage.
- the first and second interstage matching circuits PA104 and PA105 may be passive circuits composed of lumped elements.
- the parameters of the first and second output matching circuits PC 1 and PA 203 are determined in accordance with the matching circuit method described in the first embodiment. This satisfies the distortion characteristics required in the ⁇ 4 shift DQPS S modulation method of the present embodiment.
- the equivalent circuit is represented by a combination of lumped element components.
- the first and second interstage matching circuits PA104 and PA105 are microstrip lines and spiral inductors on a GaAs substrate. Evening, MIM (Melal Insulator Metal) capacity evening, comb-shaped capacity evening, thin-film resistance (NiCr, etc.) and so on.
- MIM Melal Insulator Metal
- the first and second output matching circuits PC1 and PA203, and the third interstage matching circuit PA202 are configured using chip inductors, chip capacitors, and chip resistors of chip components.
- FIG. 29 is a configuration diagram of a power amplifier with a switch according to the fifth embodiment.
- Drain voltage non-gate voltage supply units 104 and 105 to the GaAsMESFET PA 103 and PA 201 and a control voltage supply unit 106 of the first single-pole two-throw switch SW1 are mounted on a printed circuit board 107.
- the power supply control of the drain voltage / gate voltage supply units 103, 104 and 105 (power supply control circuit) and the control voltage supply unit 106 (power supply circuit) of the first single-pole two-throw switch SW1 are configured to be linked. For example, if the output selection is Pout 1, S
- Wl controls the power supply circuit to select Pout1, and controls drain voltage Z gate voltage supply unit 105 so that unused PA201 does not operate for low power consumption.
- the drain voltage / gate voltage supply unit is configured using a chip inductor and a bypass capacitor as a choke, or a microstrip line and a bypass capacitor on a print substrate for mounting a power amplifier with a switch.
- a gain control function to maintain and stabilize a constant output power is indispensable as a function of the transmission power amplifier, and a power amplifier with automatic gain control (AGC, ALC) function in Athens It incorporates an amplifier and controls the output power monitor by feedback.
- the output power is monitored by a capacitor coupling or a directional coupler.
- the parts 122 are integrated on at least one or more printed circuit boards (such as dielectric substrates), and by mounting these on the body of information and communication equipment, miniaturization and cost reduction can be achieved compared to conventional examples. High-value-added communication equipment that can use different frequency bands, transmission output power, and modulation schemes can be obtained.
- a power amplifier with a switch is connected to a switch for switching between transmission and reception for modes 1 and 2, and a switch is connected to a switch for performing diversity transmission and reception. Transmission and reception for mode 2 can be performed.
- the antenna section is shared between the mode 1 and the mode 2, the switch for switching the output of the mode 1 and the mode 2 of the power amplifier with the switch, and the switch for switching the transmission and the reception. By connecting to, transmission and reception in mode 1 and mode 2 can be performed.
- FIG. 30 is a diagram showing a part of the fifth embodiment that is formed into an MM IC. Reference numerals 302 to 305 correspond to the reference numerals given by the dotted lines in FIG.
- GaAs MESFETs, switches, matching circuits, and other peripheral circuits are composed of hybrid ICs.
- GaAs MESFETs with Wg of 0.6 mm, 2 mm, and 6 mm are sealed in a resin mold package, and GaAsM ESFETs with a Wg of 30 mm are mounted in a ceramic package (mounted on a ceramic carrier and sealed with resin. ing).
- the matching circuit and negative feedback circuit use chip inductors, chip capacitors, and chip resistors.
- the first output matching circuit PC1 or the second output matching circuit PA203 is incorporated in the first switch-equipped power amplifier SWP A1, and is resin-molded.
- the third GaAs MESFET PA 103 and the first single-pole two-throw switch SW1 are integrated on a GaAs substrate (second power amplifier with switch SWP A2), and the first output matching
- the circuit PC 1 or the second output matching circuit PA 202 is incorporated and resin-molded.
- the negative feedback circuit 101 of the third 03 85 5 ⁇ 1 £ 5-5 PA 103 may be either integrated or external.
- At least one of the elements constituting the first power amplifier PA1 and the first output matching circuit PC1 or the second output matching circuit PA203 is integrated on the GaAs substrate, Perform resin molding.
- the chip made into MM IC can be sealed in a resin mold package or mounted with bare chip.
- the integrated matching circuit consists of a combination of microstrip lines, spiral inductors, MIM (Metal Insulator Metal) capacitors, comb-shaped capacitors, and thin film resistors (NiCr, etc.) on a GaAs substrate. Components that are not converted to MM ICs are individually mounted on a printed circuit board.
- each of the above- includes selecting the components of the power amplifier (active elements, passive circuits, etc.) and converting them to MMICs.
- an active element such as an enhancement type GaAsMESFET or a transistor (MOSFE, HBT, HEMT, etc.) formed on another semiconductor substrate may be used. No.
- the operation requirement of the portable device is assumed to be a voltage of 3.0 to 3.4 V corresponding to three Ni Cd batteries or one Li ion battery.
- the operating power supply voltage of the MESFET is 3.5 V, the operating voltage of other logic devices, or other power supply voltages can be set depending on the type of information and communication equipment.
- This embodiment can be realized with an operating voltage other than 3.5 V by using an optimal active device that operates at a specified voltage.
- the gate voltage of the GaAs MESFET is a negative voltage generated by a DC-DC converter, but if an active element that operates with a single positive power supply is selected, the negative power supply is removed. This embodiment can be realized.
- the second power amplifier P A2 of this embodiment is a single-stage amplifier, a multi-stage amplifier such as the first power amplifier PA 1 may be used.
- a matching circuit constituting a power amplifier is taken up as a passive circuit.
- ⁇ 60 Replacement ⁇
- passive circuits such as choke inductors in power supply lines, bypass capacitors, split resistors for bias application, filters, harmonic trap circuits, and Atsuneta included.
- a choke inductor on the power supply line, a bypass capacitor, and a split resistor for bias application may be included in the MMIC power amplifier.
- an output matching circuit After that, a band-pass filter having a predetermined pass bandwidth may be inserted, or a harmonic trap circuit may be inserted into the output matching circuit.
- a single-pole, two-throw switch is used to transmit high-frequency signals corresponding to the two types, but the switch for switching is a single-pole, multiple-throw terminal having three or more throws.
- a desired power amplifier and information communication device can be configured even with a throw switch or a multi-pole two-throw switch having two or more multi-pole terminals.
- Mode * 1 ⁇ 4 shift DQP SK modulation method
- Mode * 2 ⁇ -no 4 shift DQP SK modulation method f Pout communication method
- Mode * 1 ⁇ 4 shift DQP SK modulation method
- the analog FM modulation method of mode 2 allows the use of a non-linear, saturated power amplifier as the power amplifier, and the second output matching circuit PA20
- FIG. 31 to FIG. 34 are diagrams for explaining a sixth embodiment of the power amplifier with a switch of the present invention.
- This power amplifier with a switch uses a wide-area power amplifier as the driving power amplifier (driver amplifier) of the final output stage power amplifier, the pre-fi driving power amplifier (pre-driver amplifier), and the first stage pre-driving power amplifier. It has a function of transmitting high-frequency signals of two types of frequencies and two types of output power by switching in synchronization with time.
- the broadband power amplifier including the multi-frequency matched power amplifier
- the broadband power amplifier including the multi-frequency matched power amplifier
- the sixth embodiment transmits a high-frequency signal having a frequency f and an output power Pout as shown in the table below.
- FIG. 31 is a configuration diagram of a power amplifier with a switch according to a sixth embodiment of the present invention.
- a first single-pole two-throw switch SW1 On the output side of the first power amplifier PA1, a first single-pole two-throw switch SW1, a first passive circuit PC1 for mode 1 and a second passive circuit PC2 for mode 2 are provided. It is connected.
- the first power amplifier PA 1 is connected to the first GaAs MESFET P A 10
- the passive circuit PC1 has a first output matching circuit PC101 and a first filter PC102
- the second passive circuit PC2 has a second output matching circuit PC201 and And a second Phil PC 202.
- the first, second, and third GaAs MESFETs PA101, PA102, and PA103 that constitute the first power amplifier PA1 are of the depletion type, and have gate widths (Wg) of lmm, 6 mm, and 30 mm, respectively. It is.
- the first GaAs MESFET PA101, the first interstage matching circuit PA104, and the first single-pole two-throw switch SW1 are integrated on a GaAs substrate.
- the first power amplifier with a switch SWPA1 and seal it in a resin mold package.
- the second GaAs MESF ET PA102 with Wg of 6 mm is mounted on a resin mold package
- the third GaAsAsMESFET PA103 with Wg of 30 mm is mounted on a ceramic package. (Mounted on a ceramic carrier and resin Sealed).
- the first single-pole, double-throw switch SW 1 uses an integrated circuit using GaAs MESFETs (see FIG. 15 in Example 2 for a circuit example).
- the first, second, and third GaAs MESFET PA 101, PA 102, and PA 103 operate at a power supply voltage of 3.5 V for the drain voltage and a gate voltage of 2.0 for the negative voltage. V to one 3.0V.
- the first GaAs MES FET PA101 gain is emphasized.
- the second and third GaAsMESFET PA102.PA103 operate in class AB (idle current of about 10% of Ids) with emphasis on linearity of input / output characteristics and digital distortion characteristics.
- the I d ss of GaAs MESFET PA 101, PA 102 and PA 103 are about 250 mA, about 1.3 A, and about 7.OA, respectively.
- the first single-pole, two-throw switch SW1 is used with a control voltage of OV / —4.7 V.
- the input matching circuit and the first and second power amplifiers are required by using a wideband power amplifier as the first, second, and third power amplifiers PA1, PA2, and PA3. Switch to switch the input matching circuit
- FIGS. 22A to 22D of the third embodiment In general, in order to realize such a wide band operation of the power amplifier, four types of methods shown in FIGS. 22A to 22D of the third embodiment are used.
- the resistance and capacity of the negative feedback circuit of the first GaAs MESFET PA101 are integrated with the first switch-equipped power amplifier SWP A1 and sealed in a resin mold package.
- the resistance and capacity of the first negative feedback circuit 101 of the PA 102 are external circuits using chip components.
- the third GaAs MESFET PA 103 whether the second negative feedback circuit 102 is integrated, the negative 1 stagnation circuit 102 is an external circuit, or the wideband matching (frequency In the frequency range including f1 and ⁇ 2, or f1 and f2, match the output impedance of the second power amplifier PA102 with the input impedance of the third capacitor PA103)
- an impedance conversion circuit that can perform the operation is used.
- the third inter-stage matching circuit PA202 has the third function of the frequency f2, which is the third of the three! ⁇ Match the output impedance of the PA103 and the input impedance of the fourth GaAs MESFET PA201.
- the first inter-stage matching circuit PA 104 is composed of a coupling capacitor, and performs high-frequency coupling of each stage (blocks a DC component).
- the first inter-stage matching circuit PA 104 and the second inter-stage matching circuit PA 105 may be passive circuits composed of lumped elements.
- the parameters of the first and second output matching circuits PC101 and PC201 are determined according to the matching circuit method described in the first embodiment. This satisfies the distortion characteristics required in the :: Q4 shift DQPSK modulation method of the present embodiment.
- each of the above matching circuits its equivalent circuit is represented by a combination of lumped element components, and the first and second interstage matching circuits PA104 and PA105, and the first and second output matching circuits PC101 and PC201.
- the microstrip line, spiral inductor, MIM metal
- the first and second output matching circuits PC101 and PC201 and the second interstage matching circuit PA105 are configured using chip inductors, chip capacitors, and chip resistors of chip components.
- the first and second filters PC 102 and PC 202 pass a band pass filter having a predetermined pass band width for the frequencies f 1 and ⁇ 2, or pass the band pass filters ⁇ ⁇ 1 and f 2 ⁇ ⁇ It consists of a combination of low pass and high pass fills in the area.
- the filter used is a dielectric filter of a chip component or a surface acoustic wave filter (SAW filter).
- FIG. 32 is a configuration diagram of a power amplifier with a switch of the sixth embodiment.
- a drain voltage gate voltage supply unit 105 and a control voltage supply unit 106 of the first single-pole, double-throw switch SW1 are mounted on a printed circuit board 107.
- VddlZVggl is the drain voltage / gate voltage supplied to the first GaAs MESFET PA101
- Vdcl2ZVgg2 is the drain voltage / gate supplied to the second and third GaAs MESFET PA102, PA103.
- VC 1 is a control voltage supplied to the first single-pole two-throw switch SW 1.
- the power supply control of the drain voltage / gate voltage supply units 104 and 105 (power supply control circuit) and the power supply control of the control voltage supply unit 106 (power supply circuit) of the first single-pole two-throw switch SW1 are configured to be linked. For example, when the output selection is Pout1, SW1 controls the power supply circuit to select Pout1.
- the drain voltage / gate voltage supply unit is configured using a chip inductor and a bypass capacitor as a choke, or a microstrip line and a bypass capacitor on a printed board for mounting a power amplifier with a switch. Including the power amplifier with switch 103 of the present embodiment described above,
- the high frequency section 120, intermediate frequency signal processing section 121, and baseband section 122 shown in the block diagram of the information communication device are integrated on at least one printed circuit board (such as a dielectric substrate). By mounting it on a portable device, it is possible to obtain a high-value-added communication device that can be reduced in size and cost as compared with the conventional example, and that can share a different frequency band, transmission output power, and modulation method.
- FIGS. 8 to 10 of the first embodiment can be considered.
- a power amplifier with a switch is connected to a switch for switching between transmission and reception for mode 1 and mode 2, and a switch is connected to a switch for diversity transmission and reception. Transmission and reception for mode 2 can be performed.
- the antenna section is shared between mode 1 and mode 2, and the switch for switching the output of mode 1 and mode 2 of the power amplifier with switch and the switch for switching between transmission and reception are connected. In this way, transmission and reception in mode 1 and mode 2 can be performed.
- FIG. 33 is a diagram showing a part to be converted to MMIC of the sixth embodiment, and corresponds to the following description (2).
- the dotted line in FIG. 33 indicates the part to be converted to MMIC.
- GaAs MESFETs, switches, matching circuits, and other peripheral circuits are composed of hybrid ICs.
- GaAs ME SFET with a Wg of lmm and 6 mm is sealed in a resin mold package, and a GaAs MESFET with a Wg force of 30 mm is mounted in a ceramic package. (Mounted on a ceramic carrier and sealed with a resin Has been stopped).
- the matching circuit and negative feedback circuit use the chip component chip inductor, chip capacitor, and chip resistor, and the filter uses the chip component dielectric filter or surface acoustic wave filter (SAW filter).
- SAW filter surface acoustic wave filter
- the first output matching circuit PC101 or the second output matching circuit PC201 is incorporated into the first switch-equipped power amplifier SWPA1, and is resin-molded.
- the third GaAs MESFET PA103 and the first single-pole two-throw switch SW1 are integrated on a GaAs substrate (second power amplifier with switch SWPA2), and the first output matching circuit PC201, Alternatively, the second output matching circuit PC202 is incorporated and molded with resin. However, the negative I retention circuit 101 of the third GaAs MESFET PA 103 may be integrated or external.
- the elements constituting the first power amplifier PA1 and at least one of the first output matching circuit PC101 or the second output matching circuit PC201 are integrated on a GaAs substrate, and resin-molded. .
- the two GaAsMESFET PA101, 102 and the first and second interstage matching circuits PA104, PA105 are integrated on a GaAs substrate (the first—body-type power amplifier MMPA1). I do. Mounting is done by putting it in a package or connecting it to a printed circuit board with a bare chip.
- the chip formed into the MM IC is sealed in a resin mold package or mounted in a bare chip, and the matching circuit formed into the MMIC is formed on a GaAs substrate.
- the second power amplifier PA 2 uses MMIC for components other than the output matching circuit. In this case, it is also necessary to select the constituent elements (active elements, passive circuits, etc.) of each of the power amplifiers described above to form an MMIC.
- GaAs AsMES FET used as an active element of the power amplifier above, it is formed on an enhancement type GaAs MES FET or other semiconductor substrate.
- An active device such as a transistor (MFETSFET, HBT, HEMT, etc.) may be used.
- the mobile device operation requirements are based on a voltage of 3.0 to 3.4 V, which is equivalent to three Ni Cd batteries or one Li ion battery.
- the operating power supply voltage of aAsMESFET is 3.5 V.
- the operating voltage of other logic ICs or other power supply voltages depending on the type of information and communication equipment can be set. This embodiment can be realized with an operating voltage other than 3.5 V by using an optimal active device that operates at a specified voltage.
- the negative voltage generated by the DC-DC converter is used as the gate voltage of the GaAsMES FET.
- the negative power supply is removed. This embodiment can be realized.
- the matching circuit constituting the power amplifier has been described as a passive circuit.
- the present invention is not limited to the passive element that plays a role of matching, but includes a choke inductor, a bypass capacitor, a bias application split resistor, and a filter for a power supply line. It also includes passive circuits such as the evening, harmonic trap circuits, and Athens.
- a choke inductor, a bypass capacitor, and a bias application split resistor for the power supply line may be included in the power amplifier that is made into an MMIC.
- a bandpass filter having a predetermined pass bandwidth may be inserted, and a harmonic trap circuit may be inserted in the output matching circuit.
- a single-pole, two-throw switch is used to transmit high-frequency signals corresponding to the two types, but the switch for switching is a single-pole, multiple-throw terminal having three or more throws.
- a desired power amplifier and information communication device can be configured even with a throw switch or a multi-pole two-throw switch having a multi-pole terminal of two or more poles.
- Mode 2 ⁇ / 4 shift DQP SK modulation method
- a non-linear or saturated power amplifier can be used as the power amplifier, and the specified output power 3 for the output matching circuit. Matching is performed so that high power added efficiency and a high harmonic component suppression ratio can be obtained at I d Bm.
- the second output matching circuit PC201 is matched so as to obtain high power added efficiency while suppressing adjacent channel leakage power at a specified output power of 22 dBm.
- the output power has the same specifications.However, by adding the gain control function as shown in FIGS. 5 and 6 of Embodiment 1, This is effective even when the output power is different.
- Mode 1 ⁇ / 4 shift DQPSK modulation method
- FIG. 34 shows the first passive circuit PC 1 connected to the two-throw terminal of the first single-pole, two-throw switch SW1 in the power amplifier of Fig. 31.
- FIG. 6 is a configuration diagram in which a second single-pole, double-throw switch SW2 is connected to each output terminal of a second passive circuit PC2. By switching the second single-pole two-throw switch SW2 in synchronization with the first single-pole two-throw switch SW1, two types of high-frequency signals can be transmitted. In other words, as a method of connecting to the antenna, in the configuration of FIG.
- the output of the first passive circuit PC 1 and the second passive circuit PC 2 connected to the two throw terminals of the first single pole two throw switch is used.
- the antenna reaches each antenna via a duplexer or a switch
- a component such as a filter may enter the path leading to the antenna.
- FIG. 39 is a block diagram of a power amplifier and a communication device according to the present invention.
- the high-frequency signal input from the input terminal In is selectively input to one of the input matching circuits PC1 and PC2 via the switch SW1.
- the outputs of PC1 and PC2 are selected by switch SW2 and input to amplifier PA1.
- the output of the amplifier PA1 is selectively input to one of the output matching circuits PC3 and PC4 via the switch SW3.
- the outputs of PC3 and PC4 are selected by switch SW4 and applied to terminal TX of switch SW5.
- the switch SW5 connects the terminal TX to the antenna ANT at the time of transmission, and connects the terminal RX to the antenna ANT at the time of reception. At the time of reception, the input signal from the antenna ANT is given to the front-end circuit FE via the switch SW5.
- a power amplifier with a switch can be realized.
- INDUSTRIAL APPLICABILITY As described above, according to the present invention, a single-pole / multi-throw switch switches between two amplifiers that amplify signals in different frequency bands. As a result, a power amplifier and a communication device that can amplify high-frequency signals in different frequency bands can be provided.
- a single-pole / multi-throw switch switches between two amplifiers that amplify signals having different output powers.
- a power amplifier and a communication device that can amplify high-frequency signals having different output powers.
- a passive circuit and an amplifier are switched instead of the above two amplifiers.
- a power amplifier and a communication device that can amplify high-frequency signals having different frequencies and / or output powers by combining the above configurations can be provided.
- the present invention by providing a switch for switching between transmission and reception at the output terminal of the power amplifier, it is possible to provide a communication device capable of receiving high-frequency signals of different frequencies.
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP96931987A EP0795956B1 (en) | 1995-09-29 | 1996-09-25 | Power amplifier and communication device |
DE69630512T DE69630512T2 (de) | 1995-09-29 | 1996-09-25 | Leistungsverstärker und kommunikationsvorrichtung |
US08/849,355 US6111459A (en) | 1995-09-29 | 1996-09-25 | Multi mode power amplifier and communication unit |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP25320495 | 1995-09-29 | ||
JP7/253204 | 1995-09-29 | ||
JP454896 | 1996-01-16 | ||
JP8/4548 | 1996-01-16 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US09/593,123 Division US6313699B1 (en) | 1995-09-29 | 2000-06-13 | Power amplifier and communication unit |
US09/607,424 Division US6313700B1 (en) | 1995-09-29 | 2000-06-29 | Power amplifier and communication unit |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1997013320A1 true WO1997013320A1 (fr) | 1997-04-10 |
Family
ID=26338355
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP1996/002770 WO1997013320A1 (fr) | 1995-09-29 | 1996-09-25 | Amplificateur de puissance et dispositif de telecommunications |
Country Status (6)
Country | Link |
---|---|
US (4) | US6111459A (ja) |
EP (1) | EP0795956B1 (ja) |
JP (2) | JP2008295088A (ja) |
CN (1) | CN1081850C (ja) |
DE (1) | DE69630512T2 (ja) |
WO (1) | WO1997013320A1 (ja) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001068942A (ja) * | 1999-07-22 | 2001-03-16 | Motorola Inc | メモリを利用する増幅負荷調整システム |
US9602061B2 (en) | 2014-03-10 | 2017-03-21 | Fujitsu Limited | Distributed amplifier |
Families Citing this family (91)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE69630512T2 (de) * | 1995-09-29 | 2004-05-06 | Matsushita Electric Industrial Co., Ltd., Kadoma | Leistungsverstärker und kommunikationsvorrichtung |
US5774017A (en) * | 1996-06-03 | 1998-06-30 | Anadigics, Inc. | Multiple-band amplifier |
US6181208B1 (en) * | 1998-03-26 | 2001-01-30 | Maxim Intergrated Products, Inc. | Switchable path power amplifier with schotky diode combining network |
JP3874145B2 (ja) * | 1998-06-10 | 2007-01-31 | ソニー株式会社 | 変調回路、送信装置及び送信回路 |
US6061551A (en) | 1998-10-21 | 2000-05-09 | Parkervision, Inc. | Method and system for down-converting electromagnetic signals |
US7515896B1 (en) | 1998-10-21 | 2009-04-07 | Parkervision, Inc. | Method and system for down-converting an electromagnetic signal, and transforms for same, and aperture relationships |
US6188277B1 (en) * | 1998-08-19 | 2001-02-13 | Harris Corporation | Power amplifier having monitoring and circuit protection |
US7236754B2 (en) | 1999-08-23 | 2007-06-26 | Parkervision, Inc. | Method and system for frequency up-conversion |
US7039372B1 (en) | 1998-10-21 | 2006-05-02 | Parkervision, Inc. | Method and system for frequency up-conversion with modulation embodiments |
US6370371B1 (en) | 1998-10-21 | 2002-04-09 | Parkervision, Inc. | Applications of universal frequency translation |
US6879817B1 (en) | 1999-04-16 | 2005-04-12 | Parkervision, Inc. | DC offset, re-radiation, and I/Q solutions using universal frequency translation technology |
US6853690B1 (en) | 1999-04-16 | 2005-02-08 | Parkervision, Inc. | Method, system and apparatus for balanced frequency up-conversion of a baseband signal and 4-phase receiver and transceiver embodiments |
US6724829B1 (en) * | 1999-03-18 | 2004-04-20 | Conexant Systems, Inc. | Automatic power control in a data transmission system |
US7693230B2 (en) | 1999-04-16 | 2010-04-06 | Parkervision, Inc. | Apparatus and method of differential IQ frequency up-conversion |
US7110444B1 (en) | 1999-08-04 | 2006-09-19 | Parkervision, Inc. | Wireless local area network (WLAN) using universal frequency translation technology including multi-phase embodiments and circuit implementations |
US7065162B1 (en) | 1999-04-16 | 2006-06-20 | Parkervision, Inc. | Method and system for down-converting an electromagnetic signal, and transforms for same |
US7265618B1 (en) | 2000-05-04 | 2007-09-04 | Matsushita Electric Industrial Co., Ltd. | RF power amplifier having high power-added efficiency |
US8295406B1 (en) | 1999-08-04 | 2012-10-23 | Parkervision, Inc. | Universal platform module for a plurality of communication protocols |
US7010286B2 (en) | 2000-04-14 | 2006-03-07 | Parkervision, Inc. | Apparatus, system, and method for down-converting and up-converting electromagnetic signals |
US6816016B2 (en) * | 2000-08-10 | 2004-11-09 | Tropian, Inc. | High-efficiency modulating RF amplifier |
JP2002111415A (ja) * | 2000-09-29 | 2002-04-12 | Hitachi Ltd | 高周波電力増幅装置及び無線通信機 |
US6489862B1 (en) * | 2000-10-03 | 2002-12-03 | Agilent Technologies, Inc. | Method for reducing noise generated in a power amplifier |
US7454453B2 (en) | 2000-11-14 | 2008-11-18 | Parkervision, Inc. | Methods, systems, and computer program products for parallel correlation and applications thereof |
ATE316294T1 (de) * | 2001-02-27 | 2006-02-15 | Mehrband-transformationsstufe für eine mehrband- hf-umschaltvorrichtung | |
GB0110854D0 (en) | 2001-05-03 | 2002-03-27 | Bae Sys Defence Sys Ltd | Amplifier |
SE519391C2 (sv) * | 2001-06-08 | 2003-02-25 | Allgon Mobile Comm Ab | Bärbar radiokommunikationsapparat och anordning för en sådan apparat |
US6680652B2 (en) | 2001-08-06 | 2004-01-20 | Rf Micro Devices, Inc. | Load switching for transmissions with different peak-to-average power ratios |
US7072427B2 (en) | 2001-11-09 | 2006-07-04 | Parkervision, Inc. | Method and apparatus for reducing DC offsets in a communication system |
JP2003347870A (ja) * | 2002-05-22 | 2003-12-05 | Mitsubishi Electric Corp | 電力増幅器 |
US7460584B2 (en) | 2002-07-18 | 2008-12-02 | Parkervision, Inc. | Networking methods and systems |
US7379883B2 (en) | 2002-07-18 | 2008-05-27 | Parkervision, Inc. | Networking methods and systems |
US20040232982A1 (en) * | 2002-07-19 | 2004-11-25 | Ikuroh Ichitsubo | RF front-end module for wireless communication devices |
JP2004296719A (ja) * | 2003-03-26 | 2004-10-21 | Renesas Technology Corp | 半導体装置 |
US6998932B2 (en) * | 2003-03-28 | 2006-02-14 | Matsushita Electric Industrial Co., Ltd. | High-frequency switch |
US6961553B2 (en) * | 2003-04-11 | 2005-11-01 | Motorola, Inc. | Bidirectional distributed amplifier |
JP2004319550A (ja) * | 2003-04-11 | 2004-11-11 | Hitachi Ltd | 半導体装置 |
US7184799B1 (en) | 2003-05-14 | 2007-02-27 | Marvell International Ltd. | Method and apparatus for reducing wake up time of a powered down device |
US7149483B1 (en) | 2003-10-28 | 2006-12-12 | Magnolia Broadband Inc. | Amplifying diversity signals using power amplifiers |
US7102444B2 (en) * | 2004-01-20 | 2006-09-05 | Anadigics, Inc. | Method and apparatus for compensating and improving efficiency in a variable power amplifier |
JP4137815B2 (ja) * | 2004-02-19 | 2008-08-20 | ソニー・エリクソン・モバイルコミュニケーションズ株式会社 | 電力増幅装置及び携帯通信端末装置 |
US8000737B2 (en) * | 2004-10-15 | 2011-08-16 | Sky Cross, Inc. | Methods and apparatuses for adaptively controlling antenna parameters to enhance efficiency and maintain antenna size compactness |
US7444119B2 (en) * | 2004-11-30 | 2008-10-28 | Symbol Technologies, Inc. | Method for sharing antennas of a wireless device |
US7508261B2 (en) * | 2005-01-19 | 2009-03-24 | Micro-Mobio, Inc. | Systems of miniaturized compatible radio frequency wireless devices |
KR100735316B1 (ko) * | 2005-06-29 | 2007-07-04 | 삼성전자주식회사 | 통신 시스템에서 신호 송신 시스템 및 방법 |
KR101002893B1 (ko) * | 2005-08-06 | 2010-12-21 | 삼성전자주식회사 | 전치 왜곡기를 이용하는 다중 모드 전력 증폭 방법 및 장치 |
US7729672B2 (en) * | 2006-03-22 | 2010-06-01 | Qualcomm, Incorporated | Dynamic bias control in power amplifier |
US20070270110A1 (en) * | 2006-05-18 | 2007-11-22 | Infinet Wireless Limited | Analog front end for a wireless device |
TWI320638B (en) * | 2006-08-11 | 2010-02-11 | Benq Corp | Transceiver of radio frequency signal capable of enhancing performance of transmission and reception of a mobile communication device |
US20080106332A1 (en) * | 2006-11-03 | 2008-05-08 | Wolf Randy L | Switching Low Noise Amplifier |
US7889751B2 (en) * | 2007-03-06 | 2011-02-15 | Sudhir Aggarwal | Low power wireless communication system |
WO2009025665A1 (en) * | 2007-08-20 | 2009-02-26 | Semiconductor Components Industries, L.L.C. | Amplifier circuit and method therefor |
US8718582B2 (en) * | 2008-02-08 | 2014-05-06 | Qualcomm Incorporated | Multi-mode power amplifiers |
US7973725B2 (en) * | 2008-02-29 | 2011-07-05 | Research In Motion Limited | Mobile wireless communications device with selective load switching for antennas and related methods |
US8160275B2 (en) * | 2008-04-28 | 2012-04-17 | Samsung Electronics Co., Ltd. | Apparatus and method for an integrated, multi-mode, multi-band, and multi-stage power amplifier |
US7934190B1 (en) | 2008-09-25 | 2011-04-26 | The United States Of America As Represented By The Secretary Of The Navy | Multiple amplifier matching over lumped networks of arbitrary topology |
JP2010081383A (ja) * | 2008-09-26 | 2010-04-08 | Panasonic Corp | 高周波回路、高周波電力増幅装置、及び半導体装置 |
US8688058B2 (en) * | 2008-11-24 | 2014-04-01 | Chiewcharn Narathong | Techniques for improving transmitter performance |
US9236644B2 (en) * | 2009-02-20 | 2016-01-12 | Space Micro Inc. | Programmable microwave integrated circuit |
CN102612126B (zh) * | 2009-02-26 | 2016-03-30 | 华为技术有限公司 | 一种基站载频功放的控制方法、装置及系统 |
JP4744615B2 (ja) * | 2009-02-26 | 2011-08-10 | 株式会社日立製作所 | マイクロ波、ミリ波帯増幅回路及びそれを用いたミリ波無線機 |
US9231680B2 (en) * | 2009-03-03 | 2016-01-05 | Rfaxis, Inc. | Multi-channel radio frequency front end circuit |
US7982543B1 (en) | 2009-03-30 | 2011-07-19 | Triquint Semiconductor, Inc. | Switchable power amplifier |
US20100244981A1 (en) * | 2009-03-30 | 2010-09-30 | Oleksandr Gorbachov | Radio frequency power divider and combiner circuit |
US8467738B2 (en) * | 2009-05-04 | 2013-06-18 | Rfaxis, Inc. | Multi-mode radio frequency front end module |
US8374557B2 (en) * | 2009-07-06 | 2013-02-12 | Rfaxis, Inc. | Radio frequency front end circuit with antenna diversity for multipath mitigation |
US8207798B1 (en) | 2009-09-09 | 2012-06-26 | Triquint Semiconductor, Inc. | Matching network with switchable capacitor bank |
US20110250861A1 (en) * | 2010-04-08 | 2011-10-13 | Viasat, Inc. | Highly integrated, high frequency, high power operation mmic |
US8299857B2 (en) * | 2011-01-27 | 2012-10-30 | Integra Technologies, Inc. | RF power amplifier including broadband input matching network |
JP2012160494A (ja) * | 2011-01-31 | 2012-08-23 | Japan Radio Co Ltd | 集積回路および中継基板 |
JP2013106128A (ja) * | 2011-11-11 | 2013-05-30 | Taiyo Yuden Co Ltd | フロントエンドモジュール |
JP5967905B2 (ja) | 2011-11-21 | 2016-08-10 | サムソン エレクトロ−メカニックス カンパニーリミテッド. | 増幅回路及び無線通信装置 |
US8729962B2 (en) | 2011-12-15 | 2014-05-20 | Qualcomm Incorporated | Millimeter wave power amplifier |
JP6040442B2 (ja) * | 2012-03-16 | 2016-12-07 | 住友電工デバイス・イノベーション株式会社 | 増幅器 |
DE102012016450B4 (de) * | 2012-08-16 | 2015-10-15 | Airbus Defence and Space GmbH | Sende-/Empfangselement für ein aktives, elektronisch gesteuertes Antennensystem |
US9160377B2 (en) * | 2012-12-19 | 2015-10-13 | Qualcomm Incorporated | Multi-mode multi-band power amplifiers |
US8897730B2 (en) * | 2012-12-31 | 2014-11-25 | Triquint Semiconductor, Inc. | Radio frequency switch circuit |
CN104753476B (zh) * | 2013-12-30 | 2018-05-18 | 国民技术股份有限公司 | 多模多频功率放大器 |
WO2015156079A1 (ja) * | 2014-04-08 | 2015-10-15 | 株式会社村田製作所 | 高周波モジュール |
US9595921B2 (en) * | 2014-06-30 | 2017-03-14 | Skyworks Solutions, Inc. | Power amplifier having a common input and a plurality of outputs |
RU2599531C2 (ru) * | 2014-12-29 | 2016-10-10 | Федеральное государственное казенное военное образовательное учреждение высшего профессионального образования "Военный учебно-научный центр Военно-воздушных сил "Военно-воздушная академия имени профессора Н.Е. Жуковского и Ю.А. Гагарина" (г. Воронеж) Министерства обороны Российской Федерации | Способ генерации и частотной модуляции высокочастотных сигналов и устройство его реализации |
KR102123600B1 (ko) * | 2015-05-29 | 2020-06-15 | 삼성전기주식회사 | 프론트 엔드 회로 |
CN105277805B (zh) * | 2015-09-14 | 2018-10-19 | 上海新爱季信息技术有限公司 | 噪声系数辅助测量装置 |
US9837972B2 (en) * | 2015-12-30 | 2017-12-05 | Skyworks Solutions, Inc. | Multi-mode power amplifier module |
US10374555B2 (en) * | 2016-09-14 | 2019-08-06 | Skyworks Solutions, Inc. | Radio-frequency amplifier having active gain bypass circuit |
JP2018050159A (ja) * | 2016-09-21 | 2018-03-29 | 株式会社村田製作所 | 送受信モジュール |
US10637405B2 (en) * | 2018-08-14 | 2020-04-28 | Nxp Usa, Inc. | Wideband biasing of high power amplifiers |
KR20200031980A (ko) * | 2019-02-26 | 2020-03-25 | 주식회사 다이얼로그 세미컨덕터 코리아 | Fdd 무선 통신 방식에서의 송수신 주파수 변환 방법 및 장치 |
KR20210095365A (ko) * | 2020-01-23 | 2021-08-02 | 삼성전자주식회사 | 무선 신호를 처리하기 위한 전자 장치 및 그의 동작 방법 |
CN111342779A (zh) * | 2020-04-14 | 2020-06-26 | 湖北楚航电子科技有限公司 | 一种多通道射频功放组件 |
CN113141743B (zh) * | 2021-04-19 | 2022-07-29 | 中国科学院合肥物质科学研究院 | 一种固态微波功率合成驱动模块 |
CN117200727B (zh) * | 2023-11-06 | 2024-01-23 | 中国电子科技集团公司第二十九研究所 | 一种同轴增益均衡装置 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02105636A (ja) * | 1988-10-14 | 1990-04-18 | Nec Corp | 無線機 |
JPH0548493A (ja) * | 1991-08-13 | 1993-02-26 | Sony Corp | ブースタ装置 |
JPH06350484A (ja) * | 1993-05-10 | 1994-12-22 | Motorola Inc | デュアルモード増幅器ネットワーク |
JPH07162252A (ja) * | 1993-12-09 | 1995-06-23 | Mitsubishi Electric Corp | 振幅制限回路 |
Family Cites Families (34)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US2160857A (en) * | 1935-03-28 | 1939-06-06 | Telefunken Gmbh | High frequency system |
BE422353A (ja) * | 1936-06-30 | 1900-01-01 | ||
US3304507A (en) * | 1964-02-07 | 1967-02-14 | Beckman Instruments Inc | Sample and hold system having an overall potentiometric configuration |
JPS5413615A (en) * | 1977-07-01 | 1979-02-01 | Nat Jutaku Kenzai | Device for laying main cable in building |
JPS54136157A (en) | 1978-04-13 | 1979-10-23 | Nippon Hoso Kyokai <Nhk> | Amplifier circuit |
JPS5546630A (en) * | 1978-09-28 | 1980-04-01 | Tech Res & Dev Inst Of Japan Def Agency | Antenna change-over circuit |
JPS55138904A (en) * | 1979-04-18 | 1980-10-30 | Toshiba Corp | Antenna unit |
JPS5627504A (en) * | 1979-08-14 | 1981-03-17 | Pioneer Electronic Corp | Active antenna system |
US4494077A (en) * | 1981-12-02 | 1985-01-15 | Nippon Electric Co., Ltd. | Amplifier system switchable between two amplifying operations |
US4598252A (en) * | 1984-07-06 | 1986-07-01 | Itt Corporation | Variable gain power amplifier |
IN165870B (ja) * | 1985-06-25 | 1990-02-03 | Siemens Ag | |
JPS62220008A (ja) * | 1986-03-20 | 1987-09-28 | Nec Corp | 増幅器切換式広帯域増幅装置 |
US4794347A (en) * | 1986-05-21 | 1988-12-27 | Canon Kabushiki Kaisha | Amplifier circuit having crossover switching features |
JPS63253730A (ja) * | 1987-04-09 | 1988-10-20 | Nec Corp | 電力増幅器 |
US5021801A (en) * | 1989-09-05 | 1991-06-04 | Motorola, Inc. | Antenna switching system |
JPH03104408A (ja) * | 1989-09-19 | 1991-05-01 | Fujitsu Ltd | 電力増幅器 |
US5276914A (en) * | 1990-10-18 | 1994-01-04 | Sony Corporation | Dual-mode transceiver that switches out a large insertion loss filter during transmission |
JP2703667B2 (ja) * | 1991-01-10 | 1998-01-26 | 三菱電機株式会社 | 電力増幅装置 |
JPH0685580A (ja) * | 1991-04-11 | 1994-03-25 | Nippon Telegr & Teleph Corp <Ntt> | 電力制御装置 |
JPH0514068A (ja) * | 1991-07-03 | 1993-01-22 | Shimada Phys & Chem Ind Co Ltd | 並列増幅部切換型高周波低雑音増幅装置 |
JPH0537255A (ja) * | 1991-07-29 | 1993-02-12 | Mitsubishi Electric Corp | 広帯域増幅器 |
FR2680291B1 (fr) * | 1991-08-08 | 1998-06-19 | Europ Agence Spatiale | Amplificateur de puissance a transistors mesfet et son bloc d'alimentation, notamment pour l'amplification de signaux hyperfrequences a bord d'un stallite. |
US5276917A (en) * | 1991-10-22 | 1994-01-04 | Nokia Mobile Phones Ltd. | Transmitter switch-on in a dual-mode mobile phone |
DE4240136C1 (ja) | 1992-01-10 | 1993-06-17 | Rasmussen Gmbh, 6457 Maintal, De | |
RU2144260C1 (ru) * | 1992-03-13 | 2000-01-10 | Моторола, Инк. | Сеть, объединяющая усилители мощности сигналов высокой частоты и двухрежимное устройство связи |
JPH0653753A (ja) * | 1992-07-29 | 1994-02-25 | Nec Corp | 電力増幅装置 |
JP3382989B2 (ja) * | 1993-02-03 | 2003-03-04 | ソニー株式会社 | セルラ端末装置 |
JPH07115381A (ja) * | 1993-10-19 | 1995-05-02 | Fujitsu Ltd | 携帯電話端末の送信電力制御回路 |
JPH07115331A (ja) * | 1993-10-19 | 1995-05-02 | Mitsubishi Electric Corp | 増幅装置 |
JP2807169B2 (ja) * | 1994-04-12 | 1998-10-08 | 第一電波工業株式会社 | 同軸ケーブルの結合装置及びアンテナ装置 |
US5592122A (en) * | 1994-05-19 | 1997-01-07 | Matsushita Electric Industrial Co., Ltd. | Radio-frequency power amplifier with input impedance matching circuit based on harmonic wave |
JPH0888524A (ja) * | 1994-09-19 | 1996-04-02 | Mitsubishi Electric Corp | 高周波集積回路 |
DE69630512T2 (de) * | 1995-09-29 | 2004-05-06 | Matsushita Electric Industrial Co., Ltd., Kadoma | Leistungsverstärker und kommunikationsvorrichtung |
US5945876A (en) | 1997-09-26 | 1999-08-31 | Ericsson Inc. | Soft switching for Cartesian feedback loop control with a transmission system |
-
1996
- 1996-09-25 DE DE69630512T patent/DE69630512T2/de not_active Expired - Lifetime
- 1996-09-25 EP EP96931987A patent/EP0795956B1/en not_active Expired - Lifetime
- 1996-09-25 CN CN96191250A patent/CN1081850C/zh not_active Expired - Fee Related
- 1996-09-25 WO PCT/JP1996/002770 patent/WO1997013320A1/ja active IP Right Grant
- 1996-09-25 US US08/849,355 patent/US6111459A/en not_active Expired - Lifetime
-
2000
- 2000-06-13 US US09/593,123 patent/US6313699B1/en not_active Expired - Lifetime
- 2000-06-29 US US09/607,424 patent/US6313700B1/en not_active Expired - Lifetime
-
2001
- 2001-09-12 US US09/954,702 patent/US6489843B1/en not_active Expired - Lifetime
-
2008
- 2008-07-29 JP JP2008195527A patent/JP2008295088A/ja active Pending
-
2011
- 2011-04-18 JP JP2011092519A patent/JP2011142692A/ja active Pending
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02105636A (ja) * | 1988-10-14 | 1990-04-18 | Nec Corp | 無線機 |
JPH0548493A (ja) * | 1991-08-13 | 1993-02-26 | Sony Corp | ブースタ装置 |
JPH06350484A (ja) * | 1993-05-10 | 1994-12-22 | Motorola Inc | デュアルモード増幅器ネットワーク |
JPH07162252A (ja) * | 1993-12-09 | 1995-06-23 | Mitsubishi Electric Corp | 振幅制限回路 |
Non-Patent Citations (1)
Title |
---|
See also references of EP0795956A4 * |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2001068942A (ja) * | 1999-07-22 | 2001-03-16 | Motorola Inc | メモリを利用する増幅負荷調整システム |
US9602061B2 (en) | 2014-03-10 | 2017-03-21 | Fujitsu Limited | Distributed amplifier |
Also Published As
Publication number | Publication date |
---|---|
US6111459A (en) | 2000-08-29 |
US6489843B1 (en) | 2002-12-03 |
EP0795956A1 (en) | 1997-09-17 |
CN1081850C (zh) | 2002-03-27 |
CN1166246A (zh) | 1997-11-26 |
EP0795956A4 (en) | 1998-12-09 |
DE69630512T2 (de) | 2004-05-06 |
EP0795956B1 (en) | 2003-10-29 |
DE69630512D1 (de) | 2003-12-04 |
US6313699B1 (en) | 2001-11-06 |
JP2008295088A (ja) | 2008-12-04 |
JP2011142692A (ja) | 2011-07-21 |
US6313700B1 (en) | 2001-11-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
WO1997013320A1 (fr) | Amplificateur de puissance et dispositif de telecommunications | |
US7315205B2 (en) | Multiple power mode amplifier with bias modulation option and without bypass switches | |
US7589588B2 (en) | High-frequency power amplifier and radio communication equipment using the same | |
US6085074A (en) | Apparatus and method for amplifying an amplitude-varying signal | |
US7715812B2 (en) | RF power amplifier | |
WO1998006174A1 (fr) | Circuit integre haute frequence pour emetteur-recepteur radio haute frequence exempt de fuites de puissance haute frequence | |
US20050012547A1 (en) | High linearity doherty communication amplifier with phase control | |
US20060160503A1 (en) | Multi-mode power amplifier module for wireless communication devices | |
WO2000003490A1 (en) | Mobile telephone system | |
JP2002094331A (ja) | 高周波電力増幅装置及び無線通信機 | |
US20030045252A1 (en) | Power amplifier | |
US6658243B2 (en) | High frequency power amplifying apparatus having amplifying stages with gain control signals of lower amplitudes applied to earlier preceding stages | |
JPH09232887A (ja) | 高周波電力増幅器 | |
US7119614B2 (en) | Multi-band power amplifier module for wireless communications | |
JP2008104221A (ja) | 電力増幅器 | |
JP2006279994A (ja) | 電力増幅器および通信機器 | |
JP2004007796A (ja) | 電力増幅器および通信機器 | |
Khabbaz et al. | A high performance 2.4 GHz transceiver chip-set for high volume commercial applications | |
JP2770905B2 (ja) | アナログおよびディジタル携帯用の電話機兼用の電力増幅器 | |
WO2003017467A2 (en) | Adaptive biasing of rf power transistors | |
JP3408712B2 (ja) | フロントエンド回路 | |
Intermod | η=(Po-Pi)/Pdc=(Po-Pi)/VccIcc (2) where: Po= the output power, and Pi= the input power. | |
Admane et al. | A novel RF front-end chipset for ISM band wireless applications |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
WWE | Wipo information: entry into national phase |
Ref document number: 96191250.2 Country of ref document: CN |
|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): CN JP KR US |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1996931987 Country of ref document: EP |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
WWP | Wipo information: published in national office |
Ref document number: 1996931987 Country of ref document: EP |
|
WWE | Wipo information: entry into national phase |
Ref document number: 08849355 Country of ref document: US |
|
WWG | Wipo information: grant in national office |
Ref document number: 1996931987 Country of ref document: EP |