WO1997014021A1

WO1997014021A1 - Portable computer ultrasonic data acquisition system

Info

Publication number: WO1997014021A1
Application number: PCT/US1996/016262
Authority: WO
Inventors: Michael J. Moore; Francis J. Dodd
Original assignee: Westinghouse Electric Corporation
Priority date: 1995-10-12
Filing date: 1996-10-11
Publication date: 1997-04-17
Also published as: AU7437696A

Abstract

A circuit board (6) having a Type II PC form factor includes a receiver interface (28) for interfacing a receiver signal (18) from an ultrasonic transducer (10) and producing a received signal therefrom; an analog-to-digital converter (32) for converting the received signal to a plurality of digital signals; a first-in, first-out memory (36) for storing the digital signals; a control circuit (40) at least for controlling transfer of the digital signals from the A/D converter (32) to the FIFO memory (36); and a memory interface circuit (38) for interfacing the FIFO memory (36) with a portable computer (4).

Description

PORTABLE COMPUTER ULTRASONIC DATA ACQUISITION SYSTEM

BACKGROUND OF THE INVENTION Field of the Invention

This invention relates to an apparatus for acquiring ultrasonic information and, more particularly, to a circuit for interfacing ultrasonic signals to a portable computer. The invention also relates to a system for acquiring ultrasonic information. Background Information

Portable or laptop computers employing suitable software are capable of performing a variety of sophisticated data analysis functions. However, it is believed that such computer software cannot process, in real-time, the relatively large quantity of data contained in an entire ultrasonic waveform, such as an ultrasonic test waveform. Typically, ultrasonic waveforms include hundreds or thousands of data points which must be sampled at rates of at least about ten million samples per second. Hence, it is believed that portable computers are not capable of operating as real-time data acquisition devices for such waveforms.

There is a need, therefore, for a portable computer which is capable of acquiring, in real-time, an entire ultrasonic waveform for subsequent analysis.

SUMMARY OF THE INVENTION This and other needs are satisfied by the present invention which is directed to a portable circuit apparatus including receiver interface means for interfacing a receiver signal from an ultrasonic transducer and producing a received signal therefrom; conversion means for converting the received signal to a plurality of converted signals; memory means for storing the converted signals; control means at least for controlling transfer of the converted signals from the conversion means to the memory means; and memory interface means for interfacing the memory means with a portable computer.

As another aspect of the invention, an ultrasonic data acquisition system includes ultrasonic transducer means operatively associated with a material under inspection; ultrasonic pulser/receiver means connected to the ultrasonic transducer means for producing an ultrasonic receiver signal; portable computer means; and circuit means interconnected with the portable computer means for interfacing the portable computer means at least with the ultrasonic pulser/receiver means. The circuit means includes receiver interface means for interfacing the ultrasonic receiver signal and producing a received signal therefrom, conversion means for converting the received signal to a plurality of converted signals, memory means for storing the converted signals, control means at least for controlling transfer of the converted signals from the conversion means to the memory means, and memory interface means for interfacing the memory means with the portable computer.

It is an object of the present invention to provide an ultrasonic data acquisition system which utilizes a portable computer and which acquires an entire waveform of ultrasonic information in real-time.

It is also an object of the invention to provide a circuit for use with a portable computer to acquire an entire waveform of ultrasonic information in real¬ time.

BRIEF DESCRIPTION OF THE DRAWINGS A full understanding of the invention can be gained from the following description of the preferred embodiment when read in conjunction with the accompanying drawings in which:

Figure 1 is a block diagram of an ultrasonic data acquisition system- including a laptop computer with an interface card in accordance with the invention; Figure 2 is a block diagram of the interface card of Figure 1 ; Figure 3 is a block diagram of an ultrasonic data acquisition system in accordance with an alternative embodiment of the invention; and

Figures 4A-4D are schematic diagrams of the interface card of Figure 2. DESCRIPTION OF THE PREFERRED EMBODIMENT

As employed herein, the term "material under inspection" shall expressly include, but not be limited to any material (e.g. , metal; flat plate; fixed diameter pipe; slightly curved, fixed diameter pipe; piping welds) suitable for inspection by any ultrasonic technique (e.g. , pulse echo, pitch-catch, through transmission modes of operation).

Referring to Figure 1 , an ultrasonic data acquisition system 2 including a computer 4, such as a "laptop" personal computer (PC), having an interface (I/F) card 6 is illustrated. In the exemplary embodiment, the interface card 6 has a Type II PC or Personal Computer Memory Card International

Association (PCMCIA) form factor. The size of the exemplary interface card 6 is about 3.37 in. x 2.126 in. x 0.197 in. and the weight of the card 6 is less than about 2 oz., thereby facilitating use of a portable computer 4 in the system 2.

The system 2 acquires ultrasonic information for use in inspecting a material under inspection (MUI) 8. A suitable ultrasonic transducer (XDCR) 10 is operatively associated with the material 8. Preferably, the transducer 10 has a flexible body 11 which conforms to a wide variety of surfaces (e.g. , convex, concave, flat) such as the surface 12 of the material 8.

An ultrasonic pulser/receiver 14 is connected to the transducer 10 through a suitable interface 16. The pulser/receiver 14 includes an ultrasonic pulser which provides a trigger pulse, such as a suitable, unipolar, negative voltage spike, to the transducer 10 through the interface 16; and an ultrasonic receiver which produces an ultrasonic receiver signal 18 of suitable bandwidth on line 20 to the interface card 6. The ultrasonic pulser is operatively associated with the transducer 10 to induce oscillations in the material 8. The ultrasonic receiver is also operatively associated with the transducer 10 to produce the receiver signal 18 from the oscillations in the material 8.

As discussed in greater detail below in connection with Figures 2 and 4A-4D, the interface card 6 is interconnected with the PC 4 through a suitable bus 22. In the exemplary embodiment, a Type II PC or PCMCIA bus is employed for communication of signals extracted from the receiver signal 18 to random access memory (RAM) 24 and/or disk storage 26 of the PC 4, although the invention is applicable to a wide variety of PC busses. Also referring to Figure 2, the interface card 6 includes a receiver interface (RI/F) 28 for interfacing the receiver signal 18 and producing a received signal 30 therefrom; a converter 32 for converting the received signal 30 to a plurality of converted signals 34; a memory 36 for storing the converted signals 34; a memory interface (MI/F) 38, such as an output state machine, for interfacing the memory 36 to the bus 22 of the PC 4; and a suitable control circuit 40 having a control state machine 42 for controlling transfer of the converted signals 34 from the converter 32 to the memory 36.

Referring to Figure 3, an alternative ultrasonic data acquisition system 2' is illustrated. The system 2' is similar to the system 2 of Figure 1 , except that a scanner/transducer 44 including the transducer 10 and a scanner 46 is employed for scanning the surface 12 of the material 8. The scanner 46 has a linkage 48 mechanically coupled to the transducer 10. The scanner 46 includes a position output circuit which outputs position pulses 50 on line 52 to the interface card 6. The position pulses 50 correspond to a dimension of the surface 12, such as one of the coordinates of a rectangular (e.g. , X axis, Y axis) or a cylindrical (e.g. , θ angle, p radius) coordinate system, although the invention is applicable to fixed transducers, transducers which are manually moved in one or more axes, automatic scanners for movement in one or more axes, and scanners which provide encoder pulses in one or more axes. The exemplary scanner 46 outputs the position pulses

50 which correspond to a coordinate of the surface 12 of the material 8. For example, each of the pulses 50 may correspond to a predefined distance on the surface 12 of the material 8. As another example, for rectangular coordinates, the scanner 46 may scan in the X direction, increment in the orthogonal Y direction, and generate position pulses 50 proportional to the position of the transducer 10 with respect to the X direction of the surface 12.

Referring again to Figure 2, in the exemplary embodiment, the receiver interface 28 suitably buffers and filters the ultrasonic receiver signal 18 which is a time-variable, analog waveform having a plurality of frequency components. The converter 32 is preferably an analog-to-digital (A/D) converter which converts the time-variable, analog received signal 30 to a plurality of digital signals 34 with a resolution of at least about eight bits, although the invention is applicable to A/D converters having a wide resolution range (e.g. , less than 8 to 16 or more bits).

Under the control of the control state machine 42, the A/D converter 32 periodically converts the time-variable, analog received signal 30 to a plurality of digital signals 34. The number of digital samples converted from the analog received signal 30 is determined by a number of samples register (N) 54 which is loaded by the PC 4 through the bus 22 of Figure 1. In the exemplary embodiment, the number of samples ranges from 16 to 4080 in units of 16 (e.g. , 512 samples), although the invention is applicable to a wide range of samples per analog waveform. The conversion rate or digitization rate at which the digital samples are converted from the analog received signal 30 is determined by a sampling rate register (S) 56 which is also loaded through the bus 22. In the exemplary embodiment, the sampling rate includes 40, 20, 10, 5, 2.5, 1.25, 0.625 or 0.3125 MHz, although the invention is applicable to a wide range of rates (e.g. , 100 MHz, 200 MHz) for sampling the analog waveform. At a sampling rate of 10 MHz with

4080 samples, for example, the duration of the waveform is about 0.4 ms. The duration of the waveform may range from about 0.4 μs to about 13 ms, although the invention is applicable to a wide range of ultrasonic receiver waveforms having a variety of durations. In this manner, the interface card 6 facilitates the digitization and storage of the entire ultrasonic waveform, in real-time, for the PC 4.

In the exemplary embodiment, the memory 36 is a 4K byte, first-in, first-out (FIFO) memory for storing the digital signals 34 and interfacing the memory interface 38, although the invention is applicable to a wide range of memory sizes and types (e.g. , random access memory, static memory, dynamic memory) for storing digital signals at least for substantially the entire duration of the waveform. Interfaces 62,64 of the control state machine 42 control the transfer ^' of the digital signals 34 from the A/D 32 to the FIFO memory 36. These interfaces 62,64 cooperate with the register (S) 56 and the control state machine 42 to control the conversion rate and, hence, the corresponding storage rate of the digital signals 34. The memory interface 38, in turn, controls transfer of the digital signals 34 stored in the memory 36 from such memory to the bus 22 of the PC 4 of Figure 1.

The receiver interface 28 preferably interfaces with the ultrasonic receiver signal 18 which may either be a unipolar analog signal (e.g. , 0.0 to +2.0 V) or a bipolar analog signal (e.g. , -1.0 to + 1.0 V). The unipolar/bipolar nature of the receiver signal 18 is selectably interfaced by the receiver interface 28. A digital-to-analog (D/A) converter interface (D/A I/F) 58 of the control circuit 40 provides a digital DC offset value 59 to a D/A converter 60 for producing an analog DC offset signal 1 12 from the digital DC offset value 59. The D/A converter interface 58 is controlled by the PC 4 through the bus 22 of Figure 1 to load the digital DC offset value 59. In the exemplary embodiment, the DC offset value 59 ranges from 0 to 2047, which corresponds to 0.0 to 2.047 V in 1 mV steps, although the invention is applicable to a wide range of offset values and corresponding offset signals.

Continuing to refer to Figure 2, an input trigger signal 66 on line 68 is input by an input trigger divider 70 having a trigger scaling register (T) 72 which is loaded by the PC 4 through the bus 22 of Figure 1. In the exemplary embodiment, the trigger scaling value ranges from 1 to 255, although the invention is applicable to a wide range of trigger scaling values. In the embodiment of Figure

1, the trigger scaling value is preferably set to one and a software input trigger signal is controlled by the PC 4 through the bus 22 according to Table I below. The PC 4 employs the software input trigger signal to control the start of the plural conversions by the A/D 32 and the storage of the converted waveform in the FIFO memory 36. In this case, an internal trigger, which is triggered under software control through the PC bus 22, is employed and the external position pulses 50 of the scanner 46 of Figure 3 are not used.

In the embodiment of Figure 3, the trigger scaling value is loaded with an appropriate value by the PC 4 through the bus 22 and the position pulses 50 on line 52 are identical to those on line 68, although the invention is applicable to other external trigger sources. The input trigger divider 70 is preset with the trigger scaling value of register (T) 72 for values of two or greater. On the other hand, the input trigger divider 70 is bypassed for trigger scaling values of one. The divider 70, in turn, is counted down with the position pulses 50. When the count reaches zero, the output 78 is active. For this external trigger, position pulses 50 which are at least three sample periods in length are employed. The input trigger divider 70 cooperates with the control state machine 42, which outputs the output trigger 74, by counting a count of the position pulses 50 output by the scanner 46 and, then, outputting the output 78 after the count equals the trigger scaling value. Hence, the input trigger divider 70 divides the scanner position pulses 50 to provide proper scaling for the output trigger 74 on line 76 to the pulser/receiver 14. In response to the output trigger 74, the ultrasonic pulser of the pulser/receiver 14 produces the trigger pulse to the transducer 10 through the interface 16.

In a like manner as the position pulses 50 which correspond to a predefined distance on the surface 12 of the material 8 of Figure 3, the input trigger divider 70 facilitates output triggers 74 which correspond to another predefined distance on the surface 12 (e.g. , one of the output triggers 74 per unit distance, such as a distance corresponding to ten of the position pulses 50). In this manner, the spatial sampling rate of the transducer 10 is insensitive to variations in the speed of the scanner 46 and, hence, provides a constant number of samples per unit distance scanned.

Referring again to Figures 1 and 2, the output 78 of the input trigger divider 70 is also input by a trigger delay counter 80. The counter 80 is preset by a conversion delay register (D) 82 which is loaded by the PC 4 through the bus 22. In the exemplary embodiment, the conversion delay value ranges from 0 to 4095 sample periods, although the invention is applicable to a wide range of conversion delay values. The register (D) 82 provides a software controlled system delay of the signal 84 to the control state machine 42. In this manner, the control signal 63 on interface 62 to the A/D 32 and the control signal 65 on interface 64 to the memory 36 are delayed by the number of sample periods, thereby delaying the conversion of the received analog signal 30 to the first of the converted digital signals 34 and permitting waveform recording in the memory 36 to begin at the desired time of flight of the oscillations into the material 8. This accommodates a wide range of delays in the pulser of the pulser/receiver 14 as well as a wide range of inspection depths within the material 8.

Continuing to refer to Figure 2, the output of a suitable oscillator or clock 86, which in the exemplary embodiment is a 40 MHz oscillator, is input on line 87 by a clock and timing circuit 88 of the control circuit 40 to control the timing thereof. The control state machine 42 also synchronizes internal timing signals with the clock 86 in order to, for example, prevent jitter in the digital converted data 34 stored in the memory 36. The output 78 of the input trigger divider 70 is input by the control state machine 42 and is synchronized with the clock signal 63 and the signal 84 output by the trigger delay counter 80. The output trigger 74 is active for the number of samples defined by register (N) 54 plus the number of samples defined by register (D) 82. A start/stop signal 90 on line 92 is employed by the control state machine 42 to start, if active, or stop, if inactive, the conversion of the received analog signal 30 and the corresponding waveform recording in the memory 36. For example, if the scanner 46 of Figure 3 is indexing the transducer 10, the signal 90 is inactive in order that spurious or unwanted data is not recorded, thereby conserving locations of the memory 36 for the actual waveform to be recorded.

Referring to Figures 4A-4D, the ultrasonic receiver signal (VIN) 18, which is referenced to analog ground (AGND) 132, is input on line 20 to a buffer/offset amplifier 94 including operational amplifier 96. The line 20 is connected to an I/O connector 95 which also includes the lines 68, 76 and 92 for the input trigger 66, output trigger 74 and start/stop 90 signals, respectively. The output 98 of the operational amplifier 98 is filtered by a low-pass filter 100. Preferably, the filter 100 passes the received signal (AIN) 30 to the A/D converter 32 without frequencies of the signal 98 above about one-half of the conversion rate defined by the register (S) 56 of Figure 2. For example, in the exemplary embodiment, with a 40 MHz conversion rate, the filter 100 is a low-pass, anti¬ aliasing filter, such as a 20 MHz single pole RC filter.

In the exemplary embodiment, the control circuit 40 is a suitably programmed, field programmable gate array, such as model ISPLSI1048 marketed by Lattice. The circuit 40 controls the serial D/A converter 60, such as model AD8300 marketed by Analog Devices, with chip select line (OFF-CS) 102, load line

(DAC-LD) 104, serial data input line (DAC-SDI) 106, clock line (DAC-CLK) 108; and clear line (DAC-CLR) 1 10 based on the digital DC offset value from the PC 4 which is communicated to the D/A converter 60 through the D/A converter interface 58 of Figure 2. The D/A 60, in turn, produces the analog DC offset signal (OFFSET) 112 from the digital DC offset value 59 of Figure 2. The signal 1 12 is input on line 114 by the buffer/offset amplifier 94 for summing with the ultrasonic receiver signal (VIN) 18 on line 20. For example, a suitable positive offset voltage on line 1 14 produces a unipolar received signal 30 from a bipolar receiver signal 18 and the offset signal 112. On the other hand, a zero offset voltage on line 114 produces a unipolar received signal 30 from a unipolar receiver signal 18 and the offset signal 112.

The D/A interface 58 (shown in Figure 2) of the circuit 40 also controls another serial D/A converter 1 18, like converter 60, with chip select line

(REF-CS) 120 and lines 104, 106, 108, 110. The D/A converter interface 58 is controlled by the PC 4 through the bus 22 of Figure 1 to define a DC reference value. In the exemplary embodiment, the DC reference value ranges from 0 to 2047, which corresponds to 0.0 to 2.047 V in 1 mV steps, although the invention is applicable to a wide range of reference values and corresponding reference signals. The D/A 1 18, in turn, produces the analog DC reference signal (VREF) 122 for input by the A/D converter 32 which, in the exemplary embodiment, is model SPT7860 marketed by Signal Processing Technologies. A suitable filtering and decoupling network 124 inputs digital +5V power (VCC) 126 and ground (GND) 128 from the bus 22 and respectively outputs analog +5V power (AVCC)

130 and analog ground (AGND) 132 for input by the A/D converter 32.

Still referring to Figures 4B-4C, A/D conversions by the converter 32 are controlled by clock signal 63 from the circuit 40. In turn, the exemplary 8- bit digital value 34 is output for input by the FIFO memory 36, which in the exemplary embodiment is model IDT72241 marketed by Integrated Device

Technologies, Inc. Storage of the digital signals 34 in the memory 36 is controlled by write enable signal (WEN/) 65 and clock signal 63 whenever the FIFO full signal (FF/) 134 is inactive. The storage rate and the number of samples stored are defined by the registers 56 and 54, respectively, of Figure 2. Retrieval of the stored digital signals 34 from the memory 36 on data lines 136 is controlled by read enable signal (REN/) 138, read signal (READ/) 139 and read clock signal (RCLK) 140 until the FIFO empty signal (EF/) 142 is active.

The memory interface 38 of Figure 2 provides the interface between the PC bus 22 and the FIFO memory 36 and registers 54,56,72,82. The interface 38 includes 16 data lines (D0-D15) 144, nine address lines (A0-A8) 146, and seven control signals 148. The control signals 148 include chip enable signal (CEI/) 150, chip enable signal (CE2/) 152, write signal (IOWR/) 154, read signal (IORD/) 156, write enable signal (WE/) 158, register signal (REG/) 160 and output enable signal (OE ) 162 of the exemplary Type II PC bus 22. Data is read and written through the PC bus 22 according to Table I.

TABLE I

DATA BITS READ/WRITE OFFSET ADDRESS card status 8 READ 2H card control 8 WRITE 2H card mode 8 WRITE 4H sampling rate (S) 56 3 WRITE 5H samples (N) 54 8 WRITE 6H trigger scaling (T)72 8 WRITE 8H

FIFO data lines 136 8 READ AH delay-Is (D) 82 8-ls WRITE CH delay- s (D) 82 4-ms WRITE DH card status 8 READ EH disarm 0 WRITE EH software trigger 0 WRITE FH

The interface card 6 is armed for data acquisition upon writing to the number of samples register (N) 54 and is disarmed upon writing to the disarm register at offset address EH. Bits 0, 1 ,2,4,5,7 of the card mode register at offset address 4H control the respective signals 108, 104, 106, 102, 120, 1 10. The delay value is loaded with the eight least significant (Is) bits at offset address CH and the four most significant (ms) bits at offset address DH.

Referring again to Figure 2, bit 2 of the card control register at offset address 2H defines a continuous data acquisition mode. In the continuous mode, the control state machine 42 outputs a plurality of triggers 74 on line 76 to the pulser/receiver 14 in order to produce a corresponding plurality of ultrasonic receiver signals 18. For example, a first trigger 74 A may correspond to a first ultrasonic receiver signal 18A and, at a later time, a second trigger 74B may . correspond to a second ultrasonic receiver signal 18B. After the first trigger 74 A and before the second trigger 74B is output, the memory 36 stores the converted digital signals 34 corresponding to the first ultrasonic signal 18 A. Next, the PC 4 inputs the converted digital signals in the memory 36 corresponding to the first ultrasonic signal 18A through the memory interface 38. Then, after the second trigger 74B, the PC 4 inputs the converted digital signals in the memory 36 corresponding to the second ultrasonic signal 18B through the memory interface 38. In this manner, the converted ultrasonic receiver signals 18A, 18B are input by the PC 4.

In the embodiment of Figure 3, for example, the triggers 74A.74B are output as a function of the number of the position pulses 50 output by the scanner 46. As a non-limiting example, if there are N = 10 position pulses 50 for each of the triggers 74A,74B, then the PC 4 inputs the converted digital signals from the memory 36 during the time of the last N-l =9 position pulses 50. Although the PC 4 inputs the converted signals stored in the memory 36 from such memory at a rate (e.g. , about 1 MHz) which is typically much slower than the sampling rate (e.g. , 40 MHz) defined by register (S) 56, the converted digital signals 34 from the plural ultrasonic receiver signals 18A, 18B are acquired by the interface card 6 in real-time and are continuously transferred to the PC 4.

The exemplary portable PC 4 may be readily moved from one ultrasonic testing application to another such application or to an entirely different application. Such mobility is highly advantageous whenever various ultrasonic testing applications are geographically distributed over a relatively large number of disparate locations. For example, the various materials under ultrasonic inspection may include a variety of metal objects, such as a relatively large number of pipe welds distributed throughout a nuclear power plant. The exemplary systems 2,2' facilitate ultrasonic data acquisition, testing and analysis of a variety of materials in which the entire ultrasonic waveform is acquired in real-time independent of the speed of the PC's software program and independent of the bandwidth of the PC's I/O bus.

The exemplary interface card 6 facilitates the acquisition of a larger number of the digital samples 34 at a faster, more consistent digitization rate than for acquisition of digital samples solely with a PC's software through such PC's I/O ^" bus. The interface card 6, furthermore, reduces the size, weight and power requirements of known ultrasonic waveform acquisition systems.

While specific embodiments of the invention have been described in detail, it will be appreciated by those skilled in the art that various modifications and alternatives to those details could be developed in light of the overall teachings of the disclosure. Accordingly, the particular arrangements disclosed are meant to be illustrative only and not limiting as to the scope of the invention which is to be given the full breadth of the appended claims and any and all equivalents thereof.

Claims

What is Claimed is:

1. A portable circuit apparatus for use with a portable computer and an ultrasonic transducer having a receiver signal, said apparatus comprising: receiver interface means for interfacing the receiver signal and producing a received signal therefrom; conversion means for converting the received signal to a plurality of converted signals; memory means for storing the converted signals; control means at least for controlling transfer of the converted signals from said conversion means to said memory means; and memory interface means for interfacing said memory means with said portable computer.

2. The apparatus of Claim 1 wherein said received signal is a time- variable analog signal; wherein said converted signals are a plurality of digital signals; and wherein said conversion means includes analog-to-digital converter means for converting the time-variable analog signal to the digital signals.

3. The apparatus of Claim 2 wherein the analog-to-digital converter means converts the time-variable analog signal at a rate of at least about 10 million analog-to-digital conversions per second.

4. The apparatus of Claim 3 wherein the digital signals of the analog-to-digital converter means have a resolution of at least about eight bits.

5. The apparatus of Claim 3 wherein the rate of converting the time- variable analog signal is at least about 40 million analog-to-digital conversions per second.

6. The apparatus of Claim 2 wherein the analog-to-digital converter means has a conversion rate for converting the time-variable analog signal; wherein the time-variable analog signal has a plurality of frequencies; and wherein said receiver interface means includes low-pass filter means for passing to the analog-to- digital converter means the frequencies of the time-variable analog signal below about one-half of the conversion rate.

7. The apparatus of Claim 1 wherein the receiver signal is a unipolar receiver signal; and wherein said receiver interface means includes means for interfacing the unipolar receiver signal.

8. The apparatus of Claim 1 wherein the receiver signal is a bipolar receiver signal; and wherein said receiver interface means includes means for interfacing the bipolar receiver signal.

9. The apparatus of Claim 1 wherein said memory means includes first-in, first-out memory means for storing the converted signals and interfacing said memory interface means.

10. The apparatus of Claim 1 wherein said control means includes means for controlling transfer of the converted signals from said conversion means to said memory means; and wherein said memory interface means includes means for controlling transfer of the converted signals stored in said memory means from said memory means to said portable computer.

1 1. An ultrasonic data acquisition system for use with a material under inspection, said system comprising: ultrasonic transducer means operatively associated with said material under inspection; ultrasonic pulser/receiver means connected to said ultrasonic transducer means for producing an ultrasonic receiver signal; portable computer means; and circuit means interconnected with said portable computer means for interfacing said portable computer means at least with said ultrasonic pulser/receiver means, said circuit means comprising: receiver interface means for interfacing the receiver signal and producing a received signal therefrom, conversion means for converting the received signal to a plurality of converted signals, memory means for storing the converted signals, control means at least for controlling transfer of the converted signals from said conversion means to said memory means, and memory interface means for interfacing said memory means with said portable computer means.

12. The system of Claim 11 wherein said portable computer means is a laptop computer.

13. The system of Claim 1 1 wherein said circuit means has a Type

II PC form factor.

14. The system of Claim 11 wherein said memory means includes means for storing at least about 4000 converted signals.

15. The system of Claim 1 1 wherein said conversion means includes means for converting the received signal at a conversion rate of at least about 10

MHz.

16. The system of Claim 15 wherein the conversion rate of said means for converting the received signal is at least about 40 MHz.

17. The system of Claim 1 1 wherein said received signal is a time- variable analog waveform having a duration; wherein said converted signals are a plurality of digital signals; wherein said conversion means, is an analog-to-digital converter which periodically converts the time-variable analog waveform to the digital signals; and wherein said memory means includes means for storing the digital signals for substantially the entire duration of the waveform.

18. The system of Claim 1 1 wherein said material under inspection is a pipe weld.

19. The system of Claim 1 1 wherein said control means includes means interfacing said portable computer means for defining the number of the converted signals.

20. The system of Claim 1 1 wherein the receiver signal is a bipolar receiver signal and the received signal is a unipolar received signal; wherein said control means includes means interfacing said portable computer means for defining an offset value; and wherein said receiver interface means includes means for producing an offset signal from the offset value, and means for producing the unipolar received signal from the bipolar receiver signal and the offset signal.

21. The system of Claim 1 1 wherein said control means includes means interfacing said portable computer means for defining a rate for converting the received signal, and means for controlling said conversion means for converting the received signal to the converted signals at said rate for converting.

22. The system of Claim 1 1 wherein said ultrasonic pulser/receiver means includes: pulser means operatively associated with said ultrasonic transducer means for inducing oscillations in said material under inspection, and receiver means operatively associated with said ultrasonic transducer means for producing the receiver signal from said material under inspection.

23. The system of Claim 22 wherein said control means includes pulser interface means for outputting a trigger to said pulser means in order to induce oscillations in said material.

24. The system of Claim 1 1 wherein said material under inspection has a surface; wherein said ultrasonic transducer means includes scanning means for scanning the surface of said material; and wherein said control means includes means for interfacing said scanning means.

25. The system of Claim 24 wherein the surface of said material has a dimension; wherein said scanning means includes means outputting position pulses to said control means corresponding to the dimension of the surface of said material; and wherein said control means includes means outputting a trigger to said pulser/receiver means as a function of the number of the position pulses output by said scanning means.

26. The system of Claim 25 wherein said control means includes means interfacing said portable computer means for providing a trigger scaling value, and means cooperating with said means outputting the trigger to said pulser/receiver means for counting a count of the position pulses output by said scanning means and outputting the trigger after the count equals the trigger scaling value.

27. The system of Claim 1 1 wherein said control means includes means interfacing said portable computer means for providing a conversion delay value, and means employing the conversion delay value for delaying the conversion of the received signal to the first of the converted signals.

28. The system of Claim 1 1 wherein said control means includes pulser interface means for outputting a trigger to said pulser/receiver means in order to produce the ultrasonic receiver signal; wherein said memory means includes means for storing the converted signals in real-time at a first rate; and wherein said portable computer means inputs the converted signals stored in said memory means from said memory means at a second rate which is slower than the first rate.

29. The system of Claim 28 wherein said pulser interface means outputs a plurality of triggers to said pulser/receiver means in order to produce a corresponding plurality of ultrasonic receiver signals, with a first trigger corresponding to a first ultrasonic receiver signal and a second trigger corresponding to a second ultrasonic receiver signal; wherein, after the first trigger and before the second trigger is output by said pulser interface means, said memory means stores the converted signals corresponding to the first ultrasonic signal therein and said portable computer means inputs said converted signals corresponding to the first ultrasonic signal, thereby permitting the ultrasonic receiver signals to be input by said portable computer means.