WO1997014289A3 - Protocol for communication with dynamic memory - Google Patents

Protocol for communication with dynamic memory Download PDF

Info

Publication number
WO1997014289A3
WO1997014289A3 PCT/US1996/016835 US9616835W WO9714289A3 WO 1997014289 A3 WO1997014289 A3 WO 1997014289A3 US 9616835 W US9616835 W US 9616835W WO 9714289 A3 WO9714289 A3 WO 9714289A3
Authority
WO
WIPO (PCT)
Prior art keywords
data transfer
controller
data
control information
system includes
Prior art date
Application number
PCT/US1996/016835
Other languages
French (fr)
Other versions
WO1997014289A2 (en
Inventor
Richard Maurice Barth
Frederick Abbot Ware
John Bradly Dillon
Donald Charles Stark
Craig Edward Hampel
Matthew Murdy Griffin
Original Assignee
Rambus Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Family has litigation
First worldwide family litigation filed litigation Critical https://patents.darts-ip.com/?family=24175641&utm_source=google_patent&utm_medium=platform_link&utm_campaign=public_patent_search&patent=WO1997014289(A3) "Global patent litigation dataset” by Darts-ip is licensed under a Creative Commons Attribution 4.0 International License.
Application filed by Rambus Inc filed Critical Rambus Inc
Priority to AT96936776T priority Critical patent/ATE228675T1/en
Priority to JP9516077A priority patent/JPH11513830A/en
Priority to AU74612/96A priority patent/AU7461296A/en
Priority to KR1019980702870A priority patent/KR19990066947A/en
Priority to EP96936776A priority patent/EP0870241B2/en
Priority to DE69625082T priority patent/DE69625082T2/en
Publication of WO1997014289A2 publication Critical patent/WO1997014289A2/en
Publication of WO1997014289A3 publication Critical patent/WO1997014289A3/en

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1605—Handling requests for interconnection or transfer for access to memory bus based on arbitration
    • G06F13/161—Handling requests for interconnection or transfer for access to memory bus based on arbitration with latency improvement
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C5/00—Details of stores covered by group G11C11/00
    • G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/066—Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1072—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C8/00—Arrangements for selecting an address in a digital store
    • G11C8/12—Group selection circuits, e.g. for memory block selection, chip selection, array selection

Abstract

A system and method for performing data transfers within a computer system is provided. The system includes a controller configured to dynamically adjust the interleave of the communications required to perform a series of data transfer operations to maximize utilization of the channel over which the communications are to be performed. The controller is able to vary the time interval between the transmission of control information that requests a data transfer and the performance of the data transfer by signaling the beginning of the data transfer with a strobe signal sent separate from the control information. The controller is able to defer the determination of how much data will be transferred in the operation by initiating the termination of a data transfer with a termination signal. The method provides a technique for distinguishing between identical control signals that are carried on the same line. The system includes a memory device with control circuitry that allows no more than one memory bank powered by any given power supply line to perform sense or precharge operations.
PCT/US1996/016835 1995-10-19 1996-10-18 Protocol for communication with dynamic memory WO1997014289A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
AT96936776T ATE228675T1 (en) 1995-10-19 1996-10-18 COMMUNICATION PROTOCOL FOR DYNAMIC MEMORY
JP9516077A JPH11513830A (en) 1995-10-19 1996-10-18 Protocol for communication with dynamic memory
AU74612/96A AU7461296A (en) 1995-10-19 1996-10-18 Protocol for communication with dynamic memory
KR1019980702870A KR19990066947A (en) 1995-10-19 1996-10-18 Protocol for communication with dynamic memory
EP96936776A EP0870241B2 (en) 1995-10-19 1996-10-18 Protocol for communication with dynamic memory
DE69625082T DE69625082T2 (en) 1995-10-19 1996-10-18 COMMUNICATION PROTOCOL FOR DYNAMIC MEMORY

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/545,292 US5748914A (en) 1995-10-19 1995-10-19 Protocol for communication with dynamic memory
US08/545,292 1995-10-19

Publications (2)

Publication Number Publication Date
WO1997014289A2 WO1997014289A2 (en) 1997-04-24
WO1997014289A3 true WO1997014289A3 (en) 1998-04-02

Family

ID=24175641

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1996/016835 WO1997014289A2 (en) 1995-10-19 1996-10-18 Protocol for communication with dynamic memory

Country Status (8)

Country Link
US (4) US5748914A (en)
EP (5) EP2290549B1 (en)
JP (1) JPH11513830A (en)
KR (1) KR19990066947A (en)
AT (1) ATE228675T1 (en)
AU (1) AU7461296A (en)
DE (2) DE02012810T1 (en)
WO (1) WO1997014289A2 (en)

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US9411538B2 (en) 2008-05-29 2016-08-09 Micron Technology, Inc. Memory systems and methods for controlling the timing of receiving read data
US9146811B2 (en) 2008-07-02 2015-09-29 Micron Technology, Inc. Method and apparatus for repairing high capacity/high bandwidth memory devices
US9275698B2 (en) 2008-07-21 2016-03-01 Micron Technology, Inc. Memory system and method using stacked memory device dice, and system using the memory system
US9602080B2 (en) 2010-12-16 2017-03-21 Micron Technology, Inc. Phase interpolators and push-pull buffers
US9171597B2 (en) 2013-08-30 2015-10-27 Micron Technology, Inc. Apparatuses and methods for providing strobe signals to memories
US9437263B2 (en) 2013-08-30 2016-09-06 Micron Technology, Inc. Apparatuses and methods for providing strobe signals to memories

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US5913046A (en) 1999-06-15
US5748914A (en) 1998-05-05
EP2290549A3 (en) 2011-05-18
EP0870241A1 (en) 1998-10-14
EP2290550A2 (en) 2011-03-02
WO1997014289A2 (en) 1997-04-24
US6122688A (en) 2000-09-19
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EP2290551B1 (en) 2013-06-12
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DE69625082D1 (en) 2003-01-09
EP2290551A2 (en) 2011-03-02
EP0870241B1 (en) 2002-11-27
EP2290550B1 (en) 2014-01-15
EP1244110A3 (en) 2005-11-09
JPH11513830A (en) 1999-11-24
US5966731A (en) 1999-10-12
DE69625082T2 (en) 2003-09-11
EP1244110A2 (en) 2002-09-25
EP2290549A2 (en) 2011-03-02
DE02012810T1 (en) 2006-01-26
ATE228675T1 (en) 2002-12-15
KR19990066947A (en) 1999-08-16
EP2290550A3 (en) 2011-12-21

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