WO1997016743A1

WO1997016743A1 - Conditionally generating test instructions depending on a package configuration

Info

Publication number: WO1997016743A1
Application number: PCT/US1996/017424
Authority: WO
Inventors: Richard Pye; Steven M. Blumenau; Paul L. Keating; William S. Schymik
Original assignee: Genrad, Inc.
Priority date: 1995-11-02
Filing date: 1996-10-30
Publication date: 1997-05-09

Abstract

A method of generating a test program by conditionally generating a test instruction for a part depending on the part package (as shown in Package Type Library, 6010) and not depending on the part circuit. The method can conditionally generate an instruction by comparing the number of pins on the package (as shown in Package Type Library, 6010) to a count threshold associated with the instruction. The method can also conditionally generate an instruction by comparing the pin pitch of the package to a pitch threshold associated with the instruction.

Description

CONDITIONALLY GENERATING TEST INSTRUCTIONS DEPENDING ON A PACKAGE CONFIGURATION

BACKGROUND OF THE INVENTION

Field ofthe Invention

This invention relates generally to a system and method for programming a system for testing a circuit assembly, and, more particularly, to a system and method for conditionally generating test instructions depending on package configurations of parts on the circuit assembly. Description of Related Art

Electronic products such as televisions typically contain one or more circuit boards manufactured by an assembly line. One method of testing a circuit board, after manufacture, is to insert the board in its product. If the product then operates, the board is deemed to be good. If the product does not operate, the board is deemed to be defective. One option in dealing with a defective board is to discard it. This option is often undesirable, however, because a board can be expensive to manufacture. Another option is to have a technician manually locate the defect on the board by probing with an oscilloscope, for example. A problem with this second option is substantial labor cost for the technicians time.

Another method of testing a circuit board, after manufacture, is to employ automatic test equipment that can detect a defective board and, sometimes, automatically diagnose a board defect. Test programs for the automatic test equipment have been complex Complex test programs can be expensive to debug, as substantial engineering time must be expended in the debugging process. Complex test programs can be expensive to support, as complex programs tend to require more complex test hardware and fixturing. Finally, and often most important, complex test programs can be expensive to execute, as more complex programs take longer to execute and, therefore, can be a bottleneck in the in the circuit board production process.

Test programs have been unnecessarily complex because test program writers, or generators, often generate every available test for each part on a circuit board, even when generation of a particular test for a particular part is not cost effective. As a practical matter it has been difficult to limit this unnecessary complexity of test programs. For example, generating a test depending on whether a part has a certain circuit can be both overinclusive, resulting in unnecessary tests, and underinclusive, omitting tests for parts that should be tested. In other words, the circuit inside a part is not necessarily a good indication of whether the part should be subjected to a certain kind of test.

SUMMARY OF THE INVENTION

It is an object ofthe present invention to provide an efficient test generation system that alleviates some problems ofthe prior art.

To achieve this and other objects ofthe present invention, in a system including a circuit assembly having a plurality parts and means for executing an instruction to test the assembly, a method comprises the steps of conditionally generating a first type of instruction for a first part in the plurality of parts, depending on a package configuration ofthe first part; and conditionally generating the first type of instruction for a second part in the plurality of parts, depending on a package configuration ofthe second part.

According to another aspect ofthe present invention, a method of generating a test program to test an assembly, the assembly including a plurality of parts, each part including a respective circuit and a respective package configuration, the package configuration including a certain number and orientation of electrical contacts for interfacing to the assembly, comprises the step, performed for each part, of generating a portion ofthe test program corresponding to the part, the content ofthe program portion being dependent on the contact configuration ofthe part, the content ofthe portion being independent of the circuit ofthe part.

According to yet another aspect ofthe present invention, s system for generating a test for a circuit assembly having a plurality parts, comprises means for storing a plurality of rules each corresponding to a respective instruction type, each rule capable of containing a rule variable; and means for performing the following steps for a first one ofthe rules and for a first one ofthe parts: evaluating the rule variable by determining a package configuration of the part, to produce an evaluation result, and conditionally generating an instruction for execution at a first location, depending on the evaluation result. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is diagram of a manufacturing process incorporating the programming method ofthe preferred embodiment ofthe invention.

Figs. 2 A is a plan view of a circuit board produced by the process shown in Fig 1

Fig. 2B is a side view ofthe circuit board shown in Fig 2 A

Fig. 3 is an illustration showing an aspect of the testing section shown in Fig 1

Fig. 4 is a diagram showing another aspect ofthe testing section

Fig. 5 is a diagram of a data flow in the testing section

Fig. 6 is a diagram emphasizing a portion of Fig. 5

Fig. 7 is another diagram emphasizing another portion of Fig. 5.

Fig. 8 is a diagram showing another data flow in the testing section

Fig. 9 is a procedural flow chart showing a processing performed by the preferred embodiment ofthe invention.

Figs. 10A, 10B, and IOC show a flow of defect data in the preferred embodiment of the invention.

Fig. 1 1 shows tables for translating faults into site defects.

The accompanying drawings which are incorporated in and which constitute a part of this specification, illustrate embodiments ofthe invention and, together with the description, explain the principles ofthe invention, and additional advantages thereof

DESCRIPTION OF THE PREFERRED EMBODIMENT The preferred embodiment is a method of generating a test program by conditionally generating a test instruction for a part depending on the part package and not depending on the part circuit. The method can conditionally generate an instruction by comparing the number of pins on the package to a count threshold associated with the instruction The method can also conditionally generate an instruction by comparing the pin pitch ofthe package to a pitch threshold associated with the instruction.

Fig. 1 shows a circuit board manufacturing facility according to a preferred embodiment ofthe present invention. Paste section 1010 receives bare circuit boards 1005 and applies paste to selected portions ofthe top of a board. Component placement section 1015 then receives the board and places electrical components 1020 on board locations having paste Components 1020, 1022, and 1024 include integrated circuit (IC) packages and discrete resistors, capacitors, diodes, and transistors

Reflow section 1025 then applies heat to melt the paste Flip section 1030 then turns the board over to expose the other side ofthe board Glue section 1045 applies glue to selected portions ofthe bottom ofthe board and shoot section 1050 applies additional components 1024 to board locations containing glue Flip section 1052 then turns the board over to expose the other side ofthe board Insertion section 1020 places additional components 1022 on top ofthe board by inserting components 1022 in through holes in the board Wave solder section 1055 applies molten solder, an alloy having a low melting point, to the bottom ofthe board to secure components onto the board and establish electrical contact between the components and electrical paths on the board

Fig 2A is a plan view of a television circuit board 100 after leaving wave solder section 1055, and Fig 2B is a view ofthe board 100 taken along the line A-A shown in Fig. 2A. Circuit board 100 includes a top surface 105 and a bottom surface 1 15 These surfaces include parts 2015, 2020, 2010, 2025, 2030, 2035, 2037, 2040, 2043, 2057, 2045, 2050, 2055, 2067, and 2069. Printed on board 100 are "designators" IC_2015, IC_2020, IC_2010, C_2025, C_2030, R_2035, IC_2037, R_2040, IC_2043, IC_2057, IC_2045, IC_2050, SW_2055, R_2067, and C_2069, each corresponding to one of parts 2015, 2020, 2010, 2025, 2030, 2035, 2037, 2040, 2043, 2057, 2045, 2050, 2055, 2067, and 2069 respectively.

Testing section 1 100, shown in Fig 1, performs tests to verify that each circuit board 100 is assembled properly

Fig. 3 shows testing section 1 100 in more detail Conveyor 1105 moves circuit boards 100 through various testing stations in the direction of arrow 1 106 Electrical station 2130 applies electrical signals to one ofthe circuit boards 100 and receives electrical signals from the circuit board 100 through pins 2132 Electrical station 2130 may be any one of a variety of automatic testers now available

Subsequently, optical station 2200 illuminates the board with lamps 2232, allowing optical recognizer 2236 to electronically photograph the board and analyze the photograph with a processor Optical analyzer 2236 may be any one of several programmable optical inspectors now available, including one ofthe Theta Vision Systems available from Theta Group, Inc., 3077 A Leeman Ferry, Rd , Huntsville, AL 35801 Subsequently, x-ray station 2300 irradiates the board with an x-ray source 2332 and detects x-rays passing through the board with detector 2334. X-ray station 2300 may be any one of several programmable x-ray analyzers now available, including one ofthe systems available from Nicolet Imaging Systems, 8221 Arjons Drive, San Diego, CA 92126, or from FEINFOCUS USA, Inc. 5142 N. Clareton Drive, Suite 160, Agoura Hills, CA 91301

If a board 100 passes all tests at stations 2100, 2200, and 2300, a board then goes to manual inspection station 2400. At manual inspection station 2400, an inspector 245 manually inspects board 100 in an attempt to detect latent defects. Inspector 245 consults a list of defects not covered by any of stations 2130, 2200, or 2300. These types of uncovered defects, called "escapes," are compiled by programming station 2100, as discussed in more detail below. Inspector 245 consults a list 2410 of escapes for board 100. List 2410 was printed by printer 2425, connected to networks 2115 (described in connection with Fig. 4) Alternatively, inspector 245 can view the escapes for board 100 on computer terminal 2415, also connected to network 21 15.

Subsequently, if board 100 passes manual inspection at manual inspection 2400 a technician 220 inserts the board 100 in its respective location in television 105. If television 105 fails to operate properly after insertion of board 100, board 100 is taken to manual diagnostic station 2430, where technician 225 attempts to diagnosis the defect in the board, by manually inspecting the board and by probing with an oscilloscope, a volt meter, or a logic analyzer. After diagnosis, technician 225 enters diagnostic information into computer terminal 2435, connected to network 2115, for transmission to data collection program 10035, described in connection with Fig. 10A et seq.

Fig. 4 shows another aspect of testing section 1100. Programming station 2100 includes an IBM compatible PC having processor 2010, random access memory 2150, disk memory 2105 for storing programs and data, and network interface 21 10. Programming station 2100 also includes a user interface having a CRT display 4120 and a mouse input device 4125.

Processor 2010 executes programs 2015 stored in memory 2150, to generate test programs for electrical station 2130, vision station 2200, and x-ray station 2300 Processor 2010 sends the generated test programs to stations 2130, 2200, and 2300 through network interface 2110. Processor 2010 also generates an uncovered defect ("escape") list, allowing inspector 245 at manual inspection station 2400 to focus on possible defects not adequately covered by any of stations 2130, 2200, and 2300

Processor 2010 receives defect reports from manual diagnostic/repair station 2430

In the data structures shown throughout the drawings, dotted lines represent a reference, such as a pointer, between one element and another These references are not necessarily direct memory address pointers. Instead, more generally, each reference is a data entity, stored in association with one (referencing) element, that enables a processor to find a related (referenced) element. To physically address the referenced element, the processor may subject the reference to various translations or mappings.

Fig. 5 shows data structures in testing system 1 100, with solid lines representing a data flow between elements "Panel" database 31 10 includes a list of "designators" for board 100 and the electrical interconnection between designators A "panel" includes one or more circuit boards manufactured on a common substrate Panel database 31 10 may include X-Y location information for electrical or optical access to a particular component, and may include X-Y location information for the component itself.

Technique generation rules 3120 control whether a particular technique will be inserted into a program A "technique" is a type of instruction executable by a station Table 1 below illustrates the organization of rules 3120

In this application, a "designator" corresponds to the term "reference designator," a term commonly used to refer to a specific part on a specific printed circuit board type As will be apparent from the description below, however, a technique performed for a particular designator name tests circuit board structure in addition to the part associated with the designator name, as interconnection to the part are also tested

ELECTRICAL Shorts [condition set 1 ]

ELECTRICAL_Resistance [condition set 2]

ELECTRIC AL OpensXpress [condition set 3]

ELECTRICAL_Capacitance [condition set 4]

ELECTRICAL Inductance [condition set 5]

ELECTRICAL_Transistor [condition set 6]

ELECTRICAL_Diode [condition set 7]

OPTICAL_Wrong [condition set 8]

OPTICAL Damaged [condition set 9]

OPTICAL_Missing [condition set 10]

OPTICAL_Orientation [condition set 1 1]

OPTIC AL_Skew [condition set 12]

OPTICAL Solder Joint [condition set 13] OPTICAL_Theta [condition set 14]

XRAY_SolderJoint [condition set 15]

ELECTRICAL_OpensXpress [condition set 16]

OPTICAL Wrong [condition set 17]

ELECTRICAL_Orientation [condition set 18]

TABLE 1 Each row in Table 1 is a rule that controls whether a particular technique will be generated for a particular designator. In general, multiple rules may correspond to a single technique; a single technique may have a set of rules. The left column designates a particular technique to be performed on a particular station.

Electrical station 2130 executes the electrical techniques: ELECTRICAL Resistance, ELECTRICAL_OpensXpress, ELECTRICAL_Capacitance, ELECTRICAL nductance, ELECTRIC AL Transistor, and ELECTRIC AL Diode. Each of these electrical techniques includes an identification of a first pin on station 2130, through which station 2130 measures a current from the board 100 being tested. Each of these electrical techniques also includes identification of a second pin on station 2130, through which station 2130 supplies an electrical measurement signal. Thus, station 2130 measures an electrical characteristic associated with a particular designator. This characteristic may be the characteristic of a part associated with the designator.

ELECTRICAL_Shorts is a technique that takes an identifier for a group of nets on the circuit board. In the preferred system, panel database 31 10 comes with a default identifier called WHOLE_BOARD, which identifies all nets on the board. The ELECTRICAL Shorts technique performs an impedance test between nets to ensure that nets are not shorted together.

The ELECTRICAL Resistance, ELECTRICAL Capacitance, and ELECTRICAL Inductance techniques measure impedances using an AC signal source

The ELECTRICAL_Diode technique is a discrete diode test to detect the presence and proper orientation of a reversed biased PN junction.

The ELECTRICAL_Transitor technique performs the processing of two ELECTRICAL_Diode techniques to test the PN junctions between the base and collector and between the base and emitter. Alternatively, ELECTRICAL Transitor test may be a veta test. The ELECTRICAL_OpensXpress technique uses capacitive coupling to measure the capacitor formed by the lead frame of a device package and a test probe placed on top ofthe package. The package material acts as an insulator between the probe and the lead frame (Opens Xpress is a mark used by GenRad Ine to describe the type of test referred to here)

The ELECTRIC AL Orientation technique employs a probe placed on top ofthe package, sends a signal through the probe, and detects the respective signals at each lead of the device under test The device lead connected to the package exterior should have the larger signal, thereby indicating the orientation ofthe device

Optical station 2200 executes the optical techniques OPTICAL Wrong, OPTICAL_Damaged, OPTICAL_Missing, OPTICAL_Orientation, OPTICAL_Skew, OPTIC AL S older Joint, and OPTIC AL Theta Each of these optical techniques includes x- y coordinates specifying a portion ofthe optical image, of board 100, to be processed by station 2200 Each optical technique also includes image data for an image to be recognized in the specified portion, and a code specifying the type of processing to be performed For example, the OPTIC AL_Theta technique attempts to recognize the image of a certain structure, such as a resistor package, within the specified image portion, and measures the orientation ofthe package relative to a nominal axis In other words, each optical technique contains coordinates specifying a portion ofthe image of board 100 (a portion ofthe received radiation reflected from board 100), and contains image data corresponding to an image to be recognized.

The OPTICAL_Wrong technique performs an optical character recognition (OR) on the label printed on the device package

The OPTICAL Damaged, OPTICAL_Missing, OPTICAL_Orientation, OPTICAL Skew, and OPTICAL_Theta techniques each attempt to recognize the image of a package and detect the orientation and position ofthe package relative some nominal position

In other words, optical station 2200 operates by applying a wave from a wave source (lamps 2232), through a space between lamps 2232 and board 100, to board 100, optical station 2200 operates by applying electromagnetic radiation, in the form of ambient light and light from lamps 2232 to board 100 Optical recognizer 2236 receives some ofthe radiation (visible light) reflected from board 100 Optical station 2200 executes an optical technique by correlating image data, in the technique, with the technique-specified portion ofthe received radiation reflected from board 100.

X-ray station 2300 executes an x-ray technique: X-RAY_Solder Joint This x-ray technique includes x-y coordinates specifying a portion of an x-ray image, of board 100, to be processed by station 2300. This x-ray technique also includes image data for an image to be recognized in the specified portion, and a code specifying the type of processing to be performed. This x-ray technique attempts to recognize a specified structure, such as a pattern of solder corresponding to a well-formed solder connection for a certain type of package. In other words, the X-RAY_SolderJoint technique contains coordinates specifying a portion of the image of board 100 (a portion ofthe received radiation passed through board 100), and contains image data corresponding to an image to be recognized

In other words, station 2300 operates by applying radiation, using x-ray source 2332, to board 100. Station 2300 receives some ofthe applied radiation (x-rays) that passes through board 100, using detector 2334. Station 2300 executes the X-RAY_Solder Joint technique by correlating image data, in the technique, with the technique-specified portion of the received radiation passed through board 100.

The right column of Table 1 specifies the conditions under which the corresponding technique is inserted into a test program. Each condition set in the right column is essentially an expression for evaluation by program generator 5100 Some variables that may appear in a condition set are summarized below:

DPM (Defects Per Million) is equal to a sum of selected defect statistics associated with the designator being processed. The defect statistics associated with the designator include statistics having the same package type and board side as the designator, as described in connection with Fig. 10A et seq. below The selected defect statistics will be for those defects covered by the technique associated with the rule(see Table 5 below).

PACKAGE_TYPE is equal to the type of package ofthe part corresponding to the designator presently being processed. Possible values of PACKAGE TYPE include FLAT PACK, GRID-ARRAY, CYLINDER, VERTICAL SURFACE-MOUNT, LONG-FORM HORIZONTAL, IN-LINE, DIP 18, DIP 10, DIP 16, CC 156, DRLY-12, SOT23F, and LED2

PINS is equal to the number of interface contacts on the package ofthe part corresponding to the presently processed designator Depending on the type of package, an interface contact may be a pin, a lead, a pad, or a ball PITCH is equal to the pitch between pins on the package of the part corresponding to the presently processed designator

BOARD SIDE is equal to TOP if the part resides on the top ofthe board or BOTTOM if the package resides on the bottom of the board

DATASHEETJTYPE is equal to a certain field of an entry, in the datasheet library, corresponding to the presently processed designator, as shown in Table 7, below Some possible values of DATASHEETJTYPE include C, R, L, IC

For example, Table 2 shows [condition set 3] for the ELECTRIC AL OpensXpress technique:

(PIN _ COUNT > = 24) AND (BOARD _SIDE = TOP)

TABLE 2 In Table 2, PIN_ COUNT is equal to the number of pins in a package associated with a particular "designator," and BOARD SIDE is equal to TOP if the package resides on the top ofthe board or BOTTOM if the package resides on the bottom ofthe board A "designator" identifies a structure on a circuit board, as described in more detail below Table 3 below shows [condition set 14] for the OPTIC AL THETA technique (PACKAGE_TYPE= LONG FORM, AXIAL, 2) AND (BOARD_SIDE = TOP)

TABLE 3 In Table 3, PACKAGE TYPE is the name of an entry in package type library 61 10 Thus, generator 5100 will generate the techniques OPTIC AL Theta (C 2025), OPTICAL_Theta (C_2030), OPTICAL_Theta (R_2035), and OPTIC AL_Theta (R_2040), because the designators C 2025, C 2030, R 2035, and R 2040 each have an associated part that satisfies the conditions of Table 3.

Table 4 below shows [condition set 4] for the ELECTRICAL Capacitance technique (DATASHEETJTYPE = C) AND (DPM>750)

TABLE 4 In Table 4 , DPM (defects per million) represents defects statistics for the package type ofthe part associated with a particular designator To process this rule, program generator 5100 inserts the ELECTRIC AL Capacitance technique into test program 21 10 for any designator having both an entry in datasheet library 6015 for which the type field is C, and a package type and board side for which the sum of defects detectable by the ELECTRICAL_Capacitance technique occurs at a rate greater than 750 per million Evaluation ofthe DPM variable will be described below in more detail in connection with Table 8.

Processor 2010, and one ofthe programs 2015, act as program generator 5100. Program generator 5100 reads database 31 10 and rules 3120, and generates program 21 10 for optical station 2230, generates program 21 15 for electrical station 2130, and generates program 2120 for x-ray station 2300. Program generator 5100 conditionally generates a certain technique depending the corresponding condition set in rules 3120, and on the board description in database 31 10.

Defect-technique table 3 1 15 associates a technique with a set of defects, as shown in Table 5:

TECHNIQUE FAULT GENERIC DEFECT CERTAINTY

ELECTRICAL Shorts Short Etch Short 100%

Solder Short 100%

Mod Wire Misconnected 100%

ELECTRICAL Resistance Short Etch Short 100% Solder Short 100%

Value Wrong Component 100%

Tolerance Bad Component 100%

Open Missing Component 100% Open Track 100% Insufficient Solder 100% Solder Hole/Crack/Void 100%

Stance Short Etch Short 100% Solder Short 100%

Value Wrong Component 90%

Tolerance Bad Component 95%

Open Missing Component Open Track 100% Insufficient Solder 100% Solder Hole/Crack/Void 100%

ELECTRICAL Orientation Polarity Misoriented Component 80%

ELECTRICAL Inductance Short Etch Short 100% Solder Short 100%

Value Wrong Component 100%

Tolerance Bad Component 100%

ELECTRICAL Diode Value Wrong Component 100% Missing Component 100%

Tolerance Bad Component 100%

ELECTRICAL Transistor Value Wrong Component 100% Missing Component 100%

Tolerance Bad Component 100%

ELECTRICAL_OρenXpress OpenPin Insufficient Solder 100% Lifted Lead 100% Bent Pin 100% Open Track 100%

Open Missing Component 100%

Orientation Misoriented Component 100%

OPTICAL Wrong Wrong Component Wrong Component 100%

OPTICAL Damaged Damaged Board Damaged 100%

OPTICAL Missing Missing Missing Component 100%

OPTICAL_Orientation Orientation Misoriented Component 50%

OPTICAL Skew Offset Misoriented Component 100%

OPTICAL SolderJoint Bad Solder Bad Solder 100%

OPTICAL Theta Rotated Misoriented Component 100% XRAY SolderJoint Bad Solder Bad Solder 100%

TABLE 5

In Table 5, the left column designates a technique, the second column designates possible results, called "faults," the technique can generate, and the third column designates a set of generic defects associated with a particular fault. Thus, defect-technique table 31 15 relates a defect to a technique by way of a fault

In Table 5, the fourth column designates a certainty that the technique will detect a particular defect. This certainty may be displayed with a report of defect coverage for a particular designator. It is presently preferred that Table 5 be initialized with a certainty of 100% for all defects. Subsequently, analysis of process history, including defect data and the techniques that detected the defect, can cause a particular certainty to be revised downward

Program generator 5100 generates defect tables 51 10 for a plurality of designators in panel database 3110. The possible defects for a designator include problems with a particular part associated with the designator and problems with the connection ofthe part.

Program generator 5100, in response to the contents of table 3115, updates defect tables 51 10 to record how a technique, generated for a particular designator, relates to one or more defects.

Fig. 6 shows panel database 31 10 in more detail. Panel database 31 10 includes information for each designator including whether the part corresponding to the designator is on the top or bottom ofthe circuit board. In database 3110, each designator also has a list of possible defects, described in more detail below in connection with Fig. 7 In database 31 10, each designator also includes references for associating the designator with a part More specifically, each entry in panel database 31 10 includes a reference into package type library 6010, thereby identifying the package type of the part associated with the designator

Each entry in package type library 6010 may also include pin pitch information or coordinate information for the package leads, as show for the package name DIP 18 in Table 6 below:

Package Name: DIP 18

Description:

Origin Units Height Pitch

Center mils 0.2 100

Number of Leads: 18 Lead name LeadX LLiead Y

1 075 0

2 175 0

3 275 0

4 375 0

5 475 0

6 575 0

7 675 0

8 775 0

9 875 0

10 875 3

11 775 3

12 675 3

13 575 3

14 475 3

15 375 3

16 275 3

17 175 3

18 075 3

TABLE 6

Each entry in panel database 31 10 also includes a reference into datasheet library 6015, thereby identifying the circuit associated with the part Table 7 below shows the library entry for the SO datasheet

Datasheet Name SO

Description

Guard Type U

Datasheet Types IC

Number of Signals 14

Signal Name Enable

END] (pin 1)

Edge Flags Digital-Input-Chip Select

DATA[l] (pin 2)

Edge Flags Digital-Input

Q[l] (pin 3)

Edge Flags Digital-Output-Tristate EN[2] (pin 4)

Edge Flags^* Digital-Input-Chip Select

DATA[2] (pin 5)

Edge Flags: Digital-Input

Q[2] (pin 6)

Edge Flags: Digital-Output-Tristate

GND (pin 7)

Edge Flags: Power - Power Low

Q[3] (pin 8)

Edge Flags. Digital-Output-Tristate

DATA[3] (pin 9)

Edge Flags: Digital-Input

EN[3] (pin 10)

Edge Flags: Digital-Input-Chip Select

Q[4] (pin l l)

Edge Flags: Digital-Output-Tristate

DATA[4] (pin 12) Edge Flags^* Digital-Input

EN[4] (pin 13)

Edge Flags: Digital-Input-Chip Select

VCC (pin 14) Edge Flags: Power

TABLE 7 Thus, in the preferred system, a designator identifies a structure on board 100 The structure may include a part having a certain package type and circuit The structure may also include an electrical interconnection between the part and the board 100 For example, when station 2100 executes the technique ELECTRIC AL Resistance (R 2040), station 2100 measures the resistance between the two fixture pins connected to board 100 the resistance of a path including both resistor 2040 and circuit board wires between these fixture pins and resistor 2040

In Fig. 6, and in other figures and tables of this application, many data items and references have been omitted for clarity of explanation

Fig 7 shows an aspect of program generator 5100 and tables 51 10 in more detail Each dotted line in Fig 7 represents a double (bidirectional) reference Program generator 5100 writes double reference 7010 for relating the bad component defect for C_2030 to the ELECTRICAL Capacitance C 2030 technique in program 21 15 In other words, dotted line 7010 represents both a reference from the ELECTRIC AL Capacitance C_2030 technique to the bad component defect for C 2030, and a reference from the bad component defect for C 2030 to the ELECTRICAL Capacitance C 2030 technique

Program generator 5100 also writes double reference 7015 for relating the wrong component defect for C_2030 to the ELECTRICAL Capacitance C_2030 technique, thereby writing a relationship between a two defects and one ofthe techniques Program generator 5100 also writes double reference 7020 for relating the MISORIENTED COMPONENT defect for C_2030 to the OPTICAL Orientation C_2030 technique in program 2110, and writes double reference 7025 for relating the misoriented component defect for C_2030 to the ELECTRICAL Orientation (C 2030) technique in program 21 15, thereby writing a relationship between one defect and two techniques Similarly, generator 5100 writes relationships between other designators (not shown in Fig 7) and possible defects

To generate Tables 51 10, generator 5100 generates respective defect tables for each component, using the respective "possible defects" data from panel database 31 10 Subsequently, as generator 5100 generates techniques, generator 5100 reads Table 5 to determine when to write a reference in a certain defect table to a certain generated technique Along with the reference to a technique, generator 5100 also writes the corresponding certainty, read from Table 5, into table 51 10

Thus, tables 5110 store a relationship between a two defects and one ofthe techniques, and stores a relationship between one defect and two techniques Similarly, table 5110 writes relationships between other designators (not shown in Fig 7) and possible defects. In other words, the defects in Table 5 are essentially a first signal and the "possible defects" in panel database 3110 are essentially a second signal Table 5 stores, for each technique type, the first signal representing a defect type detectable by execution ofthe technique Panel database 31 10 stores the second signal representing possible defects board 100 Generator 5100 generates a plurality of instructions for testing of board 100, and generates, responsive to the first and second signals, a reference (a third signal) representing a possible defect detectable by execution of one the plurality of instructions

The possible defects data in panel database 3110 is a function ofthe part corresponding to the designator (a function ofthe package type and data sheet corresponding to the designator) The possible defect data is oriented by part because, although defect statistics are organized by package type, as described in more detail below, the possible defects for a part are a function of both package type and the circuit within the part For example, although both a resistor and a capacitor may have the package type LONG FORM AXIAL, 2, an electrolytic capacitor can be mounted on a board backwards, thereby having the misoriented component defect A resistor with this package type, however, cannot have the misoriented component defect

Fig 8 shows another data flow within testing section 1 100 Processor 2010, and another one ofthe programs 2015, act as program manager 61 15 After completion of program generation, program manager 61 15 reads defect table 2105 and compiles a report of a defect coverage for designator C_2030 This report allows the user to modify the technique generation rules 3120, using technique editor 5200, to ensure appropriate defect coverage for each designator

Generator 5100 sends a list of "escapes," defects that remain uncovered, to manual inspection station 2400

Fig. 9 shows a processing, performed by program generator 5100, to generate programs 2110, 21 15, and 2120 Program generator 5100 selects a first rule from technique rules 3120 (step 9010) Program generator 5100 then selects a first designator from panel database 3110 (step 9020) Generator 5100 then determines whether the conditions for the presently selected rule are satisfied for the presently selected designator (step 9030) If the conditions are satisfied, generator 5100 inserts a technique for the designator into one of programs 2110, 2115, or 2120 (step 9032) If there are designators remaining to be processed for the present rule (step 9035), generator 5100 selects the next designator (step 9040) and processing proceeds to step 9030 If there are no designators remaining to be processed for the present rule (step 9035), generator 5100 determines whether there are rules remaining to be processed (step 9050). If there are rules remaining to be processed, generator 5100 selects the next rule (step 9080) and processing proceeds to step 9020

In other words, disk memory 2105 and random access memory 2150 are each electronic memories that store rules 3120. Each rule 3120 corresponds to a respective technique type, and each rule 3120 may contain a variable (such as DPM, for example) Memories 2105 and 2150 also store panel database 31 10, datasheet library 6015, and package type library 6010. Package type library 6010 may have common pin count data for first and second parts, the first part having a first circuit configuration and the second part having a circuit configuration different from the first circuit configuration. For example, designator C_2025 and C_2030 correspond to different parts, as they have different entries in datasheet library 6015, but have a common entry in package type library 6010 The entry in package type library 6010 has pin count information for the package

Processor 2010 and one ofthe programs 2015 together act as program generator 5100. Program generator 5100 receives Panel database 31 10, which contains a description of a circuit assembly Program generator 5100 then generates, based on the database 3110, test program 21 10 for testing the circuit assembly by performing steps 9030 and 9032, a plurality of times for each rule

Steps 9030 and 9032 act to conditionally generate an instruction for test program 2110, depending on a value of a variable in one of the OPTICAL technique rules

Similarly, steps 9030 and 9032 act to conditionally generate an instruction for test program 2115, depending on a value of a variable in one ofthe ELECTRICAL technique rules. For example, steps 9030 and 9032 conditionally generate ELECTRICAL OpenXpress (a type of instruction) for a particular designator depending on whether the package associated with the designator has a pin count of greater than 24 (depending on a package configuration ofthe part associated with the designator) To determine the pin count, generator 5100 accesses a record, in package type library 6010, associated with the designator being processed

Figs. 10A, 10B, and 10C show another aspect of testing system 1 100 Over a period of time, program executor 10020, in electrical station 2130, tests a plurality of circuit boards 1 10. Circuit board 1 10 has a different collection of parts than circuit board 100, and has a different interconnection between parts than circuit board 100 Circuit board 1 10, however, has some package types in common with circuit board 100

Executor 10020 tests a circuit board by executing techniques in test program 21 10 When execution of a particular technique results in a fault, executor 10020 reads fault-defect map 10010 to translate the fault into list of site defects A site defect is text describing a problem with the circuit board. Executor 10020 then sends a defect report to data collection program 10035 The defect report includes the designator of the technique that produced the fault and one or more site defects corresponding to the fault For example, if, while testing board 78912345, execution of ELECTRIC AL_CAPACITANCE (CJ2030) results in the fault OPEN, executor 10020 sends the ASCII text "BOARD 78912345, C_2030, MISSING COMPONENT or OPEN TRACK or INSUFFICIENT SOLDER or SOLDER HOLE/CRACK/VOID. "

After program executor 10020 sends a defect report for a particular board, the board is sent to manual diagnostic/ repair station 2430, where an operator diagnoses the actual defect on the board. Manual diagnostic/ repair station 2430 then sends a defect confirmation report, for the board, to data collection program 10035. For example, station 2430 may send BOARD 78912345, C_2030, OPEN TRACK. Data collection program 10035 processes the report from station 2430 by translating the designator in the report into a package type, by accessing a data object for the designator in panel database 31 10, to obtain a reference into package type library 6010. By receiving such reports over time, data collection program 10035 compiles DPM (defects per million) data 10040, which records defect rates for respective package types. Table 8 below shows an organization of DPM data 10040

DIP 18-TOP-BAD COMPONENT 3 1 5

DIP 18-TOP-INSUFFICIENT SOLDER 1 1 1

DIP 18-TOP-LIFTED LEAD 5 18

DIP 18-TOP-MISSING COMPONENT 650

DIP 18-TOP-OPEN TRACK 897

DIP 18-BOTTOM-B AD COMPONENT 3 1 1

DIP 18-BOTTOM-INSUFFICIENT SOLDER 514

DIP 18-BOTTOM-LIFTED LEAD 3 12

DP 18-BOTTOM-MIS SING COMPONENT 897

DIP 18-BOTTOM-OPEN TRACK 457

ΓNLΓNE,DUAL, I 6-TOP-B AD COMPONENT 213

ΓNLINE,DUAL, 16-TOP-ΓNSUFFICIENT SOLDER 517

ΓNLΓNE,DUAL, 16-TOP-LIFTED LEAD 31 1

ΓNLΓNE,DUAL, I6-TOP-MISSΓNG COMPONENT 957

ΓNLΓNE,DUAL, 16-TOP-OPEN TRACK 1012 ΓNLΓNE,DUAL, I 6-BOTTOM-B AD COMPONENT 31

INLΓNE,DUAL, 16-BOTTOM-TNSUFFICIENT SOLDER 556

ΓNLΓNE.DUAL, 16-BOTTOM-LIFTED LEAD 427

ΓNLΓNE,DUAL, 16-BOTTOM-MISSING COMPONENT 312

LNLΓNE,DUAL, l 6-BOTTOM-OPEN TRACK 898

ΓNLΓNE,DUAL, 14-TOP-B AD COMPONENT 711

ΓNLINE,DUAL, l 4-TOP-ΓNSUFFICIENT SOLDER 657

ΓNLΓNE,DUAL, 14-TOP-LIFTED LEAD 112

ΓNLΓNE,DUAL, 14-TOP-MISSΓNG COMPONENT 131

ΓNLΓNE,DUAL, I4-TOP-OPEN TRACK 574

ΓNLΓNE,DUAL, l 4-BOTTOM-BAD COMPONENT 415

INLΓNΈ,DUAL, 14-BOTTOM-ΓNSUFFICIENT SOLDER 851

ΓNLΓNE,DUAL, 14-BOTTOM-LIFTED LEAD 73

ΓNLΓNE,DUAL, I4-BOTTOM-MISSΓNG COMPONENT 574

ΓNLΓNE,DUAL, 14-BOTTOM-OPEN TRACK 131

LONG FORM,AXIAL,2-TOP-BAD COMPONENT 815

LONG FORM,AXIAL,2-TOP-TNSUFFICIENT SOLDER 213

LONG FORM,AXIAL,2-TOP-MISSING COMPONENT 75

LONG FORM,AXIAL,2-TOP-OPEN TRACK 75

LONG FORM, AXIAL,2-TOP-BAD SOLDER 51 1

LONG FORM,AXIAL,2-BOTTOM-BAD COMPONENT 205

LONG FORM, AXIAL,2-BOTTOM-TNSUFFICIENT SOLDER 37

LONG FORM,AXIAL,2-BOTTOM-MISSING COMPONENT 307

LONG FORM,AXIAL,2-BOTTOM-OPEN TRACK 15

LONG FORM, AXIAL, 2-BOTTOM-B AD SOLDER 51 1

etc

Table DPM Following is an example ofthe calculation ofthe DPM variable for a rule for the ELECTRICAL Capacitance technique and the designator C 2069 Because designator C_2069 has a package type of LONG FORM,AXIAL,2 located on the bottom ofthe board, the last five statistics in Table 8 (205, 37, 307, 15, and 51 1) correspond to designator C_2069. Of these five statistics, only four are detectable by the ELECTRIC AL Capacitance technique (205,37,307, and 15), since the defect BAD SOLDER is not detectable by the ELECTRIC AL Capacitance technique Thus, the value of DPM for an ELECTRICAL Capacitance rule processing the designator C 2069 is 564 (the sum of 205, 37, 307, and 15) Because DPM data 10040 affects the triggering of technique generation rules that contain the variable DPM, as described above, program generator 5100 can generate a program to test board 100 using defect data generated by testing board 1 10.

Data collection program 10035 can be any program that receives test results and compiles defect data in an appropriate format. Similarly, although it is presently preferred that panel database 31 10 be an object orientated data structure, other structures, such as electrical CAD (computer aided design) data, may be employed.

Fig. 10B shows defect data processing performed by optical station 2200 Program executor 10120 executes techniques in program 2115 to receive and process a light image reflected from circuit board 1 10. When a technique generates a fault, program executor 10120 reads fault-defect map 101 10 to generate a defect report and send the defect report to data collection program 10035.

Fig. 10C shows defect data processing performed by x-ray station 2300 Program generator 10220 executes test program 2120 to receive x-rays passed through circuit board 110 and processed the received x rays. When execution of a technique in program 2120 generates a fault, program executor 10220 reads fault - defect map 10210 to generate a defect report and send the defect report to data collection program 10035.

In other words, the preferred system tests boards 1 10 (a plurality of first circuit assemblies), to generate DPM data 10040. Subsequently program generator 5100 receives panel database 3110 containing a description of board 100 (a second circuit assembly). Generator 5100 generates, based on database 31 10, program 21 15 (a first test program for testing the second circuit assembly), by performing the following steps a plurality of times for one ofthe electrical technique rules: writing a value in the DPM rule variable, using DPM data 10040; and conditionally generating a technique for program 21 15, depending on the value of DPM. Generator 5100 also generates, based on database 31 10, program 21 10 (a second test program for testing the second circuit assembly), by preforming the following steps a plurality of times for one ofthe optical technique rules: writing a value in the DPM rule variable, using DPM data 10040; and conditionally generating a technique for program 2110, depending on the value of DPM.

As described above, DPM data 10040 includes a plurality of statistics, each ofthe boards 100 (second plurality of circuit assemblies) includes a plurality designators (structures). The step of generating, in the previous paragraph, includes step 9040 (selecting one ofthe designators), and selecting, from DPM data 10040, at least one statistic corresponding to the package type ofthe selected designator The writing step, in the previous paragraph, includes the step of writing a value into the DPM variable based on the selected statistic

Thus, the preferred system coordinates test program generation, for multiple stations, to promote the most cost effective techniques for each defect on a circuit assembly The preferred system thus optimizes defect coverage while minimizing programming costs

Fig 11 shows an organization of fault - defect map 10010 in electrical station 2130 When technique execution generates a fault, program executor 10020 locates an entry for the fault in list 11 100. The entry for the fault contains a reference into generic defect list 1 1200 Generic defect list 11200 contains references into site defect list 1 1300

Fault-defect map 10010 is the product of processing performed on programming station 2100 More specifically, editor 5200 has a screen interface that allows the user to create the data in site defect list 1 1300 Editor 5200 also allows the user to adjust the references in generic defect list 1 1200, to complete the mapping of faults to site defects

The combination of lists 1 1100, 1 1200, and 1 1300 is essentially a two layer mapping of faults to site defects This two layer mapping allows the user to customize the site defect report to a particular site (factory) without having to define the relatively complicated mapping of faults to defect types In other words, the mapping of generic defects to site defects will tend to be 1-to-l The more complicated mapping of faults to generic defects can be provided by the manufacturer of programming station 2100

Other data organizations shown in this application are also the result of processing performed on station 2100 In general, the station provides the user with screen interfaces that allow the user to create data structures and to conveniently make associations between data structures. For example, station 2100 provides a screen allowing the user to enter new designator names into the panel database Subsequently, the station presents a screen displaying a list of designators, a list of package types, and a series of buttons allowing the user to associate a designator with a package type

In summary, electrical station 2130 executes, at a first location, test program 21 15 by applying an electrical current to one ofthe circuit boards 100 and receiving an electrical current from the circuit board 100 Optical station 2200 executes, at a second location different from the first location, test program 21 10 by applying light to board 100 and receiving some ofthe applied light reflected from board 100, and x-ray station 2300 executes, at a third location different from the first and second locations, test program 2120 by applying x-rays to circuit board 100 and receiving some ofthe x-rays that have passed through circuit board 100.

Thus the preferred system efficiently generates test programs by conditionally generating a test instruction for a part depending on the part package

Additional advantages and modifications will readily occur to those skilled in the art The invention in its broader aspects is therefore not limited to the specific details, representative apparatus, and illustrative examples shown and described Accordingly, departures may be made from such details without departing from the spirit or the scope of Applicants' general inventive concept.

Claims

1. In a system including a circuit assembly having a plurality parts and means for executing an instruction to test the assembly, a method comprising the steps of conditionally generating a first type of instruction for a first part in the plurality of parts, depending on a package configuration of the first part; and conditionally generating the first type of instruction for a second part in the plurality of parts, depending on a package configuration ofthe second part.

2. The method of claim 1 wherein the first and second parts each have a corresponding number of interface contacts, and wherein each generating step includes the step of comparing the corresponding contact count to a count associated with the instruction

3. The method of claim 1 wherein the system includes means for storing a record having common contact count data for the first and second parts, and the first part has a first circuit configuration and the second part includes a circuit configuration different from the first circuit configuration, and wherein each generating step includes the step of accessing the record; reading the common contact count data from the record; and comparing a number, corresponding to the common contact count data, to a count associated with the instruction.

4. The method of claim 1 wherein the first and second parts each have a corresponding pitch between interface contacts, and wherein each generating step includes the step of comparing the corresponding contact pitch to a pitch associated with the instruction

5. The method of claim 1 wherein the system includes means for storing a record having common pitch data for the first and second parts, and the first part has a first circuit configuration and the second part includes a circuit configuration different from the first circuit configuration, and wherein each generating step includes the step of accessing the record; reading the common pitch data from the record; and comparing a number, corresponding to the common pitch data, to a pitch associated with the instruction.

6. The method of claim 1 wherein some of the plurality of parts have a corresponding package name, and wherein each generating step includes the step of comparing the corresponding package name to a package name associated with the instruction.

7. A method of generating a test program to test an assembly, the assembly including a plurality of parts, each part including a respective circuit and a respective package configuration, the package configuration including a certain number and orientation of electrical contacts for interfacing to the assembly, the method comprising the step, performed for each part, of: generating a portion of the test program corresponding to the part, the content ofthe program portion being dependent on the contact configuration ofthe part, the content ofthe portion being independent ofthe circuit ofthe part.

8. A system for generating a test for a circuit assembly having a plurality parts, the system comprising: means for storing a plurality of rules each corresponding to a respective instruction type, each rule capable of containing a rule variable; and means for performing the following steps for a first one ofthe rules and for a first one ofthe parts: evaluating the rule variable by determining a package configuration ofthe part, to produce an evaluation result, and conditionally generating an instruction for execution at a first location, depending on the evaluation result

9. The system of claim 8 further comprising means for performing the following steps for a second one ofthe rules and for a first one ofthe parts evaluating the rule variable by determining a package configuration of the part, to produce a second evaluation result, and conditionally generating an instruction for execution at a second location different from the first location, depending on the second evaluation result.