WO1997016854A1 - Semiconductor component with prismatic channel area - Google Patents

Semiconductor component with prismatic channel area Download PDF

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Publication number
WO1997016854A1
WO1997016854A1 PCT/EP1996/004755 EP9604755W WO9716854A1 WO 1997016854 A1 WO1997016854 A1 WO 1997016854A1 EP 9604755 W EP9604755 W EP 9604755W WO 9716854 A1 WO9716854 A1 WO 9716854A1
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WIPO (PCT)
Prior art keywords
semiconductor component
component according
gate
prism
channel region
Prior art date
Application number
PCT/EP1996/004755
Other languages
German (de)
French (fr)
Inventor
Jörg Gondermann
Hartmut Roskos
Thomas RÖWER
Heinrich Kurz
Bernd Spangenberg
Original Assignee
Amo Gmbh
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Publication date
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Publication of WO1997016854A1 publication Critical patent/WO1997016854A1/en

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H01L29/7853—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET the body having a non-rectangular crossection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66787—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel
    • H01L29/66795—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a gate at the side of the channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0256—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by the material
    • H01L31/0264—Inorganic materials
    • H01L31/028—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System
    • H01L31/0288—Inorganic materials including, apart from doping material or other impurities, only elements of Group IV of the Periodic System characterised by the doping material
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/0248—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies
    • H01L31/0352—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions
    • H01L31/035272—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by their semiconductor bodies characterised by their shape or by the shapes, relative sizes or disposition of the semiconductor regions characterised by at least one potential jump barrier or surface barrier
    • H01L31/03529—Shape of the potential jump barrier or surface barrier

Definitions

  • the invention relates to a semiconductor component in planar technology consisting of a substrate, in particular a silicon substrate, and insulated connection regions formed thereon and spaced apart from one another, between which an electrically conductive channel region is formed, insulated from the connection regions, and a method for its production and Uses of the method for the production of different semiconductor components.
  • Such a component or a method for its production is known in practice. Such a method is used in the manufacture of integrated circuits (ICs) in which many millions of transistors are accommodated on a chip area of less than 1 cm 2 . Such ICs are used, among other things, in modern computers, in the processor area and in the memory area.
  • MOS metal oxide semiconductor
  • MOS field-effect transistors produced by means of the so-called planar technology are formed in that surface areas for the source, drain and gate connections of the field-effect transistor are formed on a doped silicon substrate using a mask etching technique. The surface areas are characterized by different conductivities and are separated by insulating intermediate areas. It is spatially below the between source and Formed drain regions and from these gate region isolated by the gate oxide, a channel region is formed, through which the charge carriers flow controlled by the gate voltage.
  • Silicon MOS field effect transistors are the basic elements of the so-called VLSI / CMOS technology (very large-scale integration / complementary metal oxide semiconductor). As miniaturization progresses, that is, with an increasingly higher density of MOSFET components on a single chip, undesirable so-called short-channel effects increasingly occur, in particular when the gate length falls below 1 ⁇ m. These short-channel effects can lead to higher leakage currents in the sub-threshold voltage and saturation range, as well as to a limitation of the gain that can be achieved and to faster component aging.
  • the invention is based on the object of further developing a component or a method of the type mentioned at the outset such that further integration can be achieved without the electrical characteristics deteriorating compared to those of the known components.
  • the three-dimensionally formed channel region extending between the end regions has the shape of a prism, the cross-sectional area of which is at least three corners has, wherein one of the prism edge surfaces is arranged parallel to the substrate plane.
  • this object is achieved in that the channel region is three-dimensionally prismatic.
  • the invention is characterized in that, in contrast to conventional MOSFET planar technology, the current is routed between the connection areas in a spatially formed current-conducting path in the form of a prism.
  • the cross-sectional geometry of the prism leads to a field increase effect occurring in the respective corner areas of the prism, i.e. that when an electrical voltage is applied to the gate connection, a high electrical field is built up there, which effectively increases the volume of the conductive path under the gate connection. This ensures that a local increase in current density is achieved compared to conventional geometric dimensions.
  • a preferred embodiment of the invention provides that the substrate has a buried insulation layer and that one of the prism edge surfaces is arranged parallel to the buried insulation layer.
  • the buried insulation layer can either consist of silicon dioxide or silicon nitride or a highly doped barrier layer.
  • a further advantageous embodiment of the invention provides that at least one of the prism edge surfaces corresponds to a crystallographically marked surface of the semiconductor material. This results in a suitable possibility of manufacturing the prismatic channel region by means of wet etching technology.
  • the simplest variant of the design of the channel area according to the invention includes that the prism is a triangular prism. The base area of the prism thus formed is parallel to the substrate plane or - in the case of a component with a buried insulation layer - at the height of this insulation layer.
  • a special embodiment provides that when the active layer is executed above the buried insulation layer on the basis of group IV semiconductor material or in particular on Si material, the prism edge surfaces, ie in the special case the triangular surfaces, the crystallographic (100) or (111) faces of the silicon material. This results in a self-adjusting etching process.
  • a field-effect transistor is possible as a semiconductor component, its connection areas are designed as source or drain areas and between which there is a gate area, the electrically conductive prismatic channel being arranged isolated from and adjacent to the gate area. At least two of the prism edge surfaces (in the triangular prism exactly two edge surfaces) of the channel region are coated with an insulating gate oxide on which the gate region, in particular made of conductive polysilicon, is formed.
  • the gate contact can also be made from highly conductive silicide or from metal, in particular aluminum.
  • the invention is characterized in that the aids of the known planar technology can be used.
  • the aids of the known planar technology can be used.
  • the etching rate is direction-dependent (anisotropic), that the desired prismatic, in particular triangular, structure is created.
  • the side surfaces of the triangular channel region which are created in the structuring according to the invention are particularly suitable for passivation with a gate oxide, in particular silicon oxide, as a result of which the reliability of the component is increased.
  • the gate oxide is preferably formed by thermal oxidation.
  • a polysilicon gate is produced, in which polysilicon is first deposited over the entire surface and then the finger-shaped gate region is structured in a dry chemical manner.
  • the gate region serves as channel masking in the subsequent doping / implantation step, this also taking place as a self-adjusting process.
  • the contacts for source, drain and gate connections are lithographed, structured and alloyed.
  • the source and drain regions of the component can be formed in a conventional manner as flat mesa regions on the substrate.
  • a special embodiment of the invention provides that the manufacturing process takes place starting from a wafer consisting of a silicon substrate with an oxide layer hidden under the silicon surface.
  • Such wafers are inexpensively available as commercially available materials, preferably SIMOX or BESOI wafers can be used as starting wafers.
  • SIMOX or BESOI wafers can be used as starting wafers.
  • BESOI output wafer high switching speeds can be achieved.
  • the possible fields of application for the component according to the invention extend from the classic MOS capacitors, diodes and MOS transistors to special applications, such as complex logic operators using multiple gate structures and quantum effects, to optical components.
  • Fig. 1 is a perspective view of the basic structure of a conventional MOSFET component
  • FIG. 2a shows a plan view of the basic structure of a component according to the exemplary embodiment of the invention
  • FIG. 2c shows a representation of FIG. 2b supplemented by the gate area
  • FIGS. 2b, 2c shows a detail of the channel area according to FIGS. 2b, 2c in a perspective schematic representation
  • FIG. 3 shows the structure of an output wafer for producing a component in accordance with the exemplary embodiment of the invention
  • Fig. 4 is a schematic diagram for explaining the
  • Fig. 6 shows a transmission characteristic of the component and the characteristic of the transistor slope
  • N-channel MOSFET which consists of a p-doped substrate region 1, on the surface of which by means of appropriate mask etching technology source, gate and drain regions of the field effect transistor are trained.
  • the regions extend along the surface of the substrate 1 and each have a rectangular cross-sectional structure.
  • N contacts extend into the substrate 1 and enclose between them a channel region which is arranged vertically below the gate region and insulated from it by a gate oxide.
  • the voltage U GS present between gate and source allows the electrical current flowing in the channel to be controlled between source and drain in the sense of a controllable electrical resistance.
  • FIGS. 2a to 2d show an NMOS transistor produced in accordance with the exemplary embodiment of the invention in a basic illustration.
  • a commercially available wafer with a buried oxide layer is used as the starting material for the realization of the NMOS transistor according to the exemplary embodiment,
  • a BESOI or SIMOX wafer is used, the basic structure of which is shown in FIG. 3.
  • This consists of a p- or n-doped silicon substrate 1 with a thickness of about 700 ⁇ m, an SiO 2 layer 2 thereon with a thickness of about 500 nm, on the top of which a p- or n-doped silicon layer 3 is formed, the thickness of which is approximately 700 nm.
  • the Si0 2 layer in such a wafer is also called a buried insulation layer.
  • the layer formed on the upper side thereof is referred to as "active layer" 3.
  • Fig. 2a shows the basic structure of the component in plan view. Between the connection areas A, which will later serve as drain (D) and source (S) contacts, a channel area (K) is formed as their electrically conductive connection. This is partially covered by a gate region (G) which is electrically insulated from it.
  • the channel region has the shape of a triangular prism lying on the insulation layer (FIG. 2b). It has a cross-sectional area in the form of an acute-angled triangle, the triangular edge lying opposite the acute angle lying parallel to the substrate plane.
  • the triangular channel region K is produced by anisotropic wet chemical etching.
  • a gate oxide layer 4 is applied to the crystallographically marked side surfaces of the triangular prismatic channel region K, for example by thermal oxidation (FIG. 2c).
  • FIG. 2d shows the perspective representation belonging to FIG. 2c, the substrate or the buried insulation layer being omitted.
  • FIGS. 2a-2c essentially relates to the gate area of an NMOS transistor, the manufacturing process of which proceeds according to the following steps:
  • the mesa regions for the source and drain connections and the electrically conductive triangular-prism-shaped channel K (FIG. 2) connecting the two regions are realized by suitable masking and wet chemical structuring. Otherwise, the source and drain are electrically isolated from one another.
  • a polysilicon gate is produced in the next step. For this purpose, first of all, polysilicon is deposited over the entire surface, the gate finger structure is lithographed and then structured with dry chemistry. In the subsequent doping / implantation step, the gate area serves as channel masking (self-adjusting process).
  • the contacts are lithographed, structured and alloyed.
  • the electrical output characteristic curve of an NMOS transistor manufactured according to the embodiment shown above is shown in FIG. 5.
  • This shows the drain-source current I ds as a function of the drain-source voltage (U ds ) as a function of the gate voltage U GS .
  • the measured output characteristics show that Despite the reduced geometric lateral dimensions of the channel region, electrical behavior comparable to that of conventional planar technology is achieved, ie a high drain-source current flows.
  • the described production method is characterized by the fact that the sequence of steps is compatible with the standard MOS technology.
  • the production process described in detail below begins with the production of the mesa structure for the drain and source regions, their insulation from one another and the production of the “faceted silicon web” as a channel region (FIG. 2).
  • the usual anisotropic structuring methods of Si semiconductor technology are used.
  • BESOI wafers consist of a sandwich structure that contains a 500 nm thick hidden SiO.layer, which is provided with a 700 nm thick active Si top layer, which is p-doped (boron, 5 * 10 15 cm "3 ).
  • a 100 nm thick Si 3 N 4 layer is deposited on the surface of the BESOI wafer using the LPCVD (low pressure chemical vapor deposition) method.
  • the component layout is then exposed by means of electron beam lithography at a voltage of 35 KV using a PMMA 950K e-beam varnish with a thickness of 200 nm.
  • the wafer Due to the requirements of the anisotropic wet chemical etching process, the wafer must be aligned precisely before exposure.
  • the etching process is carried out dry-chemically by means of reactive Ion etching of the Si 3 N 4 layer by anisotropic means using CHF 3 / O-.
  • the structured Si 3 N 4 layer forms the mask for the subsequent wet etching of the active Si cover layer with a dilute KOH solution.
  • the etching rate within the Si layer depends on the direction. In the direction of the (100) crystal direction, the etching process in KOH takes place three hundred times faster than in the (111) crystal direction. As a result, the process is completely self-adjusting, namely it ends automatically when the (111) plane or the hidden oxide layer of the BESOI wafer is reached. This enables a very sharp triangular cross section to be achieved. The remaining width of the tip of the triangle thus formed is only about 50 nm.
  • the Si 3 N 2 mask is selectively removed using H 3 P0 4 .
  • a 11 nm thick gate oxide layer is waxed up at 1050 ° C. by means of dry thermal oxidation. The tip of the channel area is rounded slightly.
  • the gate oxide layer is then covered with a 300 nm thick polysilicon layer using LPCVD at 750 ° C.
  • the gate area itself is defined by a second electron beam lithography step. After exposure and development of the coating, titanium is evaporated onto the surface. A lift-off process leads to the formation of a metallic mask for the subsequent drying etching step of the polysilicon layer, which is realized by an SF 6 RIE process.
  • arsenic is implanted at an acceleration voltage of 40 KV with a dosing rate of 5 * 10 15 cm "2.
  • the channel surface is masked with the polysilicon gate, whereby the In order to prevent arsenic from diffusing out in the following temperature and activation step, SiO 2 is deposited using the PECVD method at a temperature of 300 ° C.
  • the temperature of the sample for the purpose of recrystallization and the activation of the dopant Arsenic is run simultaneously at 900 ° C.
  • connection contacts are defined by means of electron beam lithography.
  • 20 nm aluminum and 200 nm gold are evaporated over the entire surface and selectively removed except for the contact areas by a further lift-off process.
  • the contacts are alloyed at 330 ° C.
  • Geometric channel gate lengths L GB0 between 0.8 ⁇ m and 2 ⁇ m were realized by means of the manufacturing method described above.
  • the geometric gate width W geo represents the (III) edge length of the triangular channel region.
  • the height of the triangle is 700 nm and the angle of the side walls is 54.7 ° in each case. This leads to a value of W geo of 1.7 ⁇ m.
  • the current-voltage characteristic of the NMOSFET components produced in this way is comparable to that of planar elements.
  • the output currents reach values of approximately 400 ⁇ A at an operating voltage of 5 V.
  • FIG. 6 shows the transfer characteristic of the component at a drain-source voltage of 3.5 V.
  • the saturation slope g m of the transistor structure reaches values above 200 ⁇ S.
  • the poly-silicon gate covers the triangular-prism-shaped silicon channel region, which is isolated by the gate oxide, and a voltage U GS is applied between the gate and source, an inversion layer is generated in the region of the prism surface, induced by the electric fields. This forms a conductive channel between the source and drain along the edge surfaces of the triangle. At the sharp edges of the triangle, in particular in the area of the tip, the strength of the inhomogeneous electric field is much higher than with planar components. Because the electron concentration is proportional to the electric field, the conductive channel within the three-dimensionally formed silicon path can be regarded as "more effective" compared to planar components.
  • This effect illustrated by the exemplary embodiment for a component with a triangular prism, can in principle also be achieved with prism-shaped channel regions which generally have a cross section in the form of an n-corner (n _> 3). It is essential that there is an edge area on which a correspondingly inhomogeneous electrical field structure is created.

Abstract

The invention concerns a semiconductor component and a method of manufacturing the same in planar technology, the component comprising a substrate (1), in particular a silicon substrate, and formed thereon mutually spaced isolated connection areas (A), between which an electrically conductive channel area (K) is formed such that it is isolated from these connection areas (A). According to the invention, in order to permit further integration without impairing the electrical parameters with respect to components manufactured in a conventional manner, the three-dimensional channel area (K) formed between the connection areas (A) is prismatic and its cross-sectional area has at least three corners. One of the lateral surfaces of the prism is disposed parallel to the substrate plane.

Description

Halbleiter-Bauelement mit prismenförmigem KanalbereichSemiconductor component with prism-shaped channel area
Die Erfindung betrifft ein Halbleiter-Bauelement in Planartechnologie bestehend auε einem Substrat, insbesondere einem Silizium-Substrat, und darauf ausgebildeten zueinander beabstandeten isolierten Anschlußbereichen, zwischen denen, isoliert zu den Anschlußbereichen, ein elektrisch leitfähiger Kanalbereich ausgebildet ist, sowie ein Verfahren zu seiner Herstellung und Verwendungen des Verfahrens zur Herstellung von unterschiedlichen Halbleiterbauelementen.The invention relates to a semiconductor component in planar technology consisting of a substrate, in particular a silicon substrate, and insulated connection regions formed thereon and spaced apart from one another, between which an electrically conductive channel region is formed, insulated from the connection regions, and a method for its production and Uses of the method for the production of different semiconductor components.
Aus der Praxis ist ein solches Bauelement bzw. ein Verfahren zu seiner Herstellung bekannt. Ein solches Verfahren wird eingesetzt bei der Herstellung von integrierten Schaltungen (IC's), bei denen viele Millionen Transistoren auf einer Chip-Fläche von weniger als 1 cm2 untergebracht sind. Solche IC's werden unter anderem in modernen Computern, im Prozessorbereich sowie im Speicherbereich eingesetzt. Die bekannte MOS-(Metall- Oxid-Semiconductor) -Technologie eignet sich dabei aufgrund der Eigenschaften des als Ausgangsmaterial verwendeten Siliziums besonders. Mittels der sog. Planartechnologie hergestellte MOS-Feldeffekt- Transistoren werden dadurch gebildet, daß auf einem dotierten Silizium-Substrat Flächenbereiche für die Anschlüsse Source, Drain und Gate des Feldeffekt- Transistors durch eine Maskenätztechnik ausgebildet werden. Die Flächenbereiche zeichnen sich durch unterschiedliche Leitfähigkeiten aus und sind durch isolierende Zwischenbereiche voneinander getrennt. Dabei wird räumlich unterhalb des zwischen Source- und Drainbereichen ausgebildeten und von diesen durch das Gateoxid isolierten Gatebereichs ein Kanalbereich ausgebildet, durch den die Ladungsträger von der Gatespannung gesteuert fließen.Such a component or a method for its production is known in practice. Such a method is used in the manufacture of integrated circuits (ICs) in which many millions of transistors are accommodated on a chip area of less than 1 cm 2 . Such ICs are used, among other things, in modern computers, in the processor area and in the memory area. The known MOS (metal oxide semiconductor) technology is particularly suitable because of the properties of the silicon used as the starting material. MOS field-effect transistors produced by means of the so-called planar technology are formed in that surface areas for the source, drain and gate connections of the field-effect transistor are formed on a doped silicon substrate using a mask etching technique. The surface areas are characterized by different conductivities and are separated by insulating intermediate areas. It is spatially below the between source and Formed drain regions and from these gate region isolated by the gate oxide, a channel region is formed, through which the charge carriers flow controlled by the gate voltage.
Silizium MOS-Feldeffekt-Transistoren sind die Grundelemente der sog. VLSI/CMOS-Technologie (very-large- scale-Integration/ Complementary-Metal-Oxid- Semiconductor) . Mit fortschreitender Miniaturisierung, also mit zunehmend höherer Dichte von MOSFET Bauelementen auf einem einzelnen Chip, treten zunehmend unerwünschte sog. Kurzkanaleffekte auf, insbesondere bei Unterschreitung einer Gatelänge von 1 μm. Diese Kurzkanaleffekte können zu höheren Leckströmen sowohl im Unterschwellspannungs- und Sättigungsbereich, sowie zu einer Begrenzung der erreichbaren Verstärkung und zu einer schnelleren Bauelementealterung führen.Silicon MOS field effect transistors are the basic elements of the so-called VLSI / CMOS technology (very large-scale integration / complementary metal oxide semiconductor). As miniaturization progresses, that is, with an increasingly higher density of MOSFET components on a single chip, undesirable so-called short-channel effects increasingly occur, in particular when the gate length falls below 1 μm. These short-channel effects can lead to higher leakage currents in the sub-threshold voltage and saturation range, as well as to a limitation of the gain that can be achieved and to faster component aging.
Es ist bekannt, die Betriebsspannung zum Zwecke der Miniaturisierung abzusenken, um den Energieverbrauch zu reduzieren. Hierdurch wird aber die Störsicherheit gegenüber Potentialfluktuationen, z.B. dem thermischem Rauschen, herabgesetzt.It is known to lower the operating voltage for the purpose of miniaturization in order to reduce energy consumption. However, this improves the immunity to interference from potential fluctuations, e.g. thermal noise.
Der Erfindung liegt die Aufgabe zugrunde, ein Bauelement bzw. ein Verfahren der eingangs genannten Art dahingehend weiterzuentwickeln, daß eine weitere Integration erreichbar ist, ohne daß die elektrischen Kennwerte gegenüber denen der bekannten Bauelemente verschlechtert sind.The invention is based on the object of further developing a component or a method of the type mentioned at the outset such that further integration can be achieved without the electrical characteristics deteriorating compared to those of the known components.
Diese Aufgabe wird bei einem Bauelement der eingangs genannten Art dadurch gelöst, daß der sich zwischen den Abschlußbereichen erstreckende dreidimensional ausgebildete Kanalbereich die Form eines Prismas aufweist, dessen Querschnittsflache mindestens drei Ecken aufweist, wobei eine der Prismenrandflachen parallel zur Substratebene angeordnet ist.This object is achieved in the case of a component of the type mentioned at the outset in that the three-dimensionally formed channel region extending between the end regions has the shape of a prism, the cross-sectional area of which is at least three corners has, wherein one of the prism edge surfaces is arranged parallel to the substrate plane.
Bei einem Verfahren der eingangs genannten Art wird diese Aufgabe dadurch gelöst, daß der Kanalbereich dreidimensional prismenförmig ausgebildet wird.In the case of a method of the type mentioned at the outset, this object is achieved in that the channel region is three-dimensionally prismatic.
Die Erfindung zeichnet sich dadurch aus, daß im Unterschied zur herkömmlichen MOSFET Planartechnologie die Stromführung zwischen den Anschlußbereichen in einem räumlich ausgebildeten stromleitenden Pfad in der Form eines Prismas erfolgt. Die Querschnittsgeometrie des Prismas führt dazu, daß in den jeweiligen Eckbereichen des Prismas ein Feldüberhöhungseffekt auftritt, d.h., daß beim Anlegen einer elektrischen Spannung an den Gateanschluß dort ein hohes elektrisches Feld aufgebaut wird, welches effektiv daε Volumen des leitfähigen Pfades unter dem Gateanschluß erhöht. Hierdurch wird erreicht, daß gegenüber herkömmlichen geometrischen Abmessungen eine lokale Zunahme der Stromdichte erzielt wird.The invention is characterized in that, in contrast to conventional MOSFET planar technology, the current is routed between the connection areas in a spatially formed current-conducting path in the form of a prism. The cross-sectional geometry of the prism leads to a field increase effect occurring in the respective corner areas of the prism, i.e. that when an electrical voltage is applied to the gate connection, a high electrical field is built up there, which effectively increases the volume of the conductive path under the gate connection. This ensures that a local increase in current density is achieved compared to conventional geometric dimensions.
Eine bevorzugte Ausführungεform der Erfindung sieht vor, daß das Substrat eine vergrabene Iεolationsschicht aufweist, und daß eine der Prismenrandflachen parallel zur vergrabenen Isolationsεchicht angeordnet ist. Die vergrabene Isolationsschicht kann dabei entweder aus Silizium-Dioxid oder aus Silizium-Nitrid oder aus einer hochdotierten Sperrschicht bestehen.A preferred embodiment of the invention provides that the substrate has a buried insulation layer and that one of the prism edge surfaces is arranged parallel to the buried insulation layer. The buried insulation layer can either consist of silicon dioxide or silicon nitride or a highly doped barrier layer.
Eine weitere vorteilhafte Ausgestaltung der Erfindung sieht vor, daß mindestenε eine der Priεmenrandflachen einer kriεtallographisch ausgezeichneten Fläche des Halbleitermaterials entspricht. Hierdurch ergibt εich eine geeignete Herεtellungεmöglichkeit des priεmenförmigen Kanalbereichs mittels Naß-Ätztechnik. Die bevorzugte und zugleich einfachste Variante der Gestaltung des Kanalbereichs gemäß der Erfindung beinhaltet, daß das Prisma ein Dreiecksprisma ist. Dabei liegt die Grundfläche des so gebildeten Prismas parallel zur Substratebene bzw. - bei einem Bauelement mit einer vergrabenen Isolationsschicht in der Höhe dieser Isolationεschicht. Eine besondere Ausgestaltung sieht dabei vor, daß bei einer Ausführung der aktiven Schicht oberhalb der vergrabenen Isolationsschicht auf der Basis von Gruppe IV Halbleitermaterial bzw. insbesondere auf Si-Material, daß die Prismenrandflachen, d.h. im besonderen Fall die Dreiecksflächen, den kristallographischen (100)- bzw. (111) -Flächen des Silizium-Materials entsprechen. Hierdurch ergibt sich ein selbεtjuεtierender Ätzprozeß.A further advantageous embodiment of the invention provides that at least one of the prism edge surfaces corresponds to a crystallographically marked surface of the semiconductor material. This results in a suitable possibility of manufacturing the prismatic channel region by means of wet etching technology. The preferred and at the same time the simplest variant of the design of the channel area according to the invention includes that the prism is a triangular prism. The base area of the prism thus formed is parallel to the substrate plane or - in the case of a component with a buried insulation layer - at the height of this insulation layer. A special embodiment provides that when the active layer is executed above the buried insulation layer on the basis of group IV semiconductor material or in particular on Si material, the prism edge surfaces, ie in the special case the triangular surfaces, the crystallographic (100) or (111) faces of the silicon material. This results in a self-adjusting etching process.
Als Halbleiter-Bauelement kommt insbesondere ein Feldeffekt-Transiεtor in Frage, deεsen Anschlußbereiche als Source bzw. Drain-Bereiche ausgebildet sind und zwischen denen ein Gatebereich liegt, wobei isoliert vom und benachbart zum Gatebereich der elektrisch leitfähige priεmenförmige Kanal angeordnet iεt. Mindeεtenε zwei der Priεmenrandflachen (beim dreieckförmigen Priεma genau zwei Randflächen) deε Kanalbereichε εind mit einem isolierenden Gateoxid beschichtet, auf dem der Gatebereich, insbesondere aus leitfähigem Polysilizium, ausgebildet ist. Alternativ dazu kann der Gatekontakt auch aus gut leitendem Silizid oder aus Metall, insbesondere Aluminium, hergestellt sein.In particular, a field-effect transistor is possible as a semiconductor component, its connection areas are designed as source or drain areas and between which there is a gate area, the electrically conductive prismatic channel being arranged isolated from and adjacent to the gate area. At least two of the prism edge surfaces (in the triangular prism exactly two edge surfaces) of the channel region are coated with an insulating gate oxide on which the gate region, in particular made of conductive polysilicon, is formed. Alternatively, the gate contact can also be made from highly conductive silicide or from metal, in particular aluminum.
Herstellungstechnisch zeichnet sich die Erfindung dadurch aus, daß die Hilfsmittel der bekannten Planartechnologie angewendet werden können. Anstelle des herkömmlichen Ätzvorganges zur Herεtellung eines (planaren) Gatebereichs erfolgt eine speziell angepaßte Ätzung, bei der die Ätzrate derart richtungsabhängig (anisotrop) ist, daß die gewünεchte prismenförmige, inεbesondere dreieckförmige, Struktur entsteht.In terms of production technology, the invention is characterized in that the aids of the known planar technology can be used. Instead of the conventional etching process for producing a (planar) gate region, there is a specially adapted etching in which the etching rate is direction-dependent (anisotropic), that the desired prismatic, in particular triangular, structure is created.
Die bei der erfindungsgemäßen Strukturierung entεtehenden Seitenflächen deε dreieckförmigen Kanalbereichε εind für die Passivierung mit einem Gateoxid, insbesondere Siliziumoxid, besonders geeignet, wodurch die Zuverläεεigkeit des Bauelementes gesteigert wird. Die Bildung des Gateoxides erfolgt vorzugsweise durch thermische Oxidation.The side surfaces of the triangular channel region which are created in the structuring according to the invention are particularly suitable for passivation with a gate oxide, in particular silicon oxide, as a result of which the reliability of the component is increased. The gate oxide is preferably formed by thermal oxidation.
Im Anεchluß an die Bildung deε Gateoxideε wird ein Polyεilizium-Gate hergestellt, in dem zunächst Polysilizium ganzflächig abgeschieden und anschließend der fingerförmige Gatebereich trockenchemisch strukturiert wird. Der Gatebereich dient im nachfolgenden Dotierungs-/Implantationsschritt als Kanalmaskierung, wobei dies ebenfalls als selbstjustierender Prozeß abläuft. Im Anschluß an die Temperung und Aktivierung der implantierten Dotierεtoffe werden die Kontakte für Source-, Drain- und Gateanschlüsse lithographiert, strukturiert und einlegiert.Following the formation of the gate oxide, a polysilicon gate is produced, in which polysilicon is first deposited over the entire surface and then the finger-shaped gate region is structured in a dry chemical manner. The gate region serves as channel masking in the subsequent doping / implantation step, this also taking place as a self-adjusting process. Following the tempering and activation of the implanted dopants, the contacts for source, drain and gate connections are lithographed, structured and alloyed.
Die Source- und Drainbereiche deε Bauelementes können in herkömmlicher Weise als ebene Mesa-Bereiche auf dem Substrat ausgebildet sein.The source and drain regions of the component can be formed in a conventional manner as flat mesa regions on the substrate.
Weiter bevorzugte Ausführungεformen der Erfindung gehen aus weiteren Unteransprüchen hervor.Further preferred embodiments of the invention emerge from further subclaims.
Eine besondere Ausführungεform der Erfindung εieht vor, daß der Herεtellungεvorgang auεgehend von einem Wafer beεtehend auε einem Silizium-Subεtrat mit einer unter der Siliziumoberfläche verborgenen Oxidschicht erfolgt. Solche Wafer εind koεtengünstig als handelsübliche Materialien erhältlich, wobei vorzugsweiεe SIMOX oder BESOI-Wafer als Ausgangεwafer in Frage kommen. Insbesondere bei der Verwendung eines BESOI- Ausgangswafers lassen sich hohe Schaltgeschwindigkeiten erreichen.A special embodiment of the invention provides that the manufacturing process takes place starting from a wafer consisting of a silicon substrate with an oxide layer hidden under the silicon surface. Such wafers are inexpensively available as commercially available materials, preferably SIMOX or BESOI wafers can be used as starting wafers. In particular when using a BESOI output wafer, high switching speeds can be achieved.
Die möglichen Anwendungsgebiete für das erfindungsgemäße Bauelement erstrecken sich von den klassischen MOS- Kapazitäten, Dioden und MOS-Transiεtoren über Spezialanwendungen, wie zum Beispiel komplexe Logikoperatoren unter Ausnutzung von Mehrfach- Gatestrukturen und Quanteneffekten, bis hin zu optischen Bauelementen.The possible fields of application for the component according to the invention extend from the classic MOS capacitors, diodes and MOS transistors to special applications, such as complex logic operators using multiple gate structures and quantum effects, to optical components.
Die Erfindung wird im folgenden anhand von Ausführungsbeispielen näher erläutert. Dabei zeigenThe invention is explained in more detail below on the basis of exemplary embodiments. Show
Fig. 1 eine perspektivische Ansicht des prinzipiellen Aufbaus eines herkömmlichen MOSFET-BauelementesFig. 1 is a perspective view of the basic structure of a conventional MOSFET component
Fig. 2a eine Draufsicht auf den prinzipiellen Aufbau eines Bauelementeε gemäß Ausführungsbeispiel der Erfindung2a shows a plan view of the basic structure of a component according to the exemplary embodiment of the invention
Fig. 2b einen Schnitt des Kanalbereichs deε Ausführungsbeispiels der Erfindung2b shows a section of the channel region of the exemplary embodiment of the invention
Fig. 2c eine um den Gatebereich ergänzte Darstellung zu Fig. 2b2c shows a representation of FIG. 2b supplemented by the gate area
Fig. 2d einen Ausschnitt des Kanalbereichε nach Fig. 2b, 2c in perspektivischer Prinzip- Darstellung2d shows a detail of the channel area according to FIGS. 2b, 2c in a perspective schematic representation
Fig. 3 den Aufbau eines Auεgangswafers zur Herstellung eines Bauelementes gemäß Ausführungsbeispiel der Erfindung Fig. 4 eine Prinzipskizze zur Erläuterung des3 shows the structure of an output wafer for producing a component in accordance with the exemplary embodiment of the invention Fig. 4 is a schematic diagram for explaining the
Herstellungsverfahrenε für ein Bauelement gemäß Ausführungsbeiεpiel der ErfindungManufacturing method for a component according to the exemplary embodiment of the invention
Fig. 5 eine IU-Kennlinie deε Bauelementeε gemäß Auεführungεbeiεpiel5 shows an IU characteristic of the component in accordance with the example
Fig. 6 eine Übertragungs-Kennlinie des Bauelementes und die Kennlinie der Transistor-SteilheitFig. 6 shows a transmission characteristic of the component and the characteristic of the transistor slope
Fig. 1 zeigt ein nach der bekannten MOSFET- Planartechnologie hergestelltes Bauelement, hier ein N-Kanal MOSFET, welches aus einem p-dotierten Substratbereich 1 besteht, auf dessen Oberfläche durch entsprechende Masken-Ätztechnik Source-, Gate- und Drainbereiche des Feldeffekt-Transistors ausgebildet sind. Die Bereiche erstrecken sich entlang der Oberfläche des Substrates 1 und haben eine jeweils rechteckige Querschnittεεtruktur. Unterhalb deε Source- bzw. deε Drainbereichs erstrecken sich ins Substrat 1 hinein N- Kontakte, die zwischen εich einen Kanalbereich einschließen, der vertikal unterhalb des Gatebereichs und von diesem durch ein Gateoxid isoliert angeordnet ist. Durch die zwischen Gate und Source anliegende Spannung UGS läßt sich der im Kanal fließende elektriεche Strom zwischen Source und Drain im Sinne eines regelbaren elektrischen Widerstandeε εteuern.1 shows a component manufactured according to the known MOSFET planar technology, here an N-channel MOSFET, which consists of a p-doped substrate region 1, on the surface of which by means of appropriate mask etching technology source, gate and drain regions of the field effect transistor are trained. The regions extend along the surface of the substrate 1 and each have a rectangular cross-sectional structure. Below the source or drain region, N contacts extend into the substrate 1 and enclose between them a channel region which is arranged vertically below the gate region and insulated from it by a gate oxide. The voltage U GS present between gate and source allows the electrical current flowing in the channel to be controlled between source and drain in the sense of a controllable electrical resistance.
Fig. 2a biε 2d zeigen einen gemäß Ausführungsbeispiel der Erfindung hergestellten NMOS Transiεtor in Prinzip- Darεtellung.2a to 2d show an NMOS transistor produced in accordance with the exemplary embodiment of the invention in a basic illustration.
Alε Auεgangεmaterial für die Realiεierung deε NMOS- Tranεistorε nach Auεführungεbeispiel wird ein handelεüblicher Wafer mit vergrabener Oxidεchicht, beispielsweise ein BESOI- oder SIMOX-Wafer verwendet, dessen prinzipieller Aufbau in Fig. 3 dargestellt ist.A commercially available wafer with a buried oxide layer is used as the starting material for the realization of the NMOS transistor according to the exemplary embodiment, For example, a BESOI or SIMOX wafer is used, the basic structure of which is shown in FIG. 3.
Dieser besteht auε einem p- oder n-dotiertem Silizium- Subεtrat 1 mit einer Dicke von etwa 700 μm, einer darauf befindlichen Si02-Schicht 2 mit einer Dicke von etwa 500 nm, auf deren Oberεeite eine p- oder n-dotierte Siliziumschicht 3 ausgebildet ist, deren Dicke etwa 700 nm beträgt. Die Si02-Schicht in einem solchen Wafer bezeichnet man auch als vergrabene Isolationsschicht. Die auf deren Oberseite ausgebildete Schicht wird als "aktive Schicht" 3 bezeichnet.This consists of a p- or n-doped silicon substrate 1 with a thickness of about 700 μm, an SiO 2 layer 2 thereon with a thickness of about 500 nm, on the top of which a p- or n-doped silicon layer 3 is formed, the thickness of which is approximately 700 nm. The Si0 2 layer in such a wafer is also called a buried insulation layer. The layer formed on the upper side thereof is referred to as "active layer" 3.
Fig. 2a zeigt den prinzipiellen Aufbau des Bauelementes in Draufsicht. Zwischen den Anschlußbereichen A, die später als Drain (D) und Source (S) - Kontakte dienen, ist als deren elektrisch leitfähige Verbindung ein Kanalbereich (K) gebildet. Dieser wird teilweise von einem elektrisch von ihm isolierten Gatebereich (G) überdeckt. Der Kanalbereich weist die Form eines auf der Iεolationεschicht liegenden Dreieckspriεmas auf (Fig. 2b) . Es weist eine Querschnittsfläche in der Form eines εpitzwinkligen Dreieckε auf, wobei die dem εpitzen Winkel gegenüberliegende Dreieckεkante parallel zur Substratebene liegt. Die Herstellung des dreieckförmigen Kanalbereiches K erfolgt durch aniεotropeε naßchemiεches Ätzen.Fig. 2a shows the basic structure of the component in plan view. Between the connection areas A, which will later serve as drain (D) and source (S) contacts, a channel area (K) is formed as their electrically conductive connection. This is partially covered by a gate region (G) which is electrically insulated from it. The channel region has the shape of a triangular prism lying on the insulation layer (FIG. 2b). It has a cross-sectional area in the form of an acute-angled triangle, the triangular edge lying opposite the acute angle lying parallel to the substrate plane. The triangular channel region K is produced by anisotropic wet chemical etching.
Auf den kristallographisch ausgezeichneten Seitenflächen des dreiecksprismenförmigen Kanalbereichs K ist eine Gateoxidschicht 4, z.B. durch thermische Oxidation, aufgebracht (Fig. 2c) . Diese stellt eine Pasεivierung der Siliziumoberfläche deε Kanalbereichε K dar und dient zur elektrischen Isolation gegenüber der eigentlichen Gateelektrode (Gatekontakt 5) , die anschließend durch trockenchemischeε Strukturieren in Form des in Fig. 2a dargeεtellten "Gatefingerε" über der Gateoxidεchicht 4 in dem entsprechenden Bereich des Kanals K ausgebildet wird. Fig. 2d zeigt die zu Fig. 2c gehörige perspektiviεche Darεtellung, wobei das Substrat bzw. die vergrabene Isolationεschicht weggelassen wurde.A gate oxide layer 4 is applied to the crystallographically marked side surfaces of the triangular prismatic channel region K, for example by thermal oxidation (FIG. 2c). This represents a passivation of the silicon surface of the channel region K and serves for electrical insulation with respect to the actual gate electrode (gate contact 5), which is subsequently formed by dry chemical structuring in the form of FIG. 2a shown "gate finger" is formed over the gate oxide layer 4 in the corresponding region of the channel K. FIG. 2d shows the perspective representation belonging to FIG. 2c, the substrate or the buried insulation layer being omitted.
Daε in Fig. 2a-2c dargeεtellte Auεführungsbeispiel bezieht εich im weεentlichen auf den Gatebereich eines NMOS-Transistorε, deεsen Herstellungsverfahren nach folgenden Schritten abläuft:The embodiment shown in FIGS. 2a-2c essentially relates to the gate area of an NMOS transistor, the manufacturing process of which proceeds according to the following steps:
Durch geeignete Maskierung und naßchemische Strukturierung werden die Mesa-Gebiete für die Source- und Drainanεchlüεse sowie der beide Gebiete miteinander verbindende elektrisch leitfähige dreieckεpriεmenförmige Kanal K (Fig. 2) realisiert. Source und Drain sind ansonsten voneinander elektrisch isoliert. Nach der thermiεchen Oxidation zur Bildung deε Gateoxideε wird im nächεten Schritt ein Polysilizium-Gate hergestellt. Hierzu wird zunächεt Polyεilizium ganzflächig abgeεchieden, die Gatefingerεtruktur lithographiert und anschließend trockenchemisch εtrukturiert. Der Gatebereich dient im nachfolgenden Dotierungs- /Implantationεschritt alε Kanalmaεkierung (selbstjustierender Prozeß) .The mesa regions for the source and drain connections and the electrically conductive triangular-prism-shaped channel K (FIG. 2) connecting the two regions are realized by suitable masking and wet chemical structuring. Otherwise, the source and drain are electrically isolated from one another. After the thermal oxidation to form the gate oxides, a polysilicon gate is produced in the next step. For this purpose, first of all, polysilicon is deposited over the entire surface, the gate finger structure is lithographed and then structured with dry chemistry. In the subsequent doping / implantation step, the gate area serves as channel masking (self-adjusting process).
Im Anschluß an die Temperung und Aktivierung der implantierten Dotierstoffe werden die Kontakte lithographiert, strukturiert und einlegiert.Following the annealing and activation of the implanted dopants, the contacts are lithographed, structured and alloyed.
Die elektrische Ausgangskennlinie eineε nach dem oben dargestellten Auεführungεbeiεpiel hergeεtellten NMOS- Tranεiεtors iεt in Fig. 5 dargeεtellt. Dieεe zeigt den Drain-Sourcestrom Ids als Funktion der Drain- Sourceεpannung (Uds) in Abhängigkeit von der Gatespannung UGS. Die gemessenen Ausgangskennlinien verdeutlichen, daß trotz der verringerten geometrischen lateralen Abmessungen des Kanalbereichs ein mit der herkömmlichen Planartechnologie vergleichbares elektrisches Verhalten erzielt wird, d.h. ein hoher Drain-Source Strom fließt. Daε beεchriebene Herεtellungsverfahren zeichnet εich dadurch auε, daß die Schrittfolge kompatibel ist mit der Standard MOS-Technologie.The electrical output characteristic curve of an NMOS transistor manufactured according to the embodiment shown above is shown in FIG. 5. This shows the drain-source current I ds as a function of the drain-source voltage (U ds ) as a function of the gate voltage U GS . The measured output characteristics show that Despite the reduced geometric lateral dimensions of the channel region, electrical behavior comparable to that of conventional planar technology is achieved, ie a high drain-source current flows. The described production method is characterized by the fact that the sequence of steps is compatible with the standard MOS technology.
Der im folgenden detailliert beschriebene Herεtellungεprozeß beginnt mit der Herεtellung der Mesa- Struktur für die Drain- und Sourcebereiche, deren Iεolierung voneinander und der Herstellung des "facettierten Siliziumsteges" als Kanalbereich (Fig. 2) . Hierbei werden übliche anisotrope Strukturierungsmethoden der Si-Halbleitertechnologie angewendet.The production process described in detail below begins with the production of the mesa structure for the drain and source regions, their insulation from one another and the production of the “faceted silicon web” as a channel region (FIG. 2). The usual anisotropic structuring methods of Si semiconductor technology are used.
Die Herstellung erfolgt ausgehend von BESOI-Wafern, die aus einer Sandwich-Struktur beεtehen, welche eine 500 nm dicke verborgene SiO.-Schicht enthält, die mit einer 700 nm dicken aktiven Si-Deckschicht versehen ist, welche p- dotiert ist (Bor, 5*1015 cm"3) .The production is based on BESOI wafers, which consist of a sandwich structure that contains a 500 nm thick hidden SiO.layer, which is provided with a 700 nm thick active Si top layer, which is p-doped (boron, 5 * 10 15 cm "3 ).
Um die Source- und Drainflächen auszubilden sowie den dreieckförmigen Si-Kanalbereich, wird eine 100 nm dicke Si3N4-Schicht auf der Oberfläche des BESOI-Wafers mit Hilfe der LPCVD- (Low pressure chemical vapor deposition) Methode abgeschieden. Das Bauelement-Layout wird anschließend mittelε Elektronenεtrahl-Lithographie bei einer Spannung von 35 KV unter Verwendung eines PMMA 950K E-Beam Lackeε mit einer Dicke von 200 nm belichtet.In order to form the source and drain areas and the triangular Si channel region, a 100 nm thick Si 3 N 4 layer is deposited on the surface of the BESOI wafer using the LPCVD (low pressure chemical vapor deposition) method. The component layout is then exposed by means of electron beam lithography at a voltage of 35 KV using a PMMA 950K e-beam varnish with a thickness of 200 nm.
Aufgrund der Erforderniεse des anisotropen naßchemischen Ätzprozesses muß der Wafer vor der Belichtung genau ausgerichtet werden. Nach der Entwicklung des Lackes erfolgt der Ätzvorgang trockenchemisch mittels reaktiven Ionenätzenε der Si3N4-Schicht auf aniεotropen Wege mittels CHF3/O-.Due to the requirements of the anisotropic wet chemical etching process, the wafer must be aligned precisely before exposure. After the development of the lacquer, the etching process is carried out dry-chemically by means of reactive Ion etching of the Si 3 N 4 layer by anisotropic means using CHF 3 / O-.
Die strukturierte Si3N4-Schicht bildet die Maske für das folgende Naßätzen der aktiven Si-Deckschicht mit einer verdünnten KOH-Lösung. Die Ätzrate innerhalb der Si- Schicht ist dabei richtungsabhängig. In Richtung der (100) -Kristallrichtung erfolgt der Ätzvorgang in KOH dreihundertmal schneller als in der (111)- Kriεtallrichtung. Hierdurch iεt der Prozeß vollεtändig selbstjustierend, er endet nämlich dann automatisch, wenn die (111) -Ebene bzw. die verborgene Oxidschicht des BESOI-Wafers erreicht ist. Hierdurch läßt εich ein sehr εcharfkantiger dreieckiger Querschnitt erreichen. Die verbleibende Breite der Spitze des so ausgebildeten Dreiecks beträgt nur noch etwa 50 nm.The structured Si 3 N 4 layer forms the mask for the subsequent wet etching of the active Si cover layer with a dilute KOH solution. The etching rate within the Si layer depends on the direction. In the direction of the (100) crystal direction, the etching process in KOH takes place three hundred times faster than in the (111) crystal direction. As a result, the process is completely self-adjusting, namely it ends automatically when the (111) plane or the hidden oxide layer of the BESOI wafer is reached. This enables a very sharp triangular cross section to be achieved. The remaining width of the tip of the triangle thus formed is only about 50 nm.
Im nächsten Schritt wird die Si3N„-Maske selektiv mittels H3P04 entfernt. Nach der nachfolgenden üblichen RCA Reinigung wird eine 11 nm dicke Gateoxidschicht bei 1050° C mittelε trockener thermiεcher Oxidation aufgewachεen. Hierbei verrundet die Spitze des Kanalbereichs leicht. Die Gateoxidεchicht wird dann mit einer 300 nm dicken Polysiliziumschicht mittels LPCVD bei 750° C bedeckt.In the next step, the Si 3 N 2 mask is selectively removed using H 3 P0 4 . After the following conventional RCA cleaning, a 11 nm thick gate oxide layer is waxed up at 1050 ° C. by means of dry thermal oxidation. The tip of the channel area is rounded slightly. The gate oxide layer is then covered with a 300 nm thick polysilicon layer using LPCVD at 750 ° C.
Der Gatebereich selbst wird durch einen zweiten Elektronenstrahl-Lithographieεchritt definiert. Nach Belichtung und Entwicklung deε Lackeε wird Titan auf die Oberfläche aufgedampft. Ein Lift-Off-Prozeß führt dazu, daß eine metalliεche Maεke auεgebildet wird für den nachfolgenden Tockenätzεchritt der Polysiliziumschicht, welche durch einen SF6RIE-Prozeß realisiert wird.The gate area itself is defined by a second electron beam lithography step. After exposure and development of the coating, titanium is evaporated onto the surface. A lift-off process leads to the formation of a metallic mask for the subsequent drying etching step of the polysilicon layer, which is realized by an SF 6 RIE process.
Nach der Ausbildung der Polysilizium-Gateεchicht wird ein zuεätzlicher RCA Reinigungεεchritt durchgeführt, um die Oberfläche zu reinigen. Anεchließend erfolgt ein weiterer thermischer Oxidationsschritt, in dem die Seitenwände der trockengeäzten Gate-Strukturen geschützt werden. Hierdurch werden später Leckströme vermieden.After the formation of the polysilicon gate layer, an additional RCA cleaning step is carried out in order to clean the surface. Then there is another thermal oxidation step in which the sidewalls of the dry-etched gate structures are protected. As a result, leakage currents are avoided later.
Um die n+-Bereiche der Source- und Drainkontakte herzustellen, wird Arsen bei einer Beschleunigungs- εpannung von 40 KV mit einer Doεierrate von 5*1015 cm"2 implantiert. Während der Implantation iεt die Kanalfläche mit dem Polyεiliziumgate maskiert, wodurch sich der Vorteil des selbstjuεtierenden Prozesses ergibt. Um eine Ausdiffuεion von Arεen in dem folgenden Temperatur- und Aktivierungεschritt zu vermeiden, wird Si02 mittels PECVD- Verfahren bei einer Temperatur von 300° C abgeschieden. Die Temperatur der Probe zum Zwecke der Rekristalliεation und die Aktivierung deε Dotierstoffes Arsen wird gleichzeitig bei 900° C ausgeführt.In order to produce the n + regions of the source and drain contacts, arsenic is implanted at an acceleration voltage of 40 KV with a dosing rate of 5 * 10 15 cm "2. During the implantation, the channel surface is masked with the polysilicon gate, whereby the In order to prevent arsenic from diffusing out in the following temperature and activation step, SiO 2 is deposited using the PECVD method at a temperature of 300 ° C. The temperature of the sample for the purpose of recrystallization and the activation of the dopant Arsenic is run simultaneously at 900 ° C.
Anschließend wird die PECVD-Si02 Diffusionεbarriere mittels HF-Ätzens entfernt. Dann werden die Anschlußkontakte mittels Elektronenstrahl-Lithographie definiert. Um die Ohm' sehen Kontakte zu bilden, werden 20 nm Aluminium und 200 nm Gold ganzflächig aufgedampft und selektiv bis auf die Kontaktbereiche entfernt durch einen weiteren Lift-Off-Prozeß. Anschließend werden die Kontakte bei 330° C einlegiert.The PECVD-Si0 2 diffusion barrier is then removed by means of HF etching. Then the connection contacts are defined by means of electron beam lithography. In order to form the ohm 'contacts, 20 nm aluminum and 200 nm gold are evaporated over the entire surface and selectively removed except for the contact areas by a further lift-off process. Then the contacts are alloyed at 330 ° C.
Mittels deε oben beschriebenen Herstellungsverfahrens wurden geometrische Kanalgatelängen LGB0 zwischen 0,8 μm und 2 μm realisiert. Die geometrische Gateweite Wgeo stellt die (lll) -Kantenlänge des dreieckförmigen Kanalbereichs dar. Die Höhe des Dreiecks beträgt dabei 700 nm und der Winkel der Seitenwände jeweils 54,7°. Dies führt zu einem Wert von Wgeo von 1,7 μm. Die Kennlinie eines solchen Bauelementes bei Raumtemperatur mit einer Gatelänge von LGE0 = l μm ist in Figur 5 dargestellt. Die Strom-Spannungε-Charakteriεtik der auf dieεe Weiεe hergestellten NMOSFET Bauelemente ist vergleichbar mit der von planaren Elementen. Die Ausgangεεtröme erreichen Werte von etwa 400 μA bei einer Betriebsspannung von 5 V. Die Sättigung der Kennlinien des Drain-Sourcestromes IDS wird für verεchiedene Gate-Sourceεpannungen VDS erreicht. Figur 6 zeigt die Übertragungεkennlinie des Bauelementes bei einer Drain-Sourcespannung von 3,5 V. Die Sättigungssteilheit gm der Transistorstruktur erreicht Werte oberhalb von 200 μS.Geometric channel gate lengths L GB0 between 0.8 μm and 2 μm were realized by means of the manufacturing method described above. The geometric gate width W geo represents the (III) edge length of the triangular channel region. The height of the triangle is 700 nm and the angle of the side walls is 54.7 ° in each case. This leads to a value of W geo of 1.7 μm. The characteristic curve of such a component at room temperature with a gate length of L GE0 = 1 μm is shown in FIG. The current-voltage characteristic of the NMOSFET components produced in this way is comparable to that of planar elements. The output currents reach values of approximately 400 μA at an operating voltage of 5 V. The saturation of the characteristics of the drain-source current I DS is achieved for different gate-source voltages V DS . FIG. 6 shows the transfer characteristic of the component at a drain-source voltage of 3.5 V. The saturation slope g m of the transistor structure reaches values above 200 μS.
Das Verhalten des Transistors mit dreiecksprismenformigem Kanalbereich gemäß Ausführungεbeiεpiel der Erfindung kann wie folgt erklärt werden:The behavior of the transistor with a triangular prismatic channel region according to the exemplary embodiment of the invention can be explained as follows:
Wenn daε Polyεilizium-Gate den dreieckεpriεmenförmigen Silizium-Kanalbereich, welcher durch daε Gateoxid iεoliert iεt, überdeckt und eine Spannung UGS zwiεchen Gate und Source angelegt wird, wird im Bereich der Priεmenoberflache - induziert durch die elektrischen Felder - eine Inverεionεεchicht erzeugt. Dieεe bildet entlang der Randflächen deε Dreieckε einen leitenden Kanal zwiεchen Source und Drain aus. An den scharfen Kanten des Dreiecks, inεbeεondere im Bereich der Spitze, iεt die Stärke deε inhomogenen elektrischen Feldes dabei sehr viel höher als bei planaren Bauelementen. Weil die Elektronenkonzentration proportional zum elektrischen Feld verläuft, kann der leitfähige Kanal innerhalb deε dreidimenεional ausgebildeten Siliziumpfades als weεentlich "effektiver" angesehen werden im Vergleich zu planaren Bauelementen.If the poly-silicon gate covers the triangular-prism-shaped silicon channel region, which is isolated by the gate oxide, and a voltage U GS is applied between the gate and source, an inversion layer is generated in the region of the prism surface, induced by the electric fields. This forms a conductive channel between the source and drain along the edge surfaces of the triangle. At the sharp edges of the triangle, in particular in the area of the tip, the strength of the inhomogeneous electric field is much higher than with planar components. Because the electron concentration is proportional to the electric field, the conductive channel within the three-dimensionally formed silicon path can be regarded as "more effective" compared to planar components.
Dieser anhand des Ausführungsbeispieles für ein Bauelement mit einem dreieckförmigen Prisma dargestellte Effekt läßt εich prinzipiell auch bei prismenförmigen Kanalbereichen erreichen, die allgemein einen Querschnitt in Form eines n-Eckes (n _> 3) aufweiεen. Wesentlich iεt, daß ein Kantenbereich vorliegt, an dem eine entεprechend inhomogene elektrische Feldstruktur entsteht. This effect, illustrated by the exemplary embodiment for a component with a triangular prism, can in principle also be achieved with prism-shaped channel regions which generally have a cross section in the form of an n-corner (n _> 3). It is essential that there is an edge area on which a correspondingly inhomogeneous electrical field structure is created.

Claims

P A T E N T A N S P R Ü C H E PATENT CLAIMS
1. Halbleiter-Bauelement in Planartechnologie bestehend aus einem Substrat (1) , insbesondere einem Silizium- Substrat, und darauf ausgebildeten zueinander beabstandeten iεolierten Anschlußbereichen (A) , zwischen denen isoliert zu den Anschlußbereichen (A) ein elektrisch leitfähiger Kanalbereich (K) ausgebildet iεt, d a d u r c h g e k e n n z e i c h n e t, daß der sich zwiεchen den Abεchlußbereichen (A) erεtreckende dreidimensional ausgebildete Kanalbereich (K) die Form eines Prismas aufweist, dessen Querschnittsfläche mindestens drei Ecken aufweist, wobei eine der Prismenrandflächen parallel zur Substratebene angeordnet iεt.1. Semiconductor component in planar technology consisting of a substrate (1), in particular a silicon substrate, and insulated connection regions (A) spaced apart therefrom, between which an electrically conductive channel region (K) is formed in isolation from the connection regions (A) , characterized in that the three-dimensionally formed channel region (K) extending between the end regions (A) has the shape of a prism, the cross-sectional area of which has at least three corners, one of the prism edge surfaces being arranged parallel to the substrate plane.
2. Halbleiter-Bauelement nach Anεpruch 1 , d a d u r c h g e k e n n z e i c h n e t, daß daε Substrat (1) eine vergrabene Iεolationεschicht (2) aufweiεt, und daß eine der Prismenrandflächen parallel zur vergrabenen Isolationεschicht (2) angeordnet iεt.2. Semiconductor component according to claim 1, so that the substrate (1) has a buried insulation layer (2) and that one of the prism edge surfaces is arranged parallel to the buried insulation layer (2).
3. Halbleiter-Bauelement nach Anεpruch 2, d a d u r c h g e k e n n z e i c h n e t, daß mindestens eine der Prismenrandflächen einer kriεtallographisch ausgezeichneten Fläche des Halbleitermaterialε entspricht.3. Semiconductor component according to claim 2, so that at least one of the prism edge surfaces corresponds to a crystallographically marked surface of the semiconductor material.
4. Halbleiter-Bauelement nach Anspruch 3, d a d u r c h g e k e n n z e i c h n e t, daß das Prisma ein Dreiecksprisma ist . 4. A semiconductor device according to claim 3, characterized in that the prism is a triangular prism.
5. Halbleiter-Bauelement nach einem der Ansprüche 1 biε 4, d a d u r c h g e k e n n z e i c h n e t, daß die oberhalb der vergrabenen Iεolationεεchicht (2) angeordnete aktive Schicht (3) auf Gruppe IV-Halbleiter- material beruht.5. Semiconductor component according to one of claims 1 to 4, which means that the active layer (3) arranged above the buried insulation layer (2) is based on Group IV semiconductor material.
6. Halbleiter-Bauelement nach Anspruch 5, d a d u r c h g e k e n n z e i c h n e t, daß die aktive Schicht (3) auf Si-Material beruht und daß die Prismenrandflächen den (100) bzw. (111) -Flächen entsprechen.6. The semiconductor component according to claim 5, that the active layer (3) is based on Si material and that the prism edge surfaces correspond to the (100) or (111) surfaces.
7. Halbleiter-Bauelement nach einem der Ansprüche 1 bis 6, wobei daε Bauelement ein Feldeffekt-Transistor ist, und dessen Anschlußbereiche als Source (S) bzw. Drain (D) - Bereiche ausgebildet εind und zwischen diesen ein Gatebereich (G) liegt, wobei isoliert vom und benachbart zum Gatebereich (G) der elektrisch leitfähige Kanalbereich (K) angeordnet ist, d u r c h g e k e n n z e i c h n e t, daß mindeεtenε zwei Priεmenrandflächen deε Kanalbereichs (K) mit einem isolierenden Gateoxid (4) beschichtet sind, auf dem der Gatebereich (G,5) auεgebildet ist.7. Semiconductor component according to one of claims 1 to 6, wherein the component is a field effect transistor, and the connection regions of which are formed as source (S) or drain (D) regions and a gate region (G) lies between them. the electrically conductive channel region (K) being arranged insulated from and adjacent to the gate region (G), characterized in that at least two prism edge surfaces of the channel region (K) are coated with an insulating gate oxide (4) on which the gate region (G, 5) is trained.
8. Halbleiter-Bauelement nach Anspruch 7, d a d u r c h g e k e n n z e i c h n e t, daß Source (S) und Drain (D) - Bereiche alε planare Meεa-Strukturen in der aktiven Schicht (3) auεgebildet εind.8. Semiconductor component according to claim 7, so that the source (S) and drain (D) regions are formed as planar Meεa structures in the active layer (3).
9. Halbleiter-Bauelement nach Anεpruch 7, d a d u r c h g e k e n n z e i c h n e t, daß der Gatebereich (G,5) aus leitfähigem Polysilizium auεgebildet iεt. 9. A semiconductor device according to claim 7, characterized in that the gate region (G, 5) is formed from conductive polysilicon.
10. Verfahren zur Herstellung eines Halbleiter- Bauelementes in Planartechnologie, bei dem in einer aktiven Halbleiterεchicht (3) , die sich auf einem Substrat (1) befindet, entsprechend zuvor maskierten Flächen voneinander isolierte und beabstandete Anschlußbereiche (A) , die durch einen leitfähigen Kanalbereich (K) miteinander verbunden sind, durch chemisches Ätzen ausgebildet werden, d a d u r c h g e k e n n z e i c h n e t, daß der Kanalbereich (K) dreidimensional priεmenförmig auεgebildet wird.10. A method for producing a semiconductor component in planar technology, in which in an active semiconductor layer (3), which is located on a substrate (1), in accordance with previously masked areas, mutually insulated and spaced-apart connection regions (A) through a conductive channel region (K) are connected to one another, are formed by chemical etching, characterized in that the channel region (K) is formed three-dimensionally in a prismatic manner.
11. Verfahren zur Herεtellung eineε Halbleiter- Bauelements nach Anspruch 10, d a d u r c h g e k e n n z e i c h n e t, daß bei einem Subεtrat, welcheε ein Wafer mit einer vergrabenen Iεolationεεchicht (2) iεt, eine der Priεmenrandflachen auf der vergrabenen Schicht (2) angeordnet iεt.11. The method for producing a semiconductor component according to claim 10, which also means that in the case of a substrate which is a wafer with a buried insulation layer (2), one of the prism edge surfaces is arranged on the buried layer (2).
12. Verfahren zur Herεtellung eineε Halbleiter- Bauelementε nach Anspruch 10 oder 11, d a d u r c h g e k e n n z e i c h n e t, daß die Auεbildung deε prismenförmigen Kanalbereichs (4) durch einen anisotropen naßchemiεchen Ätzvorgang erfolgt.12. A method for producing a semiconductor component according to claim 10 or 11, so that the prism-shaped channel region (4) is formed by an anisotropic wet chemical etching process.
13. Verfahren zur Herεtellung eineε Halbleiter- Bauelements nach Anspruch 10, 11 oder 12, d a d u r c h g e k e n n z e i c h n e t, daß in der aktiven Siliziumschicht (3) ein sich zwischen Source (S) und Drain (D) erstreckender Kanalbereich (K) mit einem dreieckεpriεmenförmigen Querεchnitt gebildet wird, wobei der εpitze Winkel deε Dreieckpriεmaε auε der Subεtratebene weiεt, und daß nach Bildung einer Gate- Oxidschicht (4) auf den schrägen Seitenflächen des Kanalbereichs (K) die Ausbildung des Gatekontakts (5) erfolgt. 13. A method for the manufacture of a semiconductor component according to claim 10, 11 or 12, characterized in that in the active silicon layer (3) a channel region (K) extending between the source (S) and drain (D) is formed with a triangular-shaped cross-section , The acute angle of the triangular prism knows from the substrate plane, and that after the formation of a gate oxide layer (4) on the oblique side surfaces of the channel region (K), the gate contact (5) is formed.
14. Verfahren zur Herstellung eineε Bauelementeε nach Anεpruch 13, d a d u r c h g e k e n n z e i c h n e t, daß die Ausbildung der Gate-Oxidschicht (4) durch thermische Oxidation erfolgt.14. A method for producing a component according to claim 13, so that the gate oxide layer (4) is formed by thermal oxidation.
15. Verfahren zur Herstellung eines Halbleiter- Bauelementes nach einem der vorhergehenden Ansprüche 10 bis 14, d a d u r c h g e k e n n z e i c h n e t, daß die Ausbildung des Gatekontaktbereichs (5) durch trockenchemische Strukturierung erfolgt.15. A method for producing a semiconductor component according to one of the preceding claims 10 to 14, d a d u r c h g e k e n n z e i c h n e t that the formation of the gate contact region (5) is carried out by dry chemical structuring.
16. Verfahren zur Herstellung eines Halbleiter- Bauelementes nach einem der vorhergehenden Ansprüche 10 bis 15, d a d u r c h g e k e n n z e i c h n e t, daß der Gatebereich (5) als Polyεilizium Gatebereich auεgebildet ist.16. A method for producing a semiconductor component according to one of the preceding claims 10 to 15, that the gate region (5) is designed as a poly-silicon gate region.
17. Verfahren zur Herstellung eines Halbleiter- Bauelementes nach einem der Ansprüche 11 bis 16, d a d u r c h g e k e n n z e i c h n e t, daß der Auεgangswafer ein SIMOX (Separation by implanted oxygen) Wafer ist.17. A method for producing a semiconductor component according to one of claims 11 to 16, so that the output wafer is a SIMOX (Separation by implanted oxygen) wafer.
18. Verfahren zur Herstellung eines Halbleilter- Bauelementes nach einem der Ansprüche 11 biε 16, d a d u r c h g e k e n n z e i c h n e t, daß der Ausgangεwafer ein BESOI (bonded and etched (back) εilicon-on-insulator) Wafer ist.18. A method for producing a semi-conductor component according to any one of claims 11 to 16, which means that the output wafer is a BESOI (bonded and etched (back) silicone-on-insulator) wafer.
19. Verwendung eines Verfahrens nach einem der Ansprüche 10 bis 18 zur Herεtellung einer pin-Diode. 19. Use of a method according to any one of claims 10 to 18 for the manufacture of a pin diode.
20. Verwendung eineε Verfahrenε nach einem der Anεprüche 10 biε 18 zur Herstellung eineε optoelektroniεchen Bauelementeε, bei dem die aktive Schicht auε einer Silizium- Heterohalbleiterverbindung der Gruppe IV (Silizium-Germanium-Kohlenεtoff) oder aus dotiertem Silizium, insbesondere mit Seltenen-Erden dotiertem Silizium, besteht. 20. Use of a method according to one of claims 10 to 18 for producing an optoelectronic component in which the active layer is made of a group IV silicon hetero semiconductor compound (silicon-germanium carbon) or of doped silicon, in particular silicon doped with rare earths , consists.
PCT/EP1996/004755 1995-11-01 1996-11-01 Semiconductor component with prismatic channel area WO1997016854A1 (en)

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