WO1997016901A1 - Clock signal cleaning circuit - Google Patents
Clock signal cleaning circuit Download PDFInfo
- Publication number
- WO1997016901A1 WO1997016901A1 PCT/CA1996/000706 CA9600706W WO9716901A1 WO 1997016901 A1 WO1997016901 A1 WO 1997016901A1 CA 9600706 W CA9600706 W CA 9600706W WO 9716901 A1 WO9716901 A1 WO 9716901A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- clock signal
- clock
- output
- frequency
- input
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0054—Detection of the synchronisation error by features other than the received signal transition
- H04L7/0066—Detection of the synchronisation error by features other than the received signal transition detection of error based on transmission code rule
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
- H03K5/125—Discriminating pulses
- H03K5/1252—Suppression or limitation of noise or interference
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/0079—Receiver details
- H04L7/0083—Receiver details taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/027—Speed or phase control by the received code signals, the signals containing no special synchronisation information extracting the synchronising or clock signal from the received signal spectrum, e.g. by using a resonant or bandpass circuit
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
- H04L7/0337—Selecting between two or more discretely delayed clocks or selecting between two or more discretely delayed received code signals
Landscapes
- Physics & Mathematics (AREA)
- Nonlinear Science (AREA)
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Manipulation Of Pulses (AREA)
- Pulse Circuits (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE69635187T DE69635187T2 (en) | 1995-11-02 | 1996-10-24 | CIRCUIT ARRANGEMENT FOR CLOCK SIGNAL CLEANING |
EP96934256A EP0858699B1 (en) | 1995-11-02 | 1996-10-24 | Clock signal cleaning circuit |
CA002236423A CA2236423C (en) | 1995-11-02 | 1996-10-24 | Clock signal cleaning circuit |
US09/066,423 US6246276B1 (en) | 1995-11-02 | 1996-10-24 | Clock signal cleaning circuit |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CA2,161,982 | 1995-11-02 | ||
CA002161982A CA2161982A1 (en) | 1995-11-02 | 1995-11-02 | Clock cleaner |
Publications (1)
Publication Number | Publication Date |
---|---|
WO1997016901A1 true WO1997016901A1 (en) | 1997-05-09 |
Family
ID=4156897
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/CA1996/000706 WO1997016901A1 (en) | 1995-11-02 | 1996-10-24 | Clock signal cleaning circuit |
Country Status (6)
Country | Link |
---|---|
US (1) | US6246276B1 (en) |
EP (1) | EP0858699B1 (en) |
CA (1) | CA2161982A1 (en) |
DE (1) | DE69635187T2 (en) |
ES (1) | ES2249787T3 (en) |
WO (1) | WO1997016901A1 (en) |
Families Citing this family (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP3703997B2 (en) * | 1999-07-06 | 2005-10-05 | 沖電気工業株式会社 | Video signal control circuit |
US6566939B1 (en) * | 2001-08-06 | 2003-05-20 | Lsi Logic Corporation | Programmable glitch filter |
US7375569B2 (en) * | 2005-09-21 | 2008-05-20 | Leco Corporation | Last stage synchronizer system |
US7420399B2 (en) * | 2005-11-10 | 2008-09-02 | Jonghee Han | Duty cycle corrector |
US8294502B2 (en) * | 2011-03-04 | 2012-10-23 | Altera Corporation | Delay circuitry |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3599103A (en) * | 1967-11-08 | 1971-08-10 | Ibm | Synchronizer for data transmission system |
US4805197A (en) * | 1986-12-18 | 1989-02-14 | Lecroy Corporation | Method and apparatus for recovering clock information from a received digital signal and for synchronizing that signal |
EP0476968A2 (en) * | 1990-09-21 | 1992-03-25 | AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL INC. | Clock recovery circuit |
EP0576150A2 (en) * | 1992-06-19 | 1993-12-29 | Advanced Micro Devices, Inc. | Digital serializer and time delay regulator |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0624315B2 (en) * | 1983-11-04 | 1994-03-30 | 日本ビクター株式会社 | Phase shifter |
-
1995
- 1995-11-02 CA CA002161982A patent/CA2161982A1/en not_active Abandoned
-
1996
- 1996-10-24 WO PCT/CA1996/000706 patent/WO1997016901A1/en active IP Right Grant
- 1996-10-24 EP EP96934256A patent/EP0858699B1/en not_active Expired - Lifetime
- 1996-10-24 ES ES96934256T patent/ES2249787T3/en not_active Expired - Lifetime
- 1996-10-24 US US09/066,423 patent/US6246276B1/en not_active Expired - Fee Related
- 1996-10-24 DE DE69635187T patent/DE69635187T2/en not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US3599103A (en) * | 1967-11-08 | 1971-08-10 | Ibm | Synchronizer for data transmission system |
US4805197A (en) * | 1986-12-18 | 1989-02-14 | Lecroy Corporation | Method and apparatus for recovering clock information from a received digital signal and for synchronizing that signal |
EP0476968A2 (en) * | 1990-09-21 | 1992-03-25 | AT&T GLOBAL INFORMATION SOLUTIONS INTERNATIONAL INC. | Clock recovery circuit |
EP0576150A2 (en) * | 1992-06-19 | 1993-12-29 | Advanced Micro Devices, Inc. | Digital serializer and time delay regulator |
Also Published As
Publication number | Publication date |
---|---|
ES2249787T3 (en) | 2006-04-01 |
EP0858699A1 (en) | 1998-08-19 |
EP0858699B1 (en) | 2005-09-14 |
US6246276B1 (en) | 2001-06-12 |
DE69635187D1 (en) | 2005-10-20 |
CA2161982A1 (en) | 1997-05-03 |
DE69635187T2 (en) | 2006-07-06 |
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