WO1997026591A1 - Junction field effect voltage reference and fabrication method - Google Patents
Junction field effect voltage reference and fabrication method Download PDFInfo
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- WO1997026591A1 WO1997026591A1 PCT/US1997/001007 US9701007W WO9726591A1 WO 1997026591 A1 WO1997026591 A1 WO 1997026591A1 US 9701007 W US9701007 W US 9701007W WO 9726591 A1 WO9726591 A1 WO 9726591A1
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- jfets
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- jfet
- channel
- pinchoff
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Classifications
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- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/24—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only
- G05F3/242—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage
- G05F3/247—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations wherein the transistors are of the field-effect type only with compensation for device parameters, e.g. channel width modulation, threshold voltage, processing, or external variations, e.g. temperature, loading, supply voltage producing a voltage or current as a predetermined function of the supply voltage
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05F—SYSTEMS FOR REGULATING ELECTRIC OR MAGNETIC VARIABLES
- G05F3/00—Non-retroactive systems for regulating electric variables by using an uncontrolled element, or an uncontrolled combination of elements, such element or such combination having self-regulating properties
- G05F3/02—Regulating voltage or current
- G05F3/08—Regulating voltage or current wherein the variable is dc
- G05F3/10—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics
- G05F3/16—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices
- G05F3/20—Regulating voltage or current wherein the variable is dc using uncontrolled devices with non-linear characteristics being semiconductor devices using diode- transistor combinations
- G05F3/30—Regulators using the difference between the base-emitter voltages of two bipolar transistors operating at different current densities
Definitions
- This invention relates to voltage reference circuits and, more particularly, to low noise, linear temperature coefficient voltage reference circuits. Description of the Related Art
- Voltage reference circuits have been developed to provide precise voltage outputs for use in a variety of analog circuits such as operational amplifiers (op amps) , digital-to-analog converters (DACs) and analog to digital converters (ADCs) .
- Commonly used references include “Zener” and “bandgap", or ⁇ VBE, designs. Although such references are suitable for many applications, they are not without their problems. For example, their output voltages vary widely and nonlinearly with temperature, they are not always available in a desired voltage range, some exhibit a "hysteresis" effect, and their noise levels may preclude their use within systems which require a high degree of accuracy, especially low-power systems. Improved noise levels for both Zener and bandgap references may require operation at higher bias currents.
- FIG.l illustrates a basic Zener voltage reference circuit.
- a voltage +V S is supplied to a resistor R s that is connected in series with a reverse-biased Zener diode Dl, the anode of which is connected to the anode of a forward biased diode D2, whose cathode is connected to ground.
- the output reference voltage V REF appearing at terminal 9, the junction of the resistor Rs and the cathode of Dl, is the sum of the forward voltage drop of diode D2 and the avalanche voltage drop of diode Dl.
- the avalanche breakdown voltage of diode Dl is typically in the 5 to 8V range
- the reference voltage produced by such a circuit is in the 6 to 9V range. Since the reference must be driven from a voltage source higher than 6V, Zener references are not suitable for operation in systems which employ 5V or the increasingly popular lower supplies.
- voltage references based upon temperature compensated avalanche diodes tend to be noisy, due to noise generated by the di ⁇ ode's breakdown mechanism.
- Band-gap references provide a temperature-compensated reference which could operate from a lower (e.g. 5V or be- low) supply voltage.
- Band-gap references employ bipolar transistors having emitters of different sizes. Supplying the transistors with equal currents develops a difference in base-emitter voltage ⁇ V BE between the two transistors.
- Such references generally produce an output of the form V BE + ⁇ V BE (A) , where A is a gain factor.
- the V BE and ⁇ V BE compo- nents have opposite polarity temperature coefficients ( ⁇ V BE is proportional to absolute temperature and V BE is comple ⁇ mentary to absolute temperature) which tend to cancel one another out.
- bandgap reference cir ⁇ cuitry Numerous variations in bandgap reference cir ⁇ cuitry have been designed and are discussed, for example, in Fink et al . Ed., Electronics Engineers' Handbook. 3d ed., McGraw-Hill Book Co., 1989, pages 8.48-8.50.
- a bandgap circuit's basic reference voltage ⁇ V BE is developed across a fixed resistor and, because of process variations and other lim ⁇ its upon the accuracy with which an absolute resistance value (as opposed to a ratio of resistances) may be pro- prised, the resistor imparts errors to the voltage refer ⁇ ence.
- Amplification of ⁇ V BE represented by the gain A, introduces further noise into the reference output .
- the use of an absolute resistance further degrades the bandgap reference's performance because the resistor value will drift over time, causing the reference's output to simi ⁇ larly drif .
- the invention seeks to provide a JFET circuit which may be employed, to produce a low-noise voltage reference that is stable over time and temperature and is available in a wide range of voltages. It does this with a pair of junction field effect transistors (JFETs) that are formed with a precisely controlled difference between their pinchoff voltages.
- JFETs junction field effect transistors
- equal size JFETs (i.e. having equal channel width-to-length ratios) are supplied with equal drain currents and their sources are connected to a common voltage. The resulting difference in gate-to- source voltage between them provides a reference voltage.
- This basic circuit may be produced using p-channel or n- channel and enhancement-mode or depletion mode JFETs to provide positive or negative voltage references .
- the tem ⁇ perature coefficient of the reference is linear and, in one implementation, a current source which is proportional to temperature is employed to compensate for the basic refer ⁇ ence's temperature-dependent drift.
- the initial temperature coefficient of the basic two- JFET circuit is relatively low, approximately 100 ppm/°C, and linear. Temperature coefficient compensation is there- fore relatively easy and effective.
- the noise figure for the basic circuit is approximately when operated at a ias current of 6 ⁇ A. This makes it particularly suit ⁇ able for low-noise, low-power applications (the noise fig ⁇ ure may be improved by operating the circuit at a higher bias current) .
- the circuit does not depend upon absolute resistance values, as with bandgap references, and there- f ore avoi d s the introduction of errors due to initial and time-dependent inaccuracies in resistor values.
- the cir ⁇ cuit d oes not exhibit so severe a hysteresis effect as b and-gap references and, unlike Zener references, it may b e used for low-voltage applications, e.g., with a supply voltage of 5V or less.
- the invention also includes a method for producing the JFETs with precisely controlled differences between their pinch-of f voltages to make the reference highly accurate.
- the JFE T s are su b stantially identical except for h eavier ion implantation which alters the pinchoff voltages for some o f the JFETs relative to those that do not receive the heavier implant.
- FIG. l is a schematic diagram of a prior art Zener voltage reference circui .
- FIG.2 is a sectional view of a conventional p-channel JFET .
- FIG.3 is a schematic diagram of a pair of JFETs having dif ⁇ f eren t pinc h off voltages in accordance with the invention.
- FIG . 4 is a schematic diagram of a positive voltage refer ⁇ ence based upon the circuit of FIG.3.
- FI G .5 is a schematic diagram of another positive voltage reference circuit based upon the circuit of FI G .3.
- FIG.s 6 and 7 are schematic diagrams of alternate negative voltage reference circuits in accordance with the inven ⁇ tion.
- FIG.8 is a schematic diagram of the positive voltage refer ⁇ ence circuit shown in FIG.4 with an added temperature com ⁇ pensation.
- FIG.2 is a sectional view of a conventional depletion mode p-channel JFET, which is preferable to an enhancement mode device because of biasing considerations . Further discussion of JFETs will therefore refer to depletion mode devices, but the novel circuit could also employ enhance ⁇ ment mode devices.
- the JFET of FIG.2 is an ion-implanted device having a p-type substrate 10 with an n-type epitaxial tub 12 formed within the substrate 10.
- the n- type tub 12 has p-type source 14 and drain 16 regions dif ⁇ fused within it and a p-type channel 18 between the source 14 and drain 16 regions.
- An n-type top gate 19 is im ⁇ planted over the p-type channel 18. In operation, the gate 19/channel 18 junction is reverse-biased.
- V P a 2 [qN , ,(l + N A /N_,)/2e] - ⁇ 0
- N ⁇ effective channel doping
- the JFET is made of silicon and all device param ⁇ eters will refer to silicon, e.g. e is the dielectric con ⁇ stant of silicon and has the value of 1.04E "12 .
- the built in junction voltage ⁇ 0 is very temperature dependent and highly non-linear: undesirable characteristics for a voltage ref ⁇ erence. This undesirable temperature dependency arises from the built in junction voltage's relation to the JFET intrinsic carrier density:
- ⁇ 0 kT/q ln(N A N D /n x 2 )
- the built-in junction voltage is also highly temperature dependent and non-linear.
- the reference voltage is a function of the difference in pinchoff voltage between two JFETs. That is,
- N A1 is the higher effective channel doping of a first
- JFET N A _, is the lower effective channel doping of a second JFET
- the intrinsic carrier density n. can therefore be eliminated from the expression for the reference voltage by substitut ⁇ ing this expression for ⁇ 0 into that for ⁇ V P :
- N ⁇ and N M must be pre ⁇ cisely controlled.
- a diffusion process does not provide sufficient control of doping levels to produce the neces ⁇ sary precision in channel doping differences.
- An ion i - plantation process provides greater control over channel doping levels than a diffusion process, but this precision is conventionally employed to produce JFETs with precisely matched characteristics, not differences.
- a single step ion-implantation process may be employed to provide the relative channel doping levels set forth above.
- employing a single channel-implantation step to produce precisely-controlled differences in channel doping levels (and therefore in pinchoff voltages) presents daunt ⁇ ing control problems.
- channel doping levels of 1.10 E 12 and 1.25 E 12 are desired to produce a difference in pinchoff voltages corresponding to a dif- ference in doping levels of .15 E 1 .
- the implant process provides 10% accuracy, a single implant step could produce one JFET with 1.10 +.11E 12 and another with 1.25 ⁇ .125 E 12 . Consequently, the differences in channel doping levels could range from -.085 to .385 E 12 clearly an unacceptable result .
- a new two-step channel ion implanta ⁇ tion process is employed in a preferred method to produce the desired difference in pinchoff voltages. That is, the desired difference in channel doping is produced by first producing JFETs using a conventional ion implantation pro ⁇ cess, i.e. one which yields substantially identical channel doping levels. Then a novel second channel implantation is performed on selected JFETs to produce the desired differ- ence in pinchoff voltages. Using the same target figures as in the above example, i.e., doping levels of 1.1 E 12 and 1.25 E 12 , and the same 10% variation in doping accuracy, the new method will produce a much lower variation between tar ⁇ get and actual doping level differences.
- both JFET channels will have channel doping levels of 1.21 E 12 . If, in the worst case, the second channel doping, targeted at .15 E 12 , is also 10% too heavy, one of the JFET channels will be doped to a level of 1.21 E 12 and the other will be doped to a level of 1.375 E 12 , yielding a channel doping level difference of .165 E 12 , much closer to the target val ⁇ ue of .15 E12 than would reliably be provided by a single implantation step.
- a pair of p-channel JFETs are produced using Boron ions accelerated to 180 KeV and im ⁇ planted and driven to a depth of approximately .95 ⁇ m, at a concentration, or "dose", of approximately 1.10 E 12 atoms- /cc.
- Another 180 KeV Boron implant of 0.15E 12 concentration is then performed on the JFET(s) which is to have the high- er pinchoff voltage, yielding a final doping concentration within that JFET of approximately 1.25E 12 atoms/cc.
- the top gates of all the JFETs are then implanted with 150KeV Phos ⁇ phorous driven to a depth of approximately .37 ⁇ m and con ⁇ centration of 1.50E 12 atoms/cc. This combination yields a pinchoff voltage difference between the JFETs of approxi- mately .5V.
- a novel circuit illustrated in FIG. 3, develops a low-noise output voltage having a linear temper ⁇ ature coefficient which may be used, as described in rela- tion to FIGs. 4-7, as a voltage reference.
- the drain current of a JFET is given (approximately) by the following relationship:
- pinchoff voltage an "in ⁇ ternal” device characteristic
- the difference in pinchoff voltages between two JFETs may be converted, for example, to a difference in gate-to-source voltage:
- the difference in gate-to-source voltage should, ideally, be dependent only upon the first two terms on the right of the equation, i.e. ,V pl -V p2 .
- a JFET's saturation drain current I DSS can be expressed as a function of the its channel width-to-length ratio and transconductance, as follows:
- W channel width
- L channel length
- ⁇ transconductance parameter(approximately 7 ⁇ A/V 2 in a preferred implementation)
- I DI /(W : /L.) I D: /(W,/L 2 )
- two JFETs are fabricated with equal channel width-to-length ratios and unequal pinchoff voltages. In operation, the JFETs are provided with equal drain currents.
- Jl and J2 are p-channel depletion mode JFETs fabricated with equal channel width-to-length ratios. Their respective gates GI and G2 are connected to a ground supply and their drains Dl and D2 are connected to a negative supply V' .
- Current sources ID1 and ID2 force equal saturation currents from a positive supply V * into Jl and J , respectively.
- the pinchoff voltage of JFET Jl is higher than that of J2 and, because the JFETs are in satu- raticn, the difference in their pinchoff voltages will be reflected at their source terminals. That is, the differ ⁇ ence in pinchoff voltages equals the difference in gate-to- source voltages. Because their gate voltages are equal, the source terminal of JFET J2 will therefore be ⁇ VP higher than that of Jl .
- a positive voltage reference circuit which employs the novel JFET pair is illustrated by the schematic diagram of FIG.4.
- a pair of p-channel JFETs Jl and J2 have their re ⁇ spective drains Dl and D2 connected to ground GND.
- Their sources SI and S2 are connected to the inverting 22 and noninverting 24 inputs respectively of an op amp 20 and to current sources ID1 and ID2 which provide equal drain- source currents to the JFETs. Since the op amp inputs 22 and 24 will be at substantially the same voltage, current sources IDl and ID2 may be implemented as equal resistors connecting the inputs 22 and 24 to the positive supply V + .
- the pinchoff voltage of J2 is greater than that of Jl .
- the output 25 of the op amp 20 is connected through a series combination of resistors Rl and R2 to a return supply GND.
- resistors Rl and R2 are low temperature coefficient of resistance thin film resistors.
- the gate G2 of J2 is connected to the op amp output 25 and to the "high" side of resistor Rl.
- the gate GI of JFET Jl is connected to the junction 27 of resistors Rl and R2, i.e., the resistor Rl is connected across the gates of JFETs Jl and J2.
- JFETs Jl and J2 have been fabricated in the manner set forth above, i.e. an extra implantation produces a higher pinchoff voltage for J2 than that of Jl and the width-to-length ratios of Jl and J2 are equal. Conse ⁇ quently, with equal drain currents forced through them, their gate-to-source voltages differ by the difference be ⁇ tween their pinchoff voltages and this voltage is impressed across resistor Rl.
- the current through Rl and R2 is ⁇ V P /R1 and the total voltage across Rl and R2, appearing at the output 25 of the op amp 20, will be ⁇ V P (1+R2/R1) .
- the JFETs J l and J 2 must b e operated in saturation, therefore the output reference voltage V REF is greater than the greater of the two JFET pinchoff voltages.
- the circuit of FIG.4 yields a negative voltage reference with an output voltage of - ⁇ V P ( 1+R2/R1 ) .
- the novel JFET pair is also employed in the positive voltage reference of FIG.5.
- P-channel JFETs J3 and J4 are connected from their respective drains D3 and D4 through loads L l and L2 (which could be active loads) to a return supply GND.
- the JFET drains D3 and D4 are also connected, respectively to the inverting 26 and noninverting 28 inputs of an op amp 30.
- the JFET sources S3 and S4 are connected to a current source ID4 and the pinchoff voltage of JFET J4 is higher than that of JFET J3.
- the op amp output 32 pro ⁇ vides the circuit's reference voltage output and is con ⁇ nected through a series combination of resistors R3 and R4 to the return supply GND and to the gate of J .
- the junc- tion 31 of series resistors R3 and R4 is connected to the gate of J3.
- the op amp 30 forces the gate-to-source voltages of J3 and J4 to a level which splits the current from the current source ID4 equally between J3 and J4, thereby maintaining substan- tially equal input voltages at the inverting 26 and noninverting 28 inputs of the op amp 30.
- the difference between VGS4 and VGS3 ( ⁇ V P ) is impressed across resistor R3 and the current through resistors R3 and R4 is ⁇ V P /R3
- the cir- cuit's output reference voltage V REF therefore is
- a negative voltage reference employing novel p-chan ⁇ nel JFETs, is illustrated in the schematic diagram of FIG. 6.
- the drains D5 and D6 of JFETs J5 and J6 are connected to a negative supply V " and their sources S5 and S6 are respectively connected to the inverting 34 and noninverting 36 inputs of an op amp 38.
- Current sources ID5 and ID6 provide equal drain-source currents for the JFETs J5 and J6, and maintain them in saturation.
- the pinchoff voltage of JFET J6 is greater than that of J5.
- Resistors R5 and R6 are connected in series between ground GND and the op amp output 40.
- the junction 39 of series resistors R5 and R6 is connected to the gate of J5.
- the circuit of FIG.7 produces a lower-noise negative voltage reference V RBF , using new p-channel JFETs.
- the pinchoff voltage of JFET J8 is higher than that of JFET J7 and the sources S7 and S8 of JFETs J7 and J8 are connected through a current source ID7 to a ground supply GND.
- the drains D8 and D7 of J8 and J7 are connected respectively through equal loads L3 and L4 (L3 and L4 could be active loads) to a negative supply V " ,and directly to the inverting 42 and noninverting 44 inputs of an op amp 46.
- a voltage divider composed of resistors R7 and R8 connected in series spans the op amp output 48 and the ground supply GND.
- the junction 43 of the resistors R7 and R8 is connected to the gate of JFET J7.
- the op amp 46 establishes a voltage at its output 48 such that the gate-Co-source voltage of J7 steers equal currents through J7 and J8, thus maintaining equal voltages at its inputs 42 and 44. Since the op amp 46 maintains equal drain currents through J7 and J8, the difference between their pinchoff voltages will appear across R7 and the current through R7 and R8 will equal - ⁇ V P /R7.
- the output reference voltage therefore equals - ⁇ V P (I+R8/R7) .
- a positive reference may also be produced by substituting n-channel JFETs for the p-channel devices and reversing the current sources.
- FIG.s 4-7 yield voltage references having temperature coefficients of approximately -120ppm/°C. This figure is orders of magnitude less than for an uncom- pensated Vbe used in bandgap references, and several times lower than the figure for a Zener reference, but it is still too high for many applications. Because this temper ⁇ ature coefficient is linear and relatively small, it may be readily compensated by introducing a temperature compensa ⁇ tion current Ic, as illustrated in FIG.8 (an implementation based upon the circuit of FIG. ) . All components of FIG.8 are identical to those of FIG.4, with the exception that a compensation resistor Re has been added between resistor R2 and ground.
- the compensation current has a positive tem ⁇ perature coefficient of 120 ppm/ D C and may be developed from a ⁇ Vbe source, for example.
- the compensation current Ic develops a positive temperature coefficient voltage across the compensation resistor RC which cancels the negative temperature coefficient of the basic reference circuit .
- the compensation resistor RC may optionally be eliminated, with the compensation current injected at the junction of resistors Rl and R2.
- the compensation circuit should be biased so that Ic does not alter the reference voltage out ⁇ put V REF .
- enhancement mode JFETs may be used, with proper biasing, to effect the circuits disclosed above.
- Parameters other than the drain cur ⁇ rents may be forced, e.g.
- gate-to-source voltages may be forced to be equal, with a resultant difference in drain currents used as a reflection of the difference in pinchoff voltage between the JFETs.
- the embodiments were chosen and described in order to best explain the principles of the invention and its practical application, to thereby enable others skilled in the art to best utilize the invention. It is intended that the scope of the invention be limited only by the claims appended hereto.
Abstract
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Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
AU18352/97A AU1835297A (en) | 1996-01-17 | 1997-01-16 | Junction field effect voltage reference and fabrication method |
EP97903908A EP0875025B1 (en) | 1996-01-17 | 1997-01-16 | Junction field effect voltage reference and fabrication method |
DE69736827T DE69736827T2 (en) | 1996-01-17 | 1997-01-16 | VOLTAGE REFERENCE WITH BARRIER FIELD EFFECT AND MANUFACTURING METHOD |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US08/587,548 US5838192A (en) | 1996-01-17 | 1996-01-17 | Junction field effect voltage reference |
US08/587,548 | 1996-01-17 |
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WO1997026591A1 true WO1997026591A1 (en) | 1997-07-24 |
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PCT/US1997/001007 WO1997026591A1 (en) | 1996-01-17 | 1997-01-16 | Junction field effect voltage reference and fabrication method |
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US (2) | US5838192A (en) |
EP (1) | EP0875025B1 (en) |
AU (1) | AU1835297A (en) |
DE (1) | DE69736827T2 (en) |
WO (1) | WO1997026591A1 (en) |
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JP3832943B2 (en) * | 1997-10-15 | 2006-10-11 | 沖電気工業株式会社 | Constant current source circuit and digital / analog conversion circuit using the same |
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US6121824A (en) * | 1998-12-30 | 2000-09-19 | Ion E. Opris | Series resistance compensation in translinear circuits |
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JP3831894B2 (en) * | 2000-08-01 | 2006-10-11 | 株式会社ルネサステクノロジ | Semiconductor integrated circuit |
US6483372B1 (en) | 2000-09-13 | 2002-11-19 | Analog Devices, Inc. | Low temperature coefficient voltage output circuit and method |
US6362613B1 (en) * | 2000-11-13 | 2002-03-26 | Gain Technology Corporation | Integrated circuit with improved current mirror impedance and method of operation |
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US6503782B2 (en) * | 2001-03-02 | 2003-01-07 | Mississippi State University Research And Technology Corporation (Rtc) | Complementary accumulation-mode JFET integrated circuit topology using wide (>2eV) bandgap semiconductors |
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JP2003273657A (en) * | 2002-03-18 | 2003-09-26 | Mitsubishi Electric Corp | Bias circuit and a/d converter |
US7116253B2 (en) * | 2003-08-05 | 2006-10-03 | Stmicroelectronics N.V. | Radio frequency digital-to-analog converter |
US7368980B2 (en) * | 2005-04-25 | 2008-05-06 | Triquint Semiconductor, Inc. | Producing reference voltages using transistors |
US7408400B1 (en) * | 2006-08-16 | 2008-08-05 | National Semiconductor Corporation | System and method for providing a low voltage bandgap reference circuit |
US7688117B1 (en) | 2008-04-21 | 2010-03-30 | The United States Of America As Represented By The Administrator Of National Aeronautics And Space Administration | N channel JFET based digital logic gate structure |
JP5250501B2 (en) * | 2009-08-04 | 2013-07-31 | ルネサスエレクトロニクス株式会社 | Temperature detection circuit |
JP5012886B2 (en) * | 2009-12-25 | 2012-08-29 | 株式会社デンソー | Semiconductor device and manufacturing method thereof |
CN102393783A (en) * | 2011-10-19 | 2012-03-28 | 四川和芯微电子股份有限公司 | Current source circuit and system with high-order temperature compensation |
DE102014100984B4 (en) | 2014-01-28 | 2019-03-14 | Phoenix Contact Gmbh & Co. Kg | Measuring device for redundantly detecting an input voltage |
US10120405B2 (en) | 2014-04-04 | 2018-11-06 | National Instruments Corporation | Single-junction voltage reference |
US10409312B1 (en) * | 2018-07-19 | 2019-09-10 | Analog Devices Global Unlimited Company | Low power duty-cycled reference |
US11271566B2 (en) * | 2018-12-14 | 2022-03-08 | Integrated Device Technology, Inc. | Digital logic compatible inputs in compound semiconductor circuits |
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1996
- 1996-01-17 US US08/587,548 patent/US5838192A/en not_active Expired - Lifetime
-
1997
- 1997-01-16 WO PCT/US1997/001007 patent/WO1997026591A1/en active IP Right Grant
- 1997-01-16 AU AU18352/97A patent/AU1835297A/en not_active Abandoned
- 1997-01-16 EP EP97903908A patent/EP0875025B1/en not_active Expired - Lifetime
- 1997-01-16 DE DE69736827T patent/DE69736827T2/en not_active Expired - Lifetime
-
1998
- 1998-09-22 US US09/158,691 patent/US5973550A/en not_active Expired - Lifetime
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4068134A (en) * | 1975-06-16 | 1978-01-10 | Hewlett-Packard Company | Barrier height voltage reference |
US4176368A (en) * | 1978-10-10 | 1979-11-27 | National Semiconductor Corporation | Junction field effect transistor for use in integrated circuits |
US4267501A (en) * | 1979-06-21 | 1981-05-12 | Motorola, Inc. | NMOS Voltage reference generator |
US4427903A (en) * | 1980-06-24 | 1984-01-24 | Nippon Electric Co., Ltd. | Voltage current converter circuit |
US4816880A (en) * | 1986-06-05 | 1989-03-28 | Nissan Motor Co., Ltd. | Junction field effect transistor |
US5424663A (en) * | 1993-04-22 | 1995-06-13 | North American Philips Corporation | Integrated high voltage differential sensor using the inverse gain of high voltage transistors |
Non-Patent Citations (1)
Title |
---|
See also references of EP0875025A4 * |
Also Published As
Publication number | Publication date |
---|---|
EP0875025A4 (en) | 1999-12-15 |
US5838192A (en) | 1998-11-17 |
AU1835297A (en) | 1997-08-11 |
EP0875025A1 (en) | 1998-11-04 |
EP0875025B1 (en) | 2006-10-18 |
DE69736827T2 (en) | 2007-03-01 |
US5973550A (en) | 1999-10-26 |
DE69736827D1 (en) | 2006-11-30 |
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