WO1997044904A1 - Microcontroller with firmware selectable oscillator trimming - Google Patents

Microcontroller with firmware selectable oscillator trimming Download PDF

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Publication number
WO1997044904A1
WO1997044904A1 PCT/US1997/008185 US9708185W WO9744904A1 WO 1997044904 A1 WO1997044904 A1 WO 1997044904A1 US 9708185 W US9708185 W US 9708185W WO 9744904 A1 WO9744904 A1 WO 9744904A1
Authority
WO
WIPO (PCT)
Prior art keywords
oscillator
microcontroller
voltage
providing
trimming data
Prior art date
Application number
PCT/US1997/008185
Other languages
French (fr)
Inventor
Richard L. Hull
Gregory Bingham
Original Assignee
Microchip Technology, Inc.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Microchip Technology, Inc. filed Critical Microchip Technology, Inc.
Priority to JP9542519A priority Critical patent/JPH11514766A/en
Priority to DE69714824T priority patent/DE69714824T2/en
Priority to KR1019980700515A priority patent/KR100301567B1/en
Priority to EP97926506A priority patent/EP0840955B1/en
Publication of WO1997044904A1 publication Critical patent/WO1997044904A1/en

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Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K17/00Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/16Modifications for eliminating interference voltages or currents
    • H03K17/161Modifications for eliminating interference voltages or currents in field-effect transistor switches
    • H03K17/162Modifications for eliminating interference voltages or currents in field-effect transistor switches without feedback from the output circuit to the control circuit
    • H03K17/163Soft switching
    • H03K17/164Soft switching using parallel switching arrangements
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03LAUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00Automatic control of frequency or phase; Synchronisation
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/04Generating or distributing clock signals or signals derived directly therefrom
    • G06F1/08Clock generators with changeable or programmable clock frequency
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F15/00Digital computers in general; Data processing equipment in general
    • G06F15/76Architectures of general purpose stored program computers
    • G06F15/78Architectures of general purpose stored program computers comprising a single central processing unit
    • G06F15/7807System on chip, i.e. computer system on a single chip; System in package, i.e. computer system on one or more chips in a single package
    • G06F15/7814Specially adapted for real time processing, e.g. comprising hardware timers
    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K3/00Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/023Generators characterised by the type of circuit or by the means used for producing pulses by the use of differential amplifiers or comparators, with internal or external positive feedback
    • H03K3/0231Astable circuits
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02DCLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A microcontroller circuit (10) includes an oscillator (14) receiving frequency trimming data (28) from a memory (16) under control of a microcontroller logic (12). The microcontroller logic (12) permits a user to alter the trimming data and to select through an oscillator logic (20) either the oscillator (14) or an external oscillator source (34) as a system clock (32).

Description

MICROCONTROLLER WITH FIRMWARE SELECTABLE OSCILLATOR TRIMMING
RELATED APPLICATION
This patent application is related to pending U.S patent application entitled "Accurate RC Oscillator,M having serial number 08/499,602 and a filing date of July 7, 1995, in the name of Russell E. Cooper as inventor, and is incorporated herein by reference. This patent application is also related to pending U.S patent application entitled "Accurate RC Oscillator Having Peak-to- Peak Voltage Control and Method Therefor," and filed in the names of Russell Cooper and Scott Ellison as inventors, and is incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
This invention is in the field of microcontrollers and methods therefor and, more particularly, is a microcontroller having firmware selectable oscillator trimming and a method therefore.
2. Description of the Related Art
In the past, most microcontroller users would rely on external oscillators to provide an accurate clock signal to the microcontroller. This approach has the advantage of yielding an accurate clock signal to the microcontroller, however it has the inherent disadvantages of higher costs associated with using an external clock source and inefficient use of space since an external oscillator and its associated components are required in addition to the microcontroller. Thus, it would be advantageous both in terms of cost reduction and space savings to have an oscillator internal to the microcontroller chip itself, but those skilled in the art know that process variations inherent in the manufacturing procedure for the microcontroller chip typically yield oscillators on the chip that have imprecise output clock frequency.
Therefore, there existed a need to provide a microcontroller having an internal RC oscillator circuit which provides a clock signal for use by the microcontroller that can be modified, as desired, by firmware selectable oscillator trimming of the clock signal frequency and a method therefor.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a microcontroller having an internal oscillator supplying a clock signal to the microcontroller and a method therefor.
Another object of the present invention is to provide a microcontroller with firmware selectable oscillator trimming of the oscillator clock signal and a method therefor.
BRIEF DESCRIPTION OF THE PREFERRED EMBODIMENTS
According to the present invention, a microcontroller circuit having firmware selectable oscillator trimming is disclosed comprising, in combination, a microcontroller, oscillator means located within the microcontroller for providing a system clock signal for the microcontroller, and memory means coupled to the oscillator means for providing signals to the oscillator means for trimming frequency of the system clock. The microcontroller circuit further includes microcontroller logic means having trimming data stored therein for providing the trimming data to the memory means. The microcontroller logic means also includes oscillator control means therein for selecting between use of the oscillator means internal to the microcontroller for the system clock and use of an external oscillator source for the system clock.
The microcontroller circuit also includes oscillator logic means coupled to the microcontroller logic means, to the oscillator means, and to the external oscillator source for providing, in response to receipt of a signal from the oscillator control means, the system clock to the microcontroller from one of the oscillator means and the external oscillator source. The memory means comprises Static Random Access Memory (SRAM) having control register means for storing the trimming data and supplying the trimming data to the oscillator means. SRAM address, Data, Read, and Write lines are located between the microcontroller logic means and the SRAM. Additionally, the microcontroller circuit includes a plurality of lines coupling the control register means with the oscillator means for transferring the trimming data to the osc a or means. e m crocon ro er c rcu ur e trimming data adjustment means within the microcontroller logic means for altering the trimming data after the trimming data has been transferred to the memory means.
As an alternative embodiment, a method of operating a microcontroller circuit having firmware selectable oscillator trimming is disclosed comprising the steps of providing a microcontroller, providing a system clock signal to the microcontroller from oscillator means located within the microcontroller, and providing memory means coupled to the oscillator means for providing signals to the oscillator means for trimming frequency of the system clock. The method further includes the step of providing microcontroller logic means having trimming data stored therein for providing the trimming data to the memory means. The step of providing the microcontroller logic means also includes the step of providing oscillator control means therein for selecting between use of the oscillator means internal to the microcontroller for the system clock and use of an external oscillator source for the system clock.
The method further includes the step of providing oscillator logic means coupled to the microcontroller logic means, to the oscillator means, and to the external oscillator source for providing, in response to receipt of a signal from the oscillator control means, the system clock to the microcontroller from one of the oscillator means and the external oscillator source. The step of providing the memory means comprises the step of providing Static Random Access Memory (SRAM) having control register means for storing the trimming data and supplying the trimming data to the oscillator means. SRAM address, Data, Read, and Write lines are provided between the microcontroller logic means and the SRAM. The method also includes the step of providing a plurality of lines coupling the control register means with the oscillator means for transferring the trimming data to the oscillator means. The method further includes the step of providing trimming data adjustment means within the microcontroller logic means for altering the trimming data after the trimming data has been transferred to the memory means.
The foregoing and other objects, features, and advantages of the invention will be apparent from the following, more particular, description of the preferred embodiments of the invention, as illustrated in the accompanying drawing.
BRIEF DESCRIPTION OF THE DRAWING
Fig. 1 is a simplified block diagram view of the microcontroller with firmware selectable oscillator trimming of the instant invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to Figure 1, the microcontroller circuit having firmware selectable oscillator trimming (hereinafter simply referred to as microcontroller) is shown and designated by general reference number 10. Microcontrollers are well known in the art. Most microcontrollers use an external clock source because they are inherently accurate, as compared to providing an internal oscillator, which is inherently accurate, for use by the microcontroller. The instant invention uses an oscillator 14 located within the microcontroller 10 for providing a system clock signal over line 32 to the microcontroller 10. Oscillators are well known in the art; however, providing an oscillator with an accurate clock signal on a microcontroller chip is not well known. Despite being located within the microcontroller 10, oscillator 14 does provide an a precise clock signal, and the structure and operation of oscillator 14 is discussed in detail in pending U.S. patent application entitled "Accurate RC Oscillator Having Peak-to- Peak Voltage Control and Method Therefor."
The microcontroller 10 also includes a memory portion (SRAM) 16 coupled to the oscillator 14 for providing signals to the oscillator 14 for trimming frequency of the system clock. Note that other types of volatile memory could be implemented in lieu of the SRAM 16. A microcontroller logic portion 12 is also included within the microcontroller 10, and it has trimming data 22 stored therein for providing the trimming data 22 to the memory portion 16. In general, microcontroller logic portion 12 includes logic well known in the art to accomplish basic microcontroller functions. In addition, microcontroller logic portion 12 has a dedicated non-volatile memory location for storing the trimming data 22. The trimming data 22 is determined empirically upon fabrication of the microcontroller 10 to achieve a desired frequency of the clock s gnal from osc a or or a g ven se o temperature, voltage, and process variation conditions. In other words, after fabrication of the microcontroller 10, it is tested at various temperatures and voltages, and with the physical variations of the internals of the chip associated with fabrication, to determine what value of trimming data 22 will achieve the desired clock frequency. This value is located within the microcontroller logic portion 12. The microcontroller logic portion 12 also includes an oscillator control portion 24 therein for selecting between use of the oscillator 14 and an external oscillator source 34 for the system clock. The oscillator control portion 24 consists of a non-volatile bit within the microcontroller logic portion 12 set with appropriate data for selecting the desired source for the system clock.
The microcontroller 10 also includes an oscillator logic portion 20 for providing, in response to receipt of a signal from the oscillator control portion 24, the system clock to the microcontroller 10 from either the oscillator 14 or the external oscillator source 34. Logic to accomplish the task of the oscillator logic portion 20 is well known to those skilled in the art; however, while the logic to accomplish this task is well known, the particular function performed by the oscillator logic portion 20, in the context of microcontroller 10, is unique.
As previously noted, the memory portion 16 comprises Static Random Access Memory (SRAM) . The SRAM 16 has a control register portion 18 for storing the trimming data 22 and supplying the trimming data 22 to the oscillator 14. The microcontroller 10 further includes SRAM address, Data, Read, and Write lines between the microcontroller logic portion 12 and the SRAM 16. Additionally, a plurality of lines 28 couple the control register portion 18 with the oscillator 14 for transferring the trimming data 22 to the oscillator 14. The microcontroller logic portion 12 further includes a trimming data adjustment portion 26 for permitting a user to alter the trimming data 22 after it has been transferred to the SRAM 16. In practice, a user would take adjustment data provided by the manufacturer to meet the temperature and voltage conditions of his or her application and apply this data to the microcontroller logic portion 12 which would deliver this adjustment data to the SRAM 16 to modify the trimming data 22 accordingly. Logic to accomplish this function is well known to those skilled in the art; however, the practice of adjusting trimming data 22 transferred from the microcontroller logic portion 12 into SRAM 16 is unique.
OPERATION
Again referring to Figure 1, a user obtains from the manufacture a microcontroller 10 having the trimming data 22 and oscillator control portion 24 set in firmware, as desired. In particular, the user obtains a microcontroller 10 having trimming data 22 set in firmware which is appropriate for the user's application with respect to temperature and voltage conditions, and the process variations associated with the microcontroller 10 itself. Likewise, the user selects a microcontroller 10 having the appropriate data set in firmware for the oscillator control portion 24 such that the user can provide the system clock to the microcontroller 10 from either oscillator 14 or the external oscillator source 34, as desired.
Upon appropriate command, well known in the art, from the user, the oscillator control portion 24 provides a signal over line 30 to the oscillator logic portion 20 to select the source for the system clock from either the oscillator 14 or the external oscillator source 34. Thereafter, the system clock is provided from the output of the oscillator logic portion 20 for use by the microcontroller 10.
Again, upon appropriate command, well known in the art, from the user, the trimming data 22 is transferred from the microcontroller logic portion 12 to the SRAM 16, and more particularly into the control register portion 18. The trimming data 22 in the control register portion 18 is automatically fed to the oscillator 14 over lines 28. As previously mentioned, the particular operation of oscillator 14 is described in pending U.S. patent application entitled "Accurate RC Oscillator Having Peak-to- Peak Voltage Control and Method Therefor," however, note that operation of the oscillator 14 with the trimming data 22 transferred therein yields a substantially precise system clock frequency in spite of the fact that oscillator 14 is integral to the microcontroller 10 chip. The aforementioned loading of trimming data 22 into the oscillator 14 assumes that the user is satisfied with the value of trimming data 22 in firmware of the microcontroller logic portion 12. This is not always the case. A user may want to adjust the operating frequency of the system clock by trimming a small amount, or even by changing the frequency by a large amount. Accordingly, the microcontroller logic portion 12 further includes a trimming data adjustment portion 26 for permitting a user to alter the trimming data 22 after it has been transferred into the SRAM 16. In practice, a user would take adjustment data provided by the manufacturer to meet the temperature and voltage conditions of his or her application and, using commands well known to those skilled in the art, apply this data to the microcontroller logic portion 12 which would deliver this adjustment data to the SRAM 16 to modify the trimming data 22 accordingly. Last, note that communication protocol over the SRAM Address, Data, Read, and Write lines is well known to those skilled in the art, and therefore, the particulars of transferring data, whether it be trimming data 22, data from the trimming data adjustment portion 26, or otherwise, between the microcontroller logic portion 12 and the SRAM 16 are well known to those skilled in the art.
Although the invention has been particularly shown and described with reference to a preferred embodiment thereof, it will be understood by those skilled in the art that changes in form and detail may be made therein without departing from the spirit and scope of the invention.

Claims

What is Claimed is:
1. A microcontroller circuit having firmware selectable oscillator trimming comprising, in combination: a microcontroller; oscillator means located within said microcontroller for providing a system clock signal for said microcontroller; and memory means coupled to said oscillator means for providing signals to said oscillator means for trimming frequency of said system clock.
2. The microcontroller circuit of Claim 1 further including microcontroller logic means having trimming data stored therein for providing said trimming data to said memory means.
3. The microcontroller circuit of Claim 2 wherein said microcontroller logic means also includes oscillator control means therein for selecting between use of said oscillator means internal to said microcontroller for said system clock and use of an external oscillator source for said system clock.
4. The microcontroller circuit of Claim 3 further including oscillator logic means coupled to said microcontroller logic means, to said oscillator means, and to said external oscillator source for providing, in response to receipt of a signal from said oscillator control means, said system clock to said microcontroller from one of said oscillator means and said external oscillator source.
5. The microcontroller circuit of Claim 2 wherein said memory means comprises Static Random Access Memory (SRAM) having control register means for storing said trimming data and supplying said trimming data to said oscillator means.
6. The microcontroller circuit of Claim 5 further including SRAM address, data, read, and write lines between said microcontroller logic means and said SRAM.
7. The microcontroller circuit of Claim 5 further including a plurality of lines coupling said control register means with said oscillator means for transferring said trimming data to said oscillator means.
8. The microcontroller circuit of Claim 1 wherein said memory means is located within said microcontroller.
9. The microcontroller circuit of Claim 2 further including trimming data adjustment means within said microcontroller logic means for altering said trimming data after said trimming data has been transferred to said memory means.
10. A method of operating a microcontroller circuit having firmware selectable oscillator trimming comprising the steps of: providing a microcontroller; providing a system clock signal to said microcontroller from oscillator means located within said microcontroller; and providing memory means coupled to said oscillator means for providing signals to said oscillator means for trimming frequency of said system clock.
11. The method of Claim 10 further including the step of providing microcontroller logic means having trimming data stored therein for providing said trimming data to said memory means.
12. The method of Claim 11 wherein said step of providing said microcontroller logic means also includes the step of providing oscillator control means therein for selecting between use of said oscillator means internal to said microcontroller for said system clock and use of an external oscillator source for said system clock.
13. The method of Claim 12 further including the step of providing oscillator logic means coupled to said microcontroller logic means, to said oscillator means, and to said external oscillator source for providing, in response to receipt of a signal from said oscillator control means, said system clock to said microcontroller from one of said oscillator means and said external oscillator source.
14. The method of Claim 11 wherein said step of providing said memory means comprises the step of providing Static Random Access Memory (SRAM) having control register means for storing said trimming data and supplying said trimming data to said oscillator means.
15. The method of Claim 14 further including the step of providing SRAM address, data, read, and write lines between said microcontroller logic means and said SRAM.
16. The method of Claim 14 further including the step of providing a plurality of lines coupling said control register means with said oscillator means for transferring said trimming data to said oscillator means.
17. The method of Claim 10 wherein said memory means is located within said microcontroller.
18. The method of Claim 11 further including the step of providing trimming data adjustment means within said microcontroller logic means for altering said trimming data after said trimming data has been transferred to said memory means.
19. A microcontroller circuit having firmware selectable oscillator trimming comprising, in combination: a microcontroller; oscillator means located within said microcontroller for providing a system clock signal for said microcontroller; memory means coupled to said oscillator means for providing signals to said oscillator means for trimming frequency of said system clock; microcontroller logic means having trimming data stored therein for providing said trimming data to said memory means; said microcontroller logic means also including oscillator control means therein for selecting between use of said oscillator means internal to said microcontroller for said system clock and use of an external oscillator source for said system clock; oscillator logic means coupled to said microcontroller logic means, to said oscillator means, and to said external oscillator source for providing, in response to receipt of a signal from said oscillator control means, said system clock to said microcontroller from one of said oscillator means and said external oscillator source; said memory means comprising Static Random Access Memory (SRAM) having control register means for storing said trimming data and supplying said trimming data to said oscillator means; and trimming data adjustment means within said microcontroller logic means for altering said trimming data after said trimming data has been transferred to said memory means.
AMENDED CLAIMS
[received by the International Bureau on 16 September 1997 (16.09.97); original claims 1, 10 and 19 amended; remaining claims unchanged (12 pages)]
1. A microcontroller circuit having firmware selectable oscillator trimming comprising, in combination: a microcontroller; oscillator means located within said microcontroller for providing a system clock signal for said microcontroller wherein said oscillator means generating an oscillatory signal of a predetermined frequency across a series resistor-capacitor (RC) network by ensuring that the oscillatory signal accurately oscillates between first and second voltages generated from a supply voltage source where the frequency of oscillation is determined by both the time constant of the RC network and the difference between the first and second voltages, said oscillator means comprising, in combination: charging-discharging means for discharging a voltage across the capacitor commencing when voltage of the oscillatory signal exceeds a first threshold voltage and for charging said voltage across the capacitor commencing when voltage of the oscillatory signal falls below a second threshold voltage; first sampling means coupled to said charging- discharging means for obtaining a first sampled voltage of the oscillatory signal upon commencement of discharging of said voltage across the capacitor; first compensation means coupled to said first sampling means for adjusting said first threshold voltage to be the first voltage modified by a voltage difference between the first voltage and said first sampled voltage; second sampling means coupled to said charging- discharging means for obtaining a second sampled voltage of the oscillatory signal upon commencement of charging of said voltage across the capacitor; second compensation means coupled to said second sampling means for adjusting said second threshold voltage to be the second voltage modified by a voltage difference between the second voltage and said second sampled voltage; and differential voltage setting means coupled to said second compensation means for selecting the second voltage from a plurality of different possible voltages and thereby selecting a voltage difference between the first and second voltages; and memory means coupled to said oscillator means for providing signals to said oscillator means for trimming frequency of said system clock.
2. The microcontroller circuit of Claim 1 further including microcontroller logic means having trimming data stored therein for providing said trimming data to said memory means.
3. The microcontroller circuit of Claim 2 wherein said microcontroller logic means also includes oscillator control means therein for selecting between use of said oscillator means internal to said microcontroller for said system clock and use of an external oscillator source for said system clock.
4. The microcontroller circuit of Claim 3 further including oscillator logic means coupled to said microcontroller logic means, to said oscillator means, and to said external oscillator source for providing, in response to receipt of a signal from said oscillator control means, said system clock to said microcontroller from one of said oscillator means and said external oscillator source.
5. The microcontroller circuit of Claim 2 wherein said memory means comprises Static Random Access Memory (SRAM) having control register means for storing said trimming data and supplying said trimming data to said oscillator means.
6. The microcontroller circuit of Claim 5 further including SRAM address, data, read, and write lines between said microcontroller logic means and said SRAM.
7. The microcontroller circuit of Claim 5 further including a plurality of lines coupling said control register means with said oscillator means for transferring said trimming data to said oscillator means.
8. The microcontroller circuit of Claim 1 wherein said memory means is located within said microcontroller.
9. The microcontroller circuit of Claim 2 further including trimming data adjustment means within said microcontroller logic means for altering said trimming data after said trimming data has been transferred to said memory means.
10. A method of operating a microcontroller circuit having firmware selectable oscillator trimming comprising the steps of: providing a microcontroller; providing a system clock signal to said microcontroller from oscillator means located within said microcontroller, said oscillator means generating an oscillatory signal of a predetermined frequency across a series resistor-capacitor (RC) network by ensuring that the oscillatory signal accurately oscillates between first and second voltages generated from a supply voltage source where the frequency of oscillation is determined by both the time constant of the RC network and the difference between the first and second voltages, said oscillator means comprising, in combination: charging-discharging means for discharging a voltage across the capacitor commencing when voltage of the oscillatory signal exceeds a first threshold voltage and for charging said voltage across the capacitor commencing when voltage of the oscillatory signal falls below a second threshold voltage; first sampling means coupled to said charging- discharging means for obtaining a first sampled voltage of the oscillatory signal upon commencement of discharging of said voltage across the capacitor; first compensation means coupled to said first sampling means for adjusting said first threshold voltage to be the first voltage modified by a voltage difference between the first voltage and said first sampled voltage; second sampling means coupled to said charging- discharging means for obtaining a second sampled voltage of the oscillatory signal upon commencement of charging of said voltage across the capacitor; second compensation means coupled to said second sampling means for adjusting said second threshold voltage to be the second voltage modified by a voltage difference between the second voltage and said second sampled voltage; and differential voltage setting means coupled to said second compensation means for selecting the second voltage from a plurality of different possible voltages and thereby selecting a voltage difference between the first and second voltages; and providing memory means coupled to said oscillator means for providing signals to said oscillator means for trimming frequency of said system clock.
11. The method of Claim 10 further including the step of providing microcontroller logic means having trimming data stored therein for providing said trimming data to said memory means.
12. The method of Claim 11 wherein said step of providing said microcontroller logic means also includes the step of providing oscillator control means therein for selecting between use of said oscillator means internal to said microcontroller for said system clock and use of an external oscillator source for said system clock.
13. The method of Claim 12 further including the step of providing oscillator logic means coupled to said microcontroller logic means, to said oscillator means, and to said external oscillator source for providing, in response to receipt of a signal from said oscillator control means, said system clock to said microcontroller from one of said oscillator means and said external oscillator source.
14. The method of Claim 11 wherein said step of providing said memory means comprises the step of providing Static Random Access Memory (SRAM) having control register means for storing said trimming data and supplying said trimming data to said oscillator means.
15. The method of Claim 14 further including the step of providing SRAM address, data, read, and write lines between said microcontroller logic means and said SRAM. 16. The method of Claim 14 further including the step of providing a plurality of lines coupling said control register means with said oscillator means for transferring said trimming data to said oscillator means.
17. The method of Claim 10 wherein said memory means is located within said microcontroller.
18. The method of Claim 11 further including the step of providing trimming data adjustment means within said microcontroller logic means for altering said trimming data after said trimming data has been transferred to said memory means.
19. A microcontroller circuit having firmware selectable oscillator trimming comprising, in combination: a microcontroller; oscillator means located within said microcontroller for providing a system clock signal for said microcontroller wherein said oscillator means generating an oscillatory signal of a predetermined frequency across a series resistor-capacitor (RC) network by ensuring that the oscillatory signal accurately oscillates between first and second voltages generated from a supply voltage source where the frequency of oscillation is determined by both the time constant of the RC network and the difference between the first and second voltages, said oscillator means comprising, in combination: charging-discharging means for discharging a voltage across the capacitor commencing when voltage of the oscillatory signal exceeds a first threshold voltage and for charging said voltage across the capacitor commencing when voltage of the oscillatory signal falls below a second threshold voltage; first sampling means coupled to said charging- discharging means for obtaining a first sampled voltage of the oscillatory signal upon commencement of discharging of said voltage across the capacitor; first compensation means coupled to said first sampling means for adjusting said first threshold voltage to be the first voltage modified by a voltage difference between the first voltage and said first sampled voltage; second sampling means coupled to said charging- discharging means for obtaining a second sampled voltage of the oscillatory signal upon commencement of charging of said voltage across the capacitor; second compensation means coupled to said second sampling means for adjusting said second threshold voltage to be the second voltage modified by a voltage difference between the second voltage and said second sampled voltage; and differential voltage setting means coupled to said second compensation means for selecting the second voltage from a plurality of different possible voltages and thereby selecting a voltage difference between the first and second voltages memory means coupled to said oscillator means for providing signals to said oscillator means for trimming frequency of said system clock; microcontroller logic means having trimming data stored therein for providing said trimming data to said memory means; said microcontroller logic means also including oscillator control means therein for selecting between use of said oscillator means internal to said microcontroller for said system clock and use of an external oscillator source for said system clock; oscillator logic means coupled to said microcontroller logic means, to said oscillator means, and to said external oscillator source for providing, in response to receipt of a signal from said oscillator control means, said system clock to said microcontroller from one of said oscillator means and said external oscillator source; said memory means comprising Static Random Access Memory (SRAM) having control register means for storing said trimming data and supplying said trimming data to said oscillator means; and trimming data adjustment means within said microcontroller logic means for altering said trimming data after said trimming data has been transferred to said memory means.
PCT/US1997/008185 1996-05-24 1997-05-21 Microcontroller with firmware selectable oscillator trimming WO1997044904A1 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
JP9542519A JPH11514766A (en) 1996-05-24 1997-05-21 Microcontroller with firmware selectable oscillator trimming
DE69714824T DE69714824T2 (en) 1996-05-24 1997-05-21 MICROCONTROLLER WITH A SYSTEM FOR THE TRIMMER-SELECTABLE TRIMMING OF AN OSCILLATOR
KR1019980700515A KR100301567B1 (en) 1996-05-24 1997-05-21 Microcontroller with Firmware-Selectable Oscillator Trimming
EP97926506A EP0840955B1 (en) 1996-05-24 1997-05-21 Microcontroller with firmware selectable oscillator trimming

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US08/644,914 US5796312A (en) 1996-05-24 1996-05-24 Microcontroller with firmware selectable oscillator trimming
US08/644,914 1996-05-24

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WO1997044904A1 true WO1997044904A1 (en) 1997-11-27

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PCT/US1997/006482 WO1997045959A1 (en) 1996-05-24 1997-04-12 Microcontroller having a minimal number of external components
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EP (1) EP0840955B1 (en)
JP (1) JPH11514766A (en)
KR (1) KR100301567B1 (en)
DE (1) DE69714824T2 (en)
TW (1) TW344046B (en)
WO (2) WO1997045959A1 (en)

Families Citing this family (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6211739B1 (en) 1997-06-03 2001-04-03 Cypress Semiconductor Corp. Microprocessor controlled frequency lock loop for use with an external periodic signal
US6294962B1 (en) 1998-12-09 2001-09-25 Cypress Semiconductor Corp. Circuit(s), architecture and method(s) for operating and/or tuning a ring oscillator
US6191660B1 (en) 1999-03-24 2001-02-20 Cypress Semiconductor Corp. Programmable oscillator scheme
US6396317B1 (en) 1999-05-28 2002-05-28 Peco Ii, Inc., Digital voltage controlled oscillator
GB2351619A (en) 1999-07-01 2001-01-03 Ericsson Telefon Ab L M A frequency trimmable oscillator with insensitivity to power supply variations and parasitic capacitance
US6946920B1 (en) 2000-02-23 2005-09-20 Cypress Semiconductor Corp. Circuit for locking an oscillator to a data stream
US6297705B1 (en) 2000-02-23 2001-10-02 Cypress Semiconductor Corp. Circuit for locking an oscillator to a data stream
US6407641B1 (en) 2000-02-23 2002-06-18 Cypress Semiconductor Corp. Auto-locking oscillator for data communications
US7171542B1 (en) * 2000-06-19 2007-01-30 Silicon Labs Cp, Inc. Reconfigurable interface for coupling functional input/output blocks to limited number of i/o pins
US6745338B1 (en) * 2000-09-12 2004-06-01 Cypress Semiconductor Corp. System for automatically selecting clock modes based on a state of clock input pin and generating a clock signal with an oscillator thereafter
US7093151B1 (en) 2000-09-22 2006-08-15 Cypress Semiconductor Corp. Circuit and method for providing a precise clock for data communications
US7660998B2 (en) * 2002-12-02 2010-02-09 Silverbrook Research Pty Ltd Relatively unique ID in integrated circuit
JP2005049970A (en) * 2003-07-30 2005-02-24 Renesas Technology Corp Semiconductor integrated circuit
TWI289977B (en) * 2003-09-17 2007-11-11 Genesys Logic Inc Frequency lock method for ultra-wide band, and the associated devices thereof
JP2006039830A (en) * 2004-07-26 2006-02-09 Renesas Technology Corp Semiconductor integrated circuit
US7498891B2 (en) * 2005-10-18 2009-03-03 Stmicroelectronics Pvt. Ltd. Method for calibration of an oscillator for a microcontroller chip operation
US7809973B2 (en) * 2005-11-16 2010-10-05 Cypress Semiconductor Corporation Spread spectrum clock for USB
US8035455B1 (en) 2005-12-21 2011-10-11 Cypress Semiconductor Corporation Oscillator amplitude control network
US8564252B2 (en) * 2006-11-10 2013-10-22 Cypress Semiconductor Corporation Boost buffer aid for reference buffer
US8035401B2 (en) * 2007-04-18 2011-10-11 Cypress Semiconductor Corporation Self-calibrating driver for charging a capacitive load to a desired voltage
US8449483B2 (en) * 2008-12-02 2013-05-28 Patrick Eddy Compression device and control system for applying pressure to a limb of a living being
US8364870B2 (en) 2010-09-30 2013-01-29 Cypress Semiconductor Corporation USB port connected to multiple USB compliant devices
TWI446141B (en) 2010-11-09 2014-07-21 Nuvoton Technology Corp A calibration method and apparatus for clock signal and an electronic device
US9667240B2 (en) 2011-12-02 2017-05-30 Cypress Semiconductor Corporation Systems and methods for starting up analog circuits
US20130329464A1 (en) * 2012-06-06 2013-12-12 System General Corp. Digital power control circuit for power converter and control circuit for power converter
TWI491172B (en) * 2012-06-28 2015-07-01 Holtek Semiconductor Inc Oscillator apparatus embedded in chip
US10551428B2 (en) * 2016-08-25 2020-02-04 Microchip Technology Incorporated Systems and methods for storing frequency information for system calibration/trimming
US10324714B2 (en) * 2017-05-23 2019-06-18 Qualcomm Incorporated Apparatus and method for trimming parameters of analog circuits including centralized programmable ALU array

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4964141A (en) * 1987-04-15 1990-10-16 Nec Corporation Serial data processor capable of transferring data at a high speed
US5036300A (en) * 1989-07-07 1991-07-30 Sgs-Thomson Microelectronics S.A. Integrated circuit with microprocessor and programmable internal clock
US5272650A (en) * 1990-09-25 1993-12-21 Honeywell Inc. Self correcting time base for inaccurate oscillators
US5583819A (en) * 1995-01-27 1996-12-10 Single Chip Holdings, Inc. Apparatus and method of use of radiofrequency identification tags

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH03284122A (en) * 1990-03-28 1991-12-13 Mitsumi Electric Co Ltd Power supply voltage monitoring circuit
JPH04267620A (en) * 1991-02-22 1992-09-24 Nec Corp Triangle wave oscillation circuit
US5323067A (en) * 1993-04-14 1994-06-21 National Semiconductor Corporation Self-disabling power-up detection circuit

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4964141A (en) * 1987-04-15 1990-10-16 Nec Corporation Serial data processor capable of transferring data at a high speed
US5036300A (en) * 1989-07-07 1991-07-30 Sgs-Thomson Microelectronics S.A. Integrated circuit with microprocessor and programmable internal clock
US5272650A (en) * 1990-09-25 1993-12-21 Honeywell Inc. Self correcting time base for inaccurate oscillators
US5583819A (en) * 1995-01-27 1996-12-10 Single Chip Holdings, Inc. Apparatus and method of use of radiofrequency identification tags

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of EP0840955A4 *

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KR19990035854A (en) 1999-05-25
TW344046B (en) 1998-11-01
EP0840955B1 (en) 2002-08-21
WO1997045959A1 (en) 1997-12-04
JPH11514766A (en) 1999-12-14
KR100301567B1 (en) 2001-10-29
DE69714824T2 (en) 2003-05-28
EP0840955A1 (en) 1998-05-13
US5796312A (en) 1998-08-18
DE69714824D1 (en) 2002-09-26
EP0840955A4 (en) 1998-12-23

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