WO1998006139A1

WO1998006139A1 - Non-volatile storage cell

Info

Publication number: WO1998006139A1
Application number: PCT/DE1997/001600
Authority: WO
Inventors: Hans Reisinger; Reinhard Stengl; Hermann Wendt; Josef Willer; Volker Lehmann; Martin Franosch; Herbert Schäfer; Wolfgang Krautschneider; Franz Hofmann; Ulrike GRÜNING
Original assignee: Siemens Aktiengesellschaft
Priority date: 1996-08-01
Filing date: 1997-07-29
Publication date: 1998-02-12
Also published as: DE19631147C2; JP2000515325A; TW335555B; KR20000035785A; EP0916161A1; DE19631147A1

Abstract

The invention concerns a non-volatile write-once storage cell comprising a MOS transistor which, as gate dielectric, has a triple dielectric layer consisting of a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53). The first silicon oxide layer (51) and the second silicon oxide layer (53) are each at least 3 nm thick. The storage cell is not erasable and can hold data for a period of more than 1000 years.

Description

description

Non-volatile memory cell.

Non-volatile memory cells, so-called SONOS or MNOS cells, each comprising a special MOS transistor, have been proposed for the permanent storage of data (see, for example, Lai et al. IEDM Tech. Dig. 1986, pages 580 to 583). The MOS transistor comprises a gate dielectric which comprises at least one silicon nitride layer below the gate electrode and a SiO 2 layer between the silicon nitride layer and the channel region. Charge carriers are stored in the silicon nitride layer to store the information.

The thickness of the SiO ₂ layer in these non-volatile memory cells is a maximum of 2.2 nm. The thickness of the silicon nitride layer in modern SONOS memory devices is usually about 10 nm. A further SiO 2 layer is usually provided between the silicon nitride layer and the gate electrode. which has a thickness of 3 to 4 nm. These non-volatile memory cells can be electrically written and erased. During the writing process, such a voltage is applied to the gate electrode that charge carriers tunnel out of the substrate through the maximum 2.2 nm thick SiO 2 layer into the silicon nitride layer. For deletion, the gate electrode is wired in such a way that the charge carriers stored in the silicon nitride layer tunnel through the 2.2 nm thick SiO ₂ layer in the channel region and from the channel region, charge carriers of the opposite conductivity type tunnel through the SiO 2 layer into the silicon nitride layer.

The memory cells described, which are often referred to as SONOS cells, have a data retention time of <10 years. This time is too short for many applications, for example for storing data in computers. For applications in which longer times are required for data retention, it is known to use EEPROM cells with a floating gate as the non-volatile memory. In these memory cells, for example from Lai et al, IEDM Tech. Dig. 1986, pages 580 to 583, a floating gate electrode is arranged between a control gate electrode and the channel region of the MOS transistor, which is completely surrounded by dielectric material. The information is stored in the form of charge carriers on the floating gate electrode. These memory cells, which are also referred to as FLOTOX cells, can be electrically written and erased. For this purpose, the control gate electrode is connected to such a potential that charge carriers flow from the channel area onto the floating gate electrode (writing) or charge carriers flow from the floating gate electrode into the channel area (erase). These FLOTOX cells have data retention times greater than 150 years.

Compared to the SONOS cells, however, they are complicated to set up. Furthermore, the space requirement of the FLOTOX cells is greater in comparison to the SONOS cells, since the control gate electrode has to overlap the floating gate electrode laterally. Finally, the so-called radiation hardness of FLOTOX cells is limited. Radiation hardness refers to the insensitivity of the stored charge to external radiation sources and / or electromagnetic fields.

The invention is based on the problem of specifying a non-curse memory cell which has a data retention time of at least 150 years, which is simple in structure and can be integrated in a high packing density and which has improved radiation hardness in comparison with the FLOTOX cells having. This problem is solved according to the invention by a memory cell according to claim 1. Further configurations emerge from the subclaims.

The non-volatile memory cell comprises a MOS transistor with source region, channel region, drain region, gate dielectric and gate electrode, which has a dielectric triple layer as the gate dielectric. The dielectric triple layer comprises a first silicon oxide layer, a silicon nitride layer and a second silicon oxide layer. The silicon nitride layer is arranged between the two silicon oxide layers. The first silicon oxide layer and the second silicon oxide layer each have a thickness of at least 3 nm.

The thicknesses of the first silicon oxide layer and the second silicon oxide layer in the memory cell according to the invention are chosen so that they differ by an amount in the range between 0.5 and 1 nm. The smaller of the two thicknesses of the first silicon oxide layer and the second silicon oxide layer is in the range between 3 and 5 nm. The thickness of the silicon nitride layer is at least 5 nm. The MOS transistor has a gate electrode made of n ⁺ -doped silicon. In this memory cell, the dielectric triple layer is electrically symmetrical. Due to the different thicknesses of the first silicon oxide layer and the second silicon oxide layer, the work function differences between the channel region and the gate electrode and mainly the generally positive gate voltage applied during reading operation are taken into account.

The memory cell according to the invention differs from conventional SONOS cells in that the first silicon oxide layer, which is arranged between the channel region of the MOS transistor and the silicon nitride layer, has a thickness of at least 3 nm. In conventional SONOS cells, this thickness is a maximum of 2.2 nm. The invention makes use of the knowledge that in conventional SONOS cells the charge is transported through the first silicon oxide layer mainly via direct tunneling and modified Fowler-Nordheim tunneling. The tunnel probability for direct tunneling and modified Fowler-Nordheim tunneling and thus the current intensity for the transport of charge carriers through direct tunneling and modified Fowler-Nordheim tunneling depends mainly on the thickness of the tunnel barrier, that is, the thickness of the first silicon oxide layer, and on the electrical one Field. Since in conventional SONOS cells the first silicon oxide layer has a maximum thickness of 2.2 nm and the second silicon oxide layer is 3 to 4 nm thick, the current by direct tunneling through the first silicon oxide layer always prevails in electrical fields below 10 MV / cm. Via this direct tunnel current and modified Fowler-Nordheim tunneling, the writing as well as the deletion of the information takes place by appropriate wiring of the gate electrode.

The invention also makes use of the knowledge that even without connecting the gate electrode in conventional SONOS cells, a tunnel current, which is due to direct tunneling, flows through the first silicon oxide layer from the silicon nitride layer to the channel region. It was found that this direct tunnel current is decisive for the time for the data retention.

Furthermore, the invention makes use of the knowledge that the tunneling probability for direct tunneling decreases sharply with increasing thickness of the first silicon oxide layer and becomes very small with a thickness of at least 3 nm, by several (approximately 3) orders of magnitude smaller than at 2 nm.

Since the first silicon oxide layer and the second silicon oxide layer are each at least 3 nm thick in the memory cell according to the invention, a layer is stored in this memory cell. Manure carrier transport from the silicon nitride layer to the gate electrode or to the channel area largely avoided by direct tunneling. This means that the charge stored in the silicon nitride layer remains practically indefinitely. The time for data retention in the memory cell according to the invention is therefore significantly longer than in conventional SONOS cells, more than 1000 years instead of 10 years.

Since the thicknesses of the first silicon oxide layer and the second silicon oxide layer are each at least 3 nm, the tunnel probability for direct tunneling of charge carriers through the two silicon oxide layers is very small. A charge carrier transport through the first silicon oxide layer or second silicon oxide layer takes place during writing and reading only through Fowler-Nordheim tunnels.

The current intensity of the charge carrier transport through Fowler-Nordheim tunnels only depends on the strength of the applied electric field. It is not explicitly dependent on the thickness of the tunnel barrier, that is to say the thickness of the first silicon oxide layer or second silicon oxide layer.

Since the dielectric triple layer is electrically symmetrical, the Fowler-Nordheim tunneling of electrons dominates charge carrier transport regardless of the polarity of the applied field. This means that both when a positive voltage is applied and when a negative voltage is applied to the gate electrode, Fowler-Nordheim tunneling of electrons into the silicon nitride layer. If a positive voltage is present at the gate electrode, electrons tunnel from the channel region through the first silicon oxide layer into the silicon nitride layer. If, however, there is a negative voltage at the gate electrode, electrons tunnel through the second silicon oxide layer into the silicon nitride layer through Fowler-Nordheim tunnels from the gate electrode. Since the probability of direct tunneling through the first silicon oxide layer and the second silicon oxide layer is very small in this memory cell, and since electrons are transported into the silicon nitride layer through Fowler-Nordheim tunnels regardless of the polarity at the gate electrode, this memory cell cannot be erased. Information once written into the memory cell cannot be deleted again. The time for data retention in the memory cell is more than 1000 years.

A gate voltage of typically + 12 V is applied to write information into this memory cell. A gate voltage of typically + 3 V is applied to read the information.

If the memory cell is to be operated with a positive read voltage, the first silicon oxide layer has a smaller thickness than the second silicon oxide layer. If the memory cell is to be operated with a negative read voltage, the second silicon oxide layer has a smaller thickness than the first silicon oxide layer.

As is generally customary, the memory cell is integrated in memory cell arrangements which have a plurality of identical memory cells in the form of a matrix.

Since the memory cell does not have a floating gate electrode, its radiation hardness is greater than that for comparable FLOTOX cells. The MOS transistor in the memory cell can be designed both as a planar and as a vertical MOS transistor.

The invention is explained in more detail below with the aid of the exemplary embodiments and the figures.

Figure 1 shows a memory cell with a planar MOS transistor. Figure 2 shows a memory cell with a vertical MOS transistor.

A source region 2 and a drain region 3, which are n-doped, for example, are provided in a substrate 1, which comprises monocrystalline silicon at least in the region of a memory cell. A channel region 4 is arranged between the source region 2 and the drain region 3. Source region 2, channel region 4 and drain region 3 are arranged next to one another on the surface of the substrate 1. A dielectric triple layer 5 is arranged above the channel region 4 and comprises a first SiO ₂ layer 51, an Si3N ₄ layer 52 and a second SiO ₂ layer 53. The first SiO ₂ layer 51 is arranged on the surface of the channel region 4 and has a thickness of 3 to 6 nm, preferably 4 nm. The Si3N4 layer 52 is arranged on the surface of the first SiO 2 layer 51. It has a thickness of at least 5 nm, preferably 8 nm. The second SiO 2 layer 53 is arranged on the surface of the Si _{3 4} layer 52, whose thickness is 0.5 to 1 nm greater than the thickness of the first SiO 2 layer 51, that is to say in the range between 3.5 and 6 nm, preferably 4.5 to 5 nm.

A gate electrode 6 made of, for example, n-doped polysilicon is arranged on the surface of the dielectric triple layer 5. The gate electrode 6 has a thickness of, for example, 200 nm and a dopant concentration of, for example, 10 ²¹ cm ^"3 .

A semiconductor layer structure 11 made of, for example, monocrystalline silicon comprises a source region 12, a channel region 14 and a drain region 13 in vertical succession (see FIG. 2). The source region 12 and the drain region 13 are, for example, n-doped with a dopant concentration of 10 ²⁰ cm ^"3. The channel region 14 is, for example, p-doped with a dopant concentration of 10 ¹⁷ cm ^-3 Source region 12, drain region 13 and channel region 14 have a common flank 110, which preferably extends perpendicularly or slightly inclined to the surface of the semiconductor layer structure 1. The flank 110 can be both the flank of a trench or a step in a substrate and the flank of a raised structure, for example a mesa structure.

A dielectric triple structure 15 is arranged on the flank 110 and comprises a first SiO 2 layer 151, an Si3N ₄ layer 152 and a second SiO 2 layer 153. The surface of the second SiO 2 layer 153 is covered with a gate electrode 16. The gate electrode 16 is formed, for example, in the form of a spacer made of n-doped polysilicon or metal, for example aluminum. The second SiO 2 ~

Layer 153 has a thickness of, for example, 3 to 5 nm, preferably 4 nm. The Si ₃ N ₄ layer 152 has a thickness of at least 5 nm, preferably 8 nm. The first SiO 2 layer 151 is 0.5 to 1 nm thicker than the second SiO 2 layer 153, that is to say it has a thickness between 3.5 and 6 nm. It preferably has a thickness of 4.5 nm. The thicknesses of the first SiO ₂ layer 151, the Si ₃ N ₄ layer 152 and the second SiO 2 layer 153 are each measured perpendicular to the flank 110.

Claims

claims

1. non-volatile memory cell,

with a MOS transistor which has a dielectric triple layer (5) with a first silicon oxide layer (51), a silicon nitride layer (52) and a second silicon oxide layer (53) as gate dielectric,

the difference between the thicknesses of the first silicon oxide layer (51) and the second silicon oxide layer (53) is in the range between 0.5 nm and 1 nm,

- In which the smaller of the thicknesses of the first silicon oxide layer (51) and the second silicon oxide layer (53) in

Range between 3 nm and 5 nm,

in which the thickness of the silicon nitride layer is at least 5 nm,

in which the MOS transistor has a gate electrode (6) made of n-doped silicon.