WO1998008156A1

WO1998008156A1 - Digital circuit arrangement

Info

Publication number: WO1998008156A1
Application number: PCT/EP1997/003354
Authority: WO
Inventors: Heinz Loreck; Carsten Merz
Original assignee: Itt Manufacturing Enterprises, Inc.
Priority date: 1996-08-16
Filing date: 1997-06-26
Publication date: 1998-02-26
Also published as: DE19633013B4; DE19633013A1

Abstract

In a digital, clock-controlled circuit arrangement, the disturbing radiation caused by the working clock pulse (fT) is reduced by modulating the clock frequency (fFM). The circuit arrangement is divided into circuit parts (3, 16) which require a highly accurate clock frequency (fT) and into circuit parts (1, 18) with a high disturbing radiation potential. The circuit parts (3, 16) with high accuracy requirements are driven with a non-modulated clock pulse (fT), the remaining circuit parts (1, 18) are driven with a frequency-modulated clock pulse (fFM). The circuit parts driven with the non-modulated clock pulse and the circuit parts driven with the modulated clock pulse are interconnected by a communication circuit (5, 8, 20).

Description

Digital circuit arrangement

The invention relates to a digital, clock-controlled circuit arrangement in which the interference radiation, which is caused by the operating cycle or by the clocking, is reduced by modulating the clock frequency.

Such a circuit arrangement is described, for example, in US Pat. No. 4,695,808. Such digital circuits, which are operated with a predetermined, stable clock, are known to cause interference signals with integer multiples of the basic frequency of the operating clock, which are narrow-band and can assume relatively high amplitudes. In order to expand the energy of this interference radiation to a wider frequency spectrum and thereby reduce the amplitude of the interference signal, the frequency of the clock signal or clock signal is modulated. However, this measure stands in the way that in a microprocessor and also in other digital circuits of this type, the most accurate possible system clock of a predetermined basic frequency is required for the data exchange and the interaction of the individual switching groups with one another.

The invention is therefore based on the object of reconciling the two aforementioned, contradictory requirements for a high-precision, narrow-band clock signal or power cycle on the one hand and for distribution of the radiated interference energy over a wider frequency band, which could be achieved by frequency modulation.

It has been found that this problem can be solved by the circuit arrangement described in claim 1, the special feature of which is that a division of the Circuit arrangement in circuit parts with high demands on the accuracy of the clock frequency and in circuit parts with high interference radiation potential is provided that the circuit parts with high accuracy requirements, the work cycle or a clock derived from the work cycle is supplied unmodulated and the other circuit parts are supplied with a modulated clock and that one There is a communication circuit which connects the circuit parts operated with the unmodulated clock to the other circuit parts connected to the modulated clock.

According to an advantageous exemplary embodiment of the invention, a buffer memory that can be written to and read from two sides is provided as the communication circuit, via which data is transmitted from a time standard supplied with an unmodulated clock to a logic circuit supplied with a frequency-modulated clock, and in the opposite direction. According to the invention, a phase comparison or synchronization circuit can also be used as the communication circuit, which allows data to be transmitted only at times of sufficiently matching frequency or phase position between the unmodulated and the modulated clock.

Finally, it is still possible and in many cases advantageous to use a synchronization circuit as the communication circuit, which extends the time range of sufficient correspondence between the frequencies or phase positions of the non-modulated and of the modulated clock and in turn only permits data transmission in the times of sufficient correspondence.

The invention is based on the knowledge that in a digital circuit of the type in question only certain circuit parts with the precise clock frequency should be operated, while other circuit parts, from which in practice the greater part of the interference emanates, can be operated with the frequency-modulated clock, if an asynchronous data exchange or a temporary synchronization is made possible in the communication between the individual circuit parts.

The circuit arrangement according to the invention thus allows both working with high accuracy requirements in the time domain and also effective damping or reduction of the interference radiation by distributing the interference energy over a relatively broad frequency band.

Further details, possible applications and advantages of the invention will become apparent from the following description of exemplary embodiments with reference to the attached figures.

Show it:

1 is a block diagram to illustrate the basic operation of a circuit arrangement according to the invention,

Fig. 2 in the same representation another

Embodiment of a circuit arrangement according to the invention,

3A, 3B are diagrams for explaining further embodiments of the invention and

4 likewise in a block diagram and schematically simplified further details of the circuit arrangement according to FIG. 1. Fig. 1 serves to explain the basic operation of the invention. Only the essential components or functions of the circuit are shown symbolically.

A digital, clock-controlled circuit arrangement according to the invention is composed of circuit parts 1, which are operated with a clock generator 2, and of circuit parts 3, which are connected to a second clock generator 4. Communication between the circuit parts 1 and 3 takes place with the aid of a communication circuit 5, which in some way has to compensate for the control of the circuit parts 1 and 3 with different clock sources (2, 4). The circuit principle according to the invention can be applied to microprocessors or microcomputers and also to other digital circuit arrangements.

The clock source 4 supplies the circuit parts 3, which here represent "time standards", with an unmodulated, precisely predetermined operating clock f _τ . Modulation of this clock is out of the question. The remaining circuit parts 1, which can include, for example, the entire logic of a microcomputer or a control circuit, place significantly lower demands on the clock accuracy. The clock generator 2 for the logic 1 therefore generates a frequency-modulated clock with the frequency f _fH . This frequency modulation significantly reduces the interference. Since in practice in logic 1 or in circuit parts 1 the largest part of the interference emission of the entire digital circuit occurs and the time standard (circuit part 3) only contributes to the interference to a small extent, by far the largest part of the interference source is detected by frequency modulation.

The modulated clock f _FH and the unmodulated clock f _τ from sources 2 and 4 are of course derived from a common source (see FIG. 4), which is a synchronization facilitated.

In the case of digital circuits of the type in question, communication or data exchange between the circuit parts 1 and 3 is required. In spite of the different clock frequencies f _FM and f _τ a

To enable communication, a buffer memory 5, for example a so-called dual port RAM, can be written to and read from two sides in the exemplary embodiment according to FIG. 1. The circuit parts 1 and 3 can communicate asynchronously via this buffer memory 5.

In Fig. 1, the buses over which data and the data clock are transmitted are numbered 6 and 7. The two circuit parts 1 and 3 can communicate asynchronously via these buses.

Another example of the data exchange between the circuit parts 1 and 3 is shown in FIG. 2. In this example, a phase comparison device 8 is provided, which constantly compares the clock frequencies f _FM and f _τ and one

Data exchange via a data bus 9 only allows at times when the frequencies or phase positions of the two sources 2 and 4 match sufficiently precisely. The work cycle is also transmitted via bus 9.

FIG. 3A, which shows the course of the frequency over time, symbolizes that the frequency-modulated signal f ™ periodically coincides with the unmodulated frequency f _τ , so that a data exchange takes place in the times t ₁₀ , t ₁₁ , t ₁ identified by a circle can take place via the data bus 9 in FIG. 2.

A variant of the synchronization method, to which FIG. 3A relates, is illustrated by FIG. 3B. It exists basically the possibility of extending the time range for the data transmission by the action of the comparison or synchronization device on the frequency modulator, with which the frequency-modulated clock f _{FH is} obtained from the clock with the frequency f _τ . By acting on the frequency modulator - see FIG. 3 B - a time range "t ₁₃ to t ₁₄ " is created in which there is a sufficiently precise correspondence between the frequencies or phase positions of the two signals with the frequencies f _FH and f _τ . However, such a measure, namely the expansion of the time range, depending on the duration of the sufficient match between the two signals, can result in a corresponding increase or extension in the interference emission.

Finally, FIG. 4 shows further details of a digital circuit arrangement of the type in question here, for example the circuit according to FIG. 1.

4, a frequency-stable oscillator circuit 15 is provided to generate the operating cycle, which generates the unmodulated clock f _τ (or a multiple of this clock). This clock f _τ is fed to the circuit parts 16, which place high demands on the frequency stability and accuracy. The output signal of the oscillator circuit 15, which has the clock frequency f _τ , is also fed via a frequency modulator 17 to those circuit parts 18 which make the higher or decisive part of the interference radiation and which can be operated with a modulated clock f _FM without impairing the data processing. This

Circuit parts 18 represent in practice the actual jammer, the interference radiation is reduced to the permissible level by the frequency modulation. The unmodulated system clock f _τ is used for the

4 via a timer 19 to the logic 18, for example a microcomputer.

As has already been explained with reference to FIG. 1, a communication or synchronization circuit 20 is necessary in order to enable the necessary data exchange between the circuit parts 16 and 18. The device 20 symbolizes either a buffer memory (compare buffer memory 5 in FIG. 1) or a phase comparison or phase influencing device which always allows data transmission when there is a sufficiently precise match of the frequency or phase position between the frequency-modulated clock and the unmodulated clock.

Finally, FIG. 4 also shows data buses 21, 22, 23, signal transmission lines 24, 25, 26 for transmitting the modulated clock (24), a modulator control signal (26) and for signaling matching phase positions (25); these are some of the transmission lines known to be required in such digital circuits.

Claims

claims

1. Digital, clock-controlled circuit arrangement in which the interference radiation caused by the clocking is reduced by modulating the clock frequency, characterized in that a division into circuit parts (3, 16) with high demands on the accuracy of the clock frequency (f _τ ) and in

Circuit parts (1, 18) with high

Störausstrahlungspotential is envisaged that the circuit parts (3, 16) with high accuracy requirements of the working clock (f _τ), or a group derived from the clock frequency (f _τ) clock supplied unmodulated and the remaining

Circuit parts (1, 18) are supplied with a modulated clock (f _FM ) and that a communication circuit (5, 8, 20) is present via which the circuit parts (3, 16) operated with the unmodulated clock (f _τ ) with the others , connected to the modulated clock (f _Ff vj)

Circuit parts (1,18) are connected.

2. Circuit arrangement according to claim 1, characterized in that a two-page readable and readable buffer memory (5, 20), for example a dual port RAM, is provided as the communication circuit, via which data is supplied by one with an unmodulated clock (f _τ )

Time standards (3.18) are transmitted to a logic circuit (1.18) supplied with frequency-modulated clock (f _FM ) and in the opposite direction. Circuit arrangement according to Claim 1, characterized in that a phase comparison or synchronization circuit (8) is provided as the communication circuit, which only permits data transmission between the unmodulated and the modulated clock at times of a sufficiently matching frequency or phase position.

Circuit arrangement according to claim 1, characterized in that a synchronization circuit (8) is provided as the communication circuit, which has the time range sufficient correspondence (t _{1 () (11 12} , t ₁₃ to t ₁₄ ) between the frequency or phase position of the unmodulated and the modulated Clock lengthened and the frequency or phase position allows data transmission only at times of sufficient agreement ( ^t _lθ , ιι _I2 r ^t i _{3 to} ³ t ₁₄ ).