WO1998013968A1

WO1998013968A1 - Device, system and method for adaptive self-noise cancellation for decision directed timing recovery

Info

Publication number: WO1998013968A1
Application number: PCT/US1997/016935
Authority: WO
Inventors: Jian Yang
Original assignee: Motorola Inc.
Priority date: 1996-09-24
Filing date: 1997-09-19
Publication date: 1998-04-02
Also published as: AU4649297A

Abstract

In a data receiver (18) which periodically samples at predefined sample points a received analog signal and produces therefrom a digital output, an adaptive self-noise cancellation timing recovery circuit (26) includes: a self-noise canceller (44), responsive to the samples and the digital output, for adaptively approximating the self-noise component of the samples and for removing the approximated self-noise component from the samples to produce substantially self-noise free samples; a timing error generator (42), responsive to the self-noise free samples and the digital output, for generating a timing error signal proportional to sampling deviations from the predefined sample points of the data receiver; and a control device (40), responsive to the timing error signal, for controlling the sampling phase of the data receiver to eliminate the sampling deviations.

Description

DEVICE, SYSTEM AND METHOD FOR ADAPTIVE SELF- NOISE CANCELLATION FOR DECISION DIRECTED TIMING

RECOVERY

FIELD OF INVENTION

This invention relates to adaptive self-noise cancellation for decision directed timing recovery and more particularly for such noise cancellation in timing recovery in modems used for data communications over the public switched telephone network (PSTN).

BACKGROUND OF INVENTION

The PSTN consists of a digital backbone network and analog local loops that connect users to this backbone. In a typical telephone call, the analog signal sent by the local user is digitized at the local central office and converted into a 64 kbit/s bitstream which is carried across the digital backbone network and then converted back to analog at the remote central office for delivery to the remote user over the remote local loop. Dial-up modems communicate over the PSTN by modulating the digital information into an analog signal for transmission. The digital-to-analog conversion process described above introduces quantization noise which limits the data transmission speed to around 30 kbit/s. ISDN is a circuit-switched public network which allows end-to-end digital communication using 64 kbit/s circuits. When an ISDN user communicates with a PSTN user, the analog information generated at the ISDN site is converted into a 64 kbit/s bitstream in an ISDN terminal adapter, in the same manner the central office digitizes an analog signal that originates at a PSTN site. Besides ISDN, a PSTN end-point can also be reached using other forms of digital access. For example, medium-to-large size corporations often use T1 lines to access the PSTN. Regardless of the digital access medium, the traditional method of converting the modem signal into a 64 kbit/s bitstream limits the achievable modem speed to around 30 kbit/s.

There is therefore a need for a system and method of communication between users having a digital connection to the telephone network and users connected to the network by an analog loop at higher transmission rates while avoiding the requirement of specialized and expensive infrastructure.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic block diagram of data communications system used for transmission of data over the PSTN; FIG. 1A is a schematic block diagram of the sampler of FIG. 1 ;

FIG. 1 B is a schematic diagram of another configuration of the sampler of FIG. 1 ; FIG. 2 is a schematic block diagram of the timing recovery circuit of FIG. 1 configured according to this invention;

FIG. 3 is a schematic block diagram of the timing error estimator of FIG. 2; FIG. 4 is a schematic block diagram of a conventional timing error generator of FIG, 3;

FIG. 5 is a plot of a PAM signal and its component impulses;

FIG. 6 is a plot of one of the component impulses of FIG. 5 with properly taken sample points;

FIG. 7 is a plot of the component impulse of FIG. 6 with the sample points taken too early;

FIG. 8 is a plot of the component impulse of FIG. 6 with the sample points taken too late; FIG. 9 is a schematic block diagram of the timing error generator of FIG. 3 configured according to this invention;

FIG. 10 is schematic block diagram of the self-noise canceller of FIG. 3 according to this invention;

FIG. 11 is schematic block diagram of an alternative self-noise canceller according to this invention; and

FIG. 12 is a schematic block diagram of the NCO of FIG. 2. DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

A technique that allows transmission at speeds significantly higher than 30 kbit/s, when one user has a direct connection to a digital network, for example, via ISDN or T1 has been developed and is described in co-pending applications entitled Device, System and Method for Spectrally Shaping Transmitted Data Signals (CX096044); System and Device for, and Method of Processing Baseband Signals to Combat ISI and Non-linearities in a Communication System (CX096046); and System and Device for, and Method of Detecting,

Characterizing, and Mitigating Deterministic Distortion in a Communications Network (CX096047) assigned to the assignee of the instant invention. These co-pending applications are incorporated herein in their entireties by reference. With this technique, random digital information is encoded into μ-law or A-law octets, depending on the region of the world, using a channel encoder and then the octets are mapped directly into levels in the digital-to-analog (D/A) converter located in the remote user's central office. The mapping could use all of or any subset of the 256 levels of the D/A converter, subject to regulatory restrictions on average power. Since information is carried across the digital network in the form of octets, the encoded data is first mapped into μ- law (outside of North America, A-law ) octets for transmission at a rate of 8000 octets per second, and then in the remote user's central office these octets are converted into the desired amplitude levels in the D/A converter. The resulting 8 kHz sequence of levels is then passed through a low pass filter (LPF) and sent over the analog loop to the remote user. The output of the D/A converter can be viewed as a sequence of impulses each having an amplitude corresponding to one of the D/A levels. At the remote end, a receiving modem recovers the original information by first detecting which D/A levels were transmitted, and then inverse mapping these to obtain an estimate of the original digital information. This technique theoretically enables the transmission of data at 64kbps, however, with actual system constraints, acheiving transmission rates of 48kbps to 56kpbs is more pragmatic. These transmission rates are a significant improvement over the once thought theoretical limit of about 35kbps. The analog impulses are typically filtered and output every T seconds (1/8Khz) over the analog loop to the receiving modem. Received by the modem is a pulse amplitude modulated (PAM) signal which consists of a plurality of impulses on the loop. In order for the receiving modem to decode the data accurately after transmission over the channel, the PAM signal must be sampled at the proper points on the impulse every T/2 seconds so that each impulse can be interpreted. This is accomplished by feedback means known as timing recovery. Unfortunately, the impulses are not discrete, but rather, generally a number of impulses are overlapping. This impulse overlap is referred to as self-noise or intersymbol interference (ISI) which makes timing recovery more difficult. The sampled signal is then equalized to remove the ISI introduced to the signal by the channel, and decoded by, for example, a Viterbi decoder.

A properly sampled impulse is sampled at a controlled point, such as at its peak. From the sampled voltage the m-law level is determined and from the μ-law level the digital information the level represents is ascertained by the decoder. To determine if the impulses are being properly sampled, e.g. at their peaks, they are also sampled at other sample points (timing sample points), e.g. on either side of the peaks, and these sample points are compared to determine if proper sampling is occurring. If the impulses are being sampled improperly, i.e. too early or too late, the impulses are not sampled at their controlled point (the peak) and are therefore improperly decoded.

With some conventional timing recovery schemes, the equalizer output and the decoder output or decisions are utilized by a timing error generator to generate a timing error signal. The equalizer is designed to optimize decoding reliability typically by means of a long adaptive feedforward filter section. This is especially true for systems involving trellis coding. A problem with these schemes is that since the equalizer output is fed back to the timing recovery circuit an adverse interaction between the equalizer and the timing recovery circuit is introduced. More specifically, perturbations in the equalizer feedforward taps alter the impulse shape and thus shift the sampling points causing the timing recovery circuit to compensate for these shifts by adjusting the sampling phase. Since the timing recovery loop is coupled with the adaptation of the equalizer, this causes unwanted timing clock jitter which adversely effects the performance of the timing loop and reduces the accuracy of data detection.

In many conventional applications the level of timing clock jitter introduced by the above timing recovery scheme is acceptable. With this amount of jitter, sampling accuracy within approximately one tenth of a period T is achievable.

However, with the high rate transmission technique described in this and the co-pending applications referred to above there is a need for improved sampling accuracy which conventional timing recovery schemes are not capable of providing. The timing recovery scheme according to this invention which provides the necessary improved sampling accuracy is described below.

There is shown in FIG. 1 data communications system 10 which includes digital transmitter 12, directly connected to the digital telephone network 14. Digital transmitter 12 encodes, as described in the copending applications, digital data to be transmitted by grouping bits of information, correlating each group with a μ-law octet representing the group and transmitting the octet over digital network 14. The digital data from network 14 is received at the telephone company central office 16 where each octet is converted to a voltage level by a μ-law to linear converter. The voltage levels are filtered and transmitted as impulses every T seconds over analog loop 17. The signal on line 17 consisting of a plurality of impulses, the PAM signal, is provided to modem 18. In modem 18 the PAM signal is sampled by sampler 20 at a multiple of the impulse transmission frequency and the samples are provided over line 21 to an adaptive equalizer 22, which may be a fractionally spaced partial response linear equalizer. Adaptive equalizer 22 removes the self-noise or intersymbol interference introduced by the channel. The equalized signals are then provided over line 23 to a decoder circuit 24, such as a Viterbi decoder or any other suitable type of decoder, which outputs a digital data stream over line 25 that is a reproduction of the transmitted digital data. The decoding process is described in more detail in the co-pending applications referred to above.

Timing recovery circuit 26 uses the output of decoder 24, also referred to as the decisions, and the unequalized received signal samples from sampler 20 to generate a control or clock signal provided over line 27 to adjust the sampling phase of sampler 20. Timing recovery schemes which utilize the decoder output to generate the timing error signal, such as with the present scheme, are referred to as decision directed timing recovery. The control signal derives from an error signal which, as described below, is related to the levels of the timing sample points, e.g.. the ones taken before and after the controlled (or decoder) sample point. In the example described below, the timing sample points are the points taken on either side of the controlled or peak sample point of each impulse.

Sampler 20 may be configured as shown in FIG. 1A with a switch 28 which samples the analog input signal at the sampling epoch controlled by the clock signal from timing recovery circuit 26 provided over line 27. Or, preferably, as shown in FIG. 1 B, it can include a switch 30 which samples at the sampling epoch controlled by a free running clock and a digital interpolator 32 which, operating under the control of the control signal from line 27, adjusts the sampling phase. Timing recovery circuit 26, FIG. 2, includes delay 34, reference switch 36, timing error estimator 38 and numerical controlled oscillator (NCO) or voltage controlled oscillator (VCO) 40. When sampler 12 is configured with switch 28, FIG. 1A, a VCO is used to provide the clock signal to sampler 20. When switch 30 and digital interpolator 32, FIG. 1 B, are used for sampler 12, an NCO is used to generate from the timing error signal a sampler control signal z_n. The configuration of NCO 40 is depicted in FIG. 12 described below. The samples from sampler 20 are provided to timing error estimator 38 through delay 34 which provides a fixed delay to compensate for the processing delays of adaptive equalizer 22 and decoder 16. The delay ensures that the samples being fed back to timing recovery circuit 26 from sampler 20 are the samples which produced the output from decoder 24 which is also being fed back to timing recovery circuit 26. The other input signal to timing error estimator emanates from reference switch 36 which either directs thereto a timing reference signal or the signal from decoder 24.

When modem 18 is activated to receive data and possibly at other times, a training sequence is undertaken to establish a sampling phase for sampler 20 which closely approximates the sampling phase necessary to sample the incoming PAM signal properly. The training sequence is achieved by connecting reference switch 36 to the reference input. The reference input signal is a good approximation of a correctly decoded signal, i.e. one that was sampled at the proper points on the impulses to be sampled. This reference signal is provided to timing error estimator 38 which, in conjunction with the samples from sampler 20, provides an error signal to NCO 40 that sets the sampling phase of sampler 20 proximate the expected proper sampling phase.

When the training sequence is completed, impulses to be decoded are received by sampler 20 and reference switch 36 connects the output of decoder 24 to timing error estimator 38. The decoded output signals, which are now assumed to be a reliable representation of the signals that should be received, in conjunction with the unequalized data samples from sampler 20, which are samples of the actual received signals, are used by timing error estimator 38 to generate a timing error signal which in turn is used by NCO 40 to adjust the sampling phase of sampler 20 if it is sampling off of the desired sampling points of the incoming impulses which are being decoded. NCO 40 averages a number of timing error signals before adjusting the sampling phase of sampler 20. This feedback loop maintains the appropriate sampling phase which allows the received impulses to be sampled at the desired sampling points.

Timing error estimator 38 is shown in more detail in FIG. 3 to include timing error generator 42 and self-noise canceller 44. Timing error generator 42 receives two inputs, one from decoder 24 over line 45 and one from self-noise canceller 44 over line 46 and generates the timing error signal discussed above which is provided to NCO 40. Self-noise canceller 44 receives the output of decoder 24 and the output of delay 34, FIG. 2. The unequalized samples from delay 34 include contributions from the impulse which is to be decoded as well as the self-noise from the overlapping impulses. Self-noise canceller 44 produces an estimate of the self-noise generated by the channel without using feedforward taps and those contributions are subtracted from the samples before the samples are provided to timing error generator 42. The timing error signal is thus generated without the self-noise contributions from the channel and without the perturbations caused by the adaptive equalizer associated with some conventional timing recovery schemes. These conventional timing recovery schemes do not use the output of the sampler as an input to the timing recovery circuit (the other being the decoder output), but rather, these systems use the output of the adaptive equalizer. As described in the Background of Invention, perturbations in the feedforward equalizer taps of the adaptive equalizer cause jitter in the clock signal which reduces the ability of the sampler to sample very close to the desired sample points. Timing error generator 42, which is configured in a known manner, except that one of its inputs is from self-noise canceller 44, is depicted in more detail in FIG. 4. The function of timing error generator 42 is to determine if sampler 20 is sampling at the desired sample points on each impulse which is to be decoded or if it is sampling too early or too late and, if it is, to generate a timing error signal which will enable the sampling phase of sampler 20 to be adjusted accordingly. Timing error generator 42 is only exemplary, as any comparable timing error generator could be used with this invention.

In FIG. 5 there is shown an example of a portion of a received PAM signal 50 x(t) which is input over analog loop 17, FIG. 1 , to sampler 20. PAM signal 50 is the sum of a number of overlapping impulses g(t). In this example only three impulses 52, 54, and 56 are depicted; however, there would actually be a much larger number of impulses forming the PAM signal. The impulse of interest 52, which is the impulse to be presently decoded, is depicted in FIG. 6 being properly sampled at the stable point of the timing recovery loop. In this example, the controlled sample point g₀ 57 is properly taken at the peak of impulse 52, and, because it is properly sampled, timing sample points g._1/2 58 and g_1/2 59 are equivalent in magnitude. If sampler 20, FIG. 1 , is sampling too early, the peak or controlled sample point g₀ 57', FIG. 7, is not taken at the peak of impulse 52 and the magnitudes of timing sample points g._{1 2} 58' and g_1/2 59' are unequal, with the point g.ι_/2 58' having a lower magnitude than point g_{1 2} 59'. This difference in magnitude is referred to as the bias 60. Alternatively, sampler 20 can sample impulse 52 too late as depicted in FIG. 8. In that case peak or controlled sample point g₀ 57" is not located at the peak of impulse 52. Consequently, timing sample points g.ι ₂ 58" and g₁ 59" are not equal in magnitude and sample point g._1/2 58" is greater in magnitude than point gι ₂ 59", creating a bias 60.

Referring again to FIG. 4, the output of self-noise canceller 44 is provided to a first delay block 70, which provides a delay of one half of the impulse or symbol period T, and to summer 72. The output of delay 70 is provided to a second, identical delay block 74 whose output is connected to the other input of summer 72. Thus, the first input to summer 72 directly from self-noise canceller 44 is the sampled point after the peak on each impulse, e.g. point g_{1 2} 58, FIG. 6, and since there are two T/2 delays the other input to summer 72 is the sampled point before the peak sampled point, e.g. sample point g_ι_/2 56, FIG. 6. This therefore enables the comparison of the two timing sample points, namely, g_{1 2} and g._{1 2} , one on either side of each impulse peak, to determine if they are equal. As described above, if they are equal this indicates that sampler 20 is sampling the impulses properly. It must be noted that this peak sampling is only exemplary, as the impulses can be sampled at other controlled points, in which case the timing sample points g._1/2 and g_{1 2} would be compared differently. The summed signal is then supplied to sampler 75 which samples that difference signal down and provides a difference signal each period T (T=1/8Khz). The sampled down difference and the decoder signal are input to multiplier 76 which outputs to NCO 40 the timing error signal. If a negative output is received by NCO 40 this indicates that sampler 20 is sampling too early, a positive timing error signal indicates that the sampling is too late and a timing error signal of zero indicates proper sampling.

Typically, the procedure to start up the connection is for the modem to quickly estimate the channel response, i.e. the shape of the received pulses, as well as the initial timing offset. This is typically done with the help of training sequences, and various techniques to do this are well known in the art. These estimates can be used to jam the timing and self-noise canceller coefficients such that the user data transmission can be started as soon as possible. A disadvantage of the timing error generator of FIG. 4 is that if the initial sampling phase is off from the stable point, the self-noise canceller coefficients will need to be re-estimated after the timing jam. This unnecessarily increases start-up time. An improved timing error generator 42a, according to this invention, is depicted in FIG. 9. The stable point of this generator can be selected. This flexibility can be utilized to deal with the above mentioned problem. In fact, the stable point can be selected to coincide with the initial sampling phase. This eliminates the need for timing jam, and thus the need for re-estimating the self-noise canceller coefficients. Timing error generator 42a is configured similarly to timing error generator 42, FIG. 4, however, it includes a few unique and important components, namely, multipliers 80 and 82 which multiply the signal from self-noise canceller 44 by p and the delayed signal by q, respectively, and computation blocks 81 and 83. Clearly the timing error generator of FIG. 4 can be viewed as a special case with p=q=1. However, by properly choosing the values for p and q, the stable point of the timing loop can be selected. It is advantageous to set p= g._1/2 and q=g_1/2. where g_1/2 and g._1/2 are those given by the initial sampling phase. This way the initial sampling phase becomes the stable point of the timing loop. The values p and q are calculated by computation blocks 81 and 83, respectively, based on the initial channel estimates. Alternatively, instead of using multipliers 80 and 82, a summer 90 which adds the bias 60 to the output of summer 72a could be utilized to accomplish the same function.

As illustrated in FIG. 8. the initial sampling phase is too late for the timing error generator of FIG. 4. A large timing adjustment would be needed before the timing loop converges to its stable point. The self-noise canceller will need to be re-estimated due to the timing adjustment. On the other hand, for the timing error generator of FIG. 9 the timing error is close to zero, i.e. no timing adjustment is needed since the loop is already operating near its stable point.

Self-noise canceller 44 is shown in detail in FIG. 10; however, before describing its structure, a description of the mathematics behind its design is warranted. A received PAM signal, such as signal x(t) 50, FIG. 5, is a superposition of impulses g(t), such as impulses 52, 54 and 56, each of which is scaled by an information symbol a_k and delayed in time by kT. The PAM signal may be described mathematically as follows:

x(t) = ∑ a_k ^* g(t-kT) ( 1 ) where the summation in equation (1 ) and the following equations are over k.

A decision directed timing recovery scheme is typically based on a class of timing function f({gk}) of samples of the impulses g(t), where gι< is defined as: g_k = g(kT+τ) (2)

and where k= 0, +/- 0.5, +/-1.0, +/-1.5,... for a 2X impulse sampling rate, i.e. sampler 20 , FIG. 1 , sampling at twice the transmission rate of the impulses. For a particular sampling phase t, the timing function attains a value of zero. This sampling phase is referred to as the stable point of the timing recovery loop and is the sampling phase the timing recovery loop attempts to maintain.

Examples of several timing functions are:

(3)

f(τ) = g ,.2

(4)

f(τ) = p ^* g_1/2 - q ^* g._{1 2}

(5)

where p and q are constants.

The pulse waveform g(t) is unknown and thus the timing function cannot be computed directly. Instead, it can be estimated using unequalized samples of the received PAM signal 50 (x_n, n=0, 0.5, 1.0,...) which, according to this invention, are provided to self-noise canceller 44, FIG. 3, from sampler 20, FIG. 1 , in conjunction with the output (decisions) a_n from decoder 24. Samples of the received signal 50 are defined as follows:

x_n = x(nT+τ) (6)

=Σ a_k ^* g((n-k)T+τ) =∑ g_κ * a_n.k

The estimate of the timing function is called the timing error signal. For notational simplicity we assume that a_n ^*a_n is equal to one, although the self-noise canceller of the present invention works equally well for general cases. Examples of timing error signals for the three timing functions in equations (3), (4), and (5) above are, respectively:

^βn = (Xn+1 /2 " Xn-1/2) * ^n

(7)

On — ^xn+1/2 <*n

(8)

^β _n = p Xn+1 /2 &n " Xn-1 /2 * ^n

(9)

In general, the difference between the timing function f(τ) and the estimate of the timing function e_n is non-zero. This difference is due to the self-noise or intersymbol interference introduced to the PAM signal 50. In accordance with the present invention, self-noise canceller 44 is employed to significantly reduce the amount of self-noise in the timing error signal. To understand the operation of self-noise canceller 44, the X_{n+ 1 /2} * a_n term must be examined. This term can be expanded as follows:

Xn+1/2 * 3-n = 9l/2 + [Xn+1 /2 " 9l/2 * &ts] * ^n ( 1 0)

= 9ι/2 + a_n ^* [Σ gk+1 2 ^* 3n-k]

where k does not equal zero for the summation term.

The first term, g_{1 2} on the right hand side of equation (10) contributes to the timing function and the remaining terms contribute only to the self-noise. The self-noise terms can be substantially removed by estimating the summation term and subtracting it from the received signal sample x_n+i_/2 to form a self-noise canceled received signal Tx_n+1/2:

TXn+1 /2 ⁼ Xn+1/2 " ∑ H g k+1/2 * 3n-k

( 1 1 )

where k does not equal zero for the summation term. Referring again to FIG. 10, self-noise canceller 44 is a device which produces the self-noise canceled signal Tx_{n+1 2}. Self-noise canceller 44 includes a channel estimator block 100 which produces estimates of the impulse waveform samples Hg_k+1/2. for example, timing sample estimates Hg_{1 2} 101 , Hg._1/2 102, i.e. those which do not contribute to self-noise and self- noise sample estimates Hg_{3 2} 103, and Hg._{3 2} 104, etc. which of course do contribute to self-noise. Channel estimator block 100 is in this embodiment a least means square (LMS) estimator; however, any comparable estimation algorithm could be used. The decoder 24 output or decisions are provided to a series of cascaded delay blocks of which five, 106-110, are depicted. The number of delay blocks used in a particular application depends on the spreading of the impulse. If more spreading is desired, more delay blocks are utilized. The input to the first delay block 106, the digital output, and the outputs to the remaining delay blocks, the delayed digital outputs, are provided to a number of multipliers 112-119. The other inputs to the multipliers come from the estimates of the impulse waveform samples from channel estimator block 100. The products output from all of the multipliers, except 115 and 116, are the estimates of the self-noise terms and are provided to summer 120 which subtracts these self-noise terms from the received samples from delay 34 after the samples have been sampled down by two by sampler 122. The self-noise canceled sample or signal Tx_{n+1 2} is output to timing error generator 42, FIG.3. That sample or signal is also supplied to summer 124,

FIG. 10, which receives at one of its other two inputs the product from multiplier 115 of sample Hg._1/2 and the delayed a_n term from the input of the center delay block 108 and at its other input the product from multiplier 116 of the sample Hg_{1 2} and the delayed a_n term from the output of the center delay block 108. The output of summer 124 is provided to channel estimator block 100.

Self-noise canceller 44 does not remove from the samples the term Hg._{1 2} ^* a_n.ι which also contributes to self noise. However, when using the timing error signal of equation (7) which was used to implement self-noise canceller 44, it is unnecessary to remove this term. This is because at the stable point the term cancels during an averaging of the timing error signal which occurs in NCO 40. The canceling effect is illustrated by the following:

Xn+1/2 * ^an = 91/2 + 9-1/2 * ^an * ^an+1

and

Xn-1/2 * ^an = 9-1/2 + 9l/2 * ^an ^an-1

(13) + Σ g_k._1/2 ^* a_n ^* a_n._k

where k does not equal zero or negative one in equation (12) and k does not equal zero or one in equation (13) for the summation terms. At the stable point, g._1/2 is approximately equal to g_1/2 and the term g._1/2 ^* an ^* a_n+1 cancels term g_1/2 * a_n ^* a_n., when e_n are averaged. The present invention which utilizes self noise canceller 44 effectively decouples the timing recovery from the adaptation of the channel, in the sense that perturbations in the estimates (Hgk_+1/2) do not change the stable point of the timing loop. This results in increased accuracy and fast tracking capability of the timing loop.

Another embodiment of the self-noise canceller of this invention is depicted in FIG. 11. In this embodiment, self noise canceller 44a uses the channel estimator 100a outputs (Hgk_+1/2) to directly estimate the timing function by forming the timing error signal as follows:

(14)

The timing error signal could alternatively be formed as:

e_n= Hgι_/2 (1 5) o r e_n = P ^* Hg_t/2 - q^* Hg.ι_/2 ( 1 6)

Channel estimator block 100a operates in the same manner as block 100, FIG. 10; however, instead of outputting the self-noise canceled received samples to timing error generator 42, FIG. 3, the channel estimates Hg_{1 2} 101 a and Hg. _1/2 102a of the timing sample points which are substantially free of self-noise, are summed by summer 124a and their difference is the timing error signal which is directly supplied to NCO 40. The channel estimates Hgι_/2 101a and Hg.ι ₂ 102a along with all of the other channel estimates are multiplied by the decisions, a_n , from decoder 24 by multipliers 112a-119a. These products are summed by summer 120a with the received samples sampled down by two by sampler 122a and the output is provided to channel estimator block 100a. The self-noise canceling occurs within channel estimator block 100a.

Estimator block 100a utilizes more taps than necessary to compute the timing error signal and those extra taps serve to remove the self-noise and thus provide self-noise free estimates Hgι ₂ and Hg.ι ₂ of the timing sample points. One exemplary implementation of NCO 40 is shown in detail in FIG. 12. The timing error signal from timing error generator 42 or directly from self-noise canceller 44a is provided to timing error averager 128 which averages a predetermined number of timing error signals. The averaged timing error signal is then provided to both multipliers 130 and 132 which multiply the signal with filter parameters (a) and (b), respectively. The output of multiplier 132 is provided to summer 134 which sums it with the output of summer 134 delayed by delay 136 for one period T. The output of summer 134 is also provided to summer 138 which sums it with the output of multiplier 130 and the output of delay 140. The output of delay 140 is also the control signal z_n which is provided to sampler 20 over line 27, FIG.1. Control signal z_n instructs the interpolator to adjust the sampling phase to sample the PAM signal either earlier or later and the extent of the phase adjustment.

The present invention may be embodied in other specific forms without departing from the spirit or essential characteristics. The described embodiments are to be considered in all respects only as illustrative and not restrictive.

What is claimed is:

Claims

1. In a data receiver which periodically samples at predefined sample points a received analog signal and produces therefrom a digital output, an adaptive self-noise cancellation timing recovery circuit, comprising: a self-noise canceller, responsive to the samples and the digital output, for adaptively approximating the self-noise component of the samples and for removing the approximated self-noise component from the samples to produce substantially self-noise free samples; a timing error generator, responsive to the self-noise free samples and the digital output, for generating a timing error signal proportional to sampling deviations from the predefined sample points of the data receiver; and a control device, responsive to the timing error signal, for controlling the sampling phase of the data receiver to eliminate the sampling deviations.

2. The timing recovery circuit of claim 1 wherein the self- noise canceller includes a plurality of cascaded delays through which the digital output propagates to produce a plurality of delayed digital outputs; a channel estimator which produces timing and self-noise sample estimates of the received analog signal; a plurality of multipliers which multiply the digital output and the plurality of delayed digital outputs with the self-noise sample estimates to form the approximated self- noise component of the samples; and a subtractor for taking the difference between the unequalized samples and the approximated self-noise component of the samples to form the substantially self-noise free samples.

3. The timing recovery circuit of claim 1 wherein the control device is a numerical controlled oscillator.

4. In a data receiver which periodically samples at predefined sample points a received analog signal and produces therefrom a digital output, an adaptive self-noise cancellation timing recovery circuit, comprising: a self-noise canceller, responsive to the samples and the digital output, for adaptively approximating a self-noise free timing error signal proportional to sampling deviations from the predefined sample points of the data receiver; and a control device, responsive to the timing error signal, for controlling the sampling phase of the data receiver to eliminate the sampling deviations.

5 The timing recovery circuit of claim 4 wherein the self- noise canceller includes a channel estimator which estimates a pair of substantially self-noise free timing samples and a subtractor for taking the difference between the timing samples to form the timing error signal.

6. The timing recovery circuit of claim 4 wherein the control device is a numerical controlled oscillator.

7. A data receiver which utilizes adaptive self-noise cancellation timing recovery, comprising: a sampler circuit for periodically sampling a received analog signal at predefined sample points to provide a plurality of unequalized data samples; an equalizer circuit, operably coupled to the sampler circuit, for providing equalized data samples; a data detection circuit, operably coupled to the equalizer circuit, for decoding the equalized data samples to produce a decoded digital output; and an adaptive self-noise cancellation timing recovery circuit, operably coupled to the sampler circuit and to the data detection circuit, for detecting sampling deviations from the predefined sample points and adjusting the sampling phase of the sampler circuit to eliminate the sampling deviations, including: a self-noise canceller, responsive to the unequalized data samples and to the output of said data detection circuit, for adaptively approximating the self- noise component of the unequalized data samples and for removing from the data samples the approximated self- noise component of the data samples to produce substantially self-noise free data samples; a timing error generator, responsive to the substantially self-noise free data samples and the output of the data detection circuit, for generating a timing error signal proportional to the sampling deviations; and a control device, responsive to the timing error signal, for controlling the sampling phase of the sampler circuit to eliminate the sampling deviations.

8. The data receiver of claim 7 wherein the self-noise canceller includes a plurality of cascaded delays through which the digital output propagates to produce a plurality of delayed digital outputs; a channel estimator which produces timing and self-noise sample estimates of the received analog signal; a plurality of multipliers which multiply the digital output and the plurality of delayed digital outputs with the self-noise sample estimates to form the approximated self-noise component of the samples; and a subtractor for taking the difference between the unequalized samples and the approximated self-noise component of the samples to form the substantially self-noise free samples.

9. The data receiver of claim 7 wherein the control device is a numerical controlled oscillator.

10. A data receiver which utilizes adaptive self-noise cancellation timing recovery, comprising: a sampler circuit for periodically sampling a received analog signal at predefined sample points to provide a plurality of unequalized data samples; an equalizer circuit, operably coupled to the sampler circuit, for producing equalized data samples; a data detection circuit, operably coupled to the equalizer circuit, for decoding the equalized data samples to produce a decoded digital output; and an adaptive self-noise cancellation timing recovery circuit, operably coupled to the sampler circuit and the data detection circuit, for detecting sampling deviations from the predefined sample points and adjusting the sampling phase of the sampler circuit to eliminate the sampling deviations, including: a self-noise canceller, responsive to the unequalized data samples and the output of the data detection circuit, for adaptively approximating a substantially self-noise free timing error signal proportional to the sampling deviations; and a control device, responsive to the timing error signal, for controlling the sampling phase of the sampler circuit to eliminate the sampling deviations.

1 1 The data receiver of claim 10 wherein the self-noise canceller includes a channel estimator which estimates a pair of substantially self-noise free timing samples and a subtractor for taking the difference between the timing samples to form the timing error signal.

12. The data receiver of claim 10 wherein the control device is a numerical controlled oscillator.

13. In a data receiver which periodically samples at predefined sample points a received analog signal and produces therefrom a digital output, an adaptive self-noise cancellation timing recovery method, comprising: adaptively approximating the self-noise component of the samples removing the approximated self-noise component from the samples to produce substantially self-noise free samples; generating, from the self-noise free samples and the digital output, a timing error signal proportional to sampling deviations from the predefined sample points of the data receiver; and controlling, based on the timing error signal, the sampling phase of the data receiver to eliminate the sampling deviations.

14. The method of claim 13 wherein the step of adaptively approximating includes producing a plurality of delayed digital outputs; producing timing and self-noise sample estimates of the received analog signal; and multiplying the digital output and the plurality of delayed digital outputs with the self-noise sample estimates to form the approximated self-noise component of the samples; and wherein the step of removing includes taking the difference between the unequalized samples and the approximated self-noise component of the samples to form the substantially self-noise free samples.

15. In a data receiver which periodically samples at predefined sample points a received analog signal and produces therefrom a digital output, an adaptive self-noise cancellation timing recovery method, comprising: adaptively approximating a self-noise free timing error signal proportional to sampling deviations from the predefined sample points of the data receiver; and controlling, based on the timing error signal, the sampling phase of the data receiver to eliminate the sampling deviations.

1 6 The method of claim 15 wherein the step of adaptively approximating includes estimating a pair of substantially self- noise free timing samples and taking the difference between the timing samples to form the timing error signal.

17. A method of receiving data which utilizes adaptive self- noise cancellation timing recovery, the method comprising: periodically sampling a received analog signal at predefined sample points to provide a plurality of unequalized data samples; equalizing the unequalized data samples to produce equalized data samples; decoding the equalized data samples to produce a decoded digital output; detecting sampling deviations from the predefined sample points and adjusting the sampling phase of the sampler circuit to eliminate the sampling deviations; the step of detecting and adjusting including: adaptively approximating, from the unequalized data samples and the digital output, the self-noise component of the unequalized data samples; removing from the unequalized data samples the approximated self-noise component of the data samples to produce substantially self-noise free data samples; generating, from the substantially self-noise free data samples and the digital output, a timing error signal proportional to the sampling deviations; and controlling, based on the timing error signal, the phase of the sampling to eliminate the sampling deviations.

18. The method of claim 17 wherein the step of adaptively approximating includes producing a plurality of delayed digital outputs; producing timing and self-noise sample estimates of the received analog signal; and multiplying the digital output and the plurality of delayed digital outputs with the self-noise sample estimates to form the approximated self-noise component of the samples; and wherein the step of removing includes taking the difference between the unequalized samples and the approximated self-noise component of the samples to form the substantially self-noise free samples.

19. A method of receiving data which utilizes adaptive self- noise cancellation timing recovery , the method comprising: periodically sampling a received analog signal at predefined sample points to provide a plurality of unequalized data samples; equalizing the unequalized data samples to produce equalized data samples; decoding the equalized data samples to produce a decoded digital output; and detecting sampling deviations from the predefined sample points and adjusting the sampling phase of the sampler circuit to eliminate the sampling deviations; the step of detecting and adjusting including: adaptively approximating, from the unequalized data samples and the digital output, a substantially self- noise free timing error signal proportional to the sampling deviations; and controlling, based on the timing error signal, the phase of the sampling to eliminate the sampling deviations.

20 The method of claim 19 wherein the step of adaptively approximating includes estimating a pair of substantially self- noise free timing samples and taking the difference between the timing samples to form the timing error signal.