WO1998014015A3 - A method and apparatus for having multiple virtual paths in one serial i/o controller channel - Google Patents
A method and apparatus for having multiple virtual paths in one serial i/o controller channel Download PDFInfo
- Publication number
- WO1998014015A3 WO1998014015A3 PCT/US1997/017165 US9717165W WO9814015A3 WO 1998014015 A3 WO1998014015 A3 WO 1998014015A3 US 9717165 W US9717165 W US 9717165W WO 9814015 A3 WO9814015 A3 WO 9814015A3
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- sub
- data streams
- serial
- binary bits
- function data
- Prior art date
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Classifications
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q11/00—Selecting arrangements for multiplex systems
- H04Q11/04—Selecting arrangements for multiplex systems for time-division multiplexing
- H04Q11/0428—Integrated services digital network, i.e. systems for transmission of different types of digitised signals, e.g. speech, data, telecentral, television signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13003—Constructional details of switching devices
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13034—A/D conversion, code compression/expansion
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13036—Serial/parallel conversion, parallel bit transmission
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13103—Memory
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13106—Microprocessor, CPU
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13174—Data transmission, file transfer
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13199—Modem, modulation
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13202—Network termination [NT]
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13204—Protocols
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13209—ISDN
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13214—Clock signals
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13216—Code signals, frame structure
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13224—Off-net subscriber, dial in to/out from network, teleworking
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13299—Bus
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/1331—Delay elements, shift registers
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/1332—Logic circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13322—Integrated circuits
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04Q—SELECTING
- H04Q2213/00—Indexing scheme relating to selecting arrangements in general and for multiplex systems
- H04Q2213/13399—Virtual channel/circuits
Abstract
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/717,173 | 1996-09-24 | ||
US08/717,173 US5983291A (en) | 1996-09-24 | 1996-09-24 | System for storing each of streams of data bits corresponding from a separator thereby allowing an input port accommodating plurality of data frame sub-functions concurrently |
Publications (3)
Publication Number | Publication Date |
---|---|
WO1998014015A2 WO1998014015A2 (en) | 1998-04-02 |
WO1998014015A9 WO1998014015A9 (en) | 1998-08-06 |
WO1998014015A3 true WO1998014015A3 (en) | 1998-10-29 |
Family
ID=24880992
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1997/017165 WO1998014015A2 (en) | 1996-09-24 | 1997-09-24 | A method and apparatus for having multiple virtual paths in one serial i/o controller channel |
Country Status (2)
Country | Link |
---|---|
US (1) | US5983291A (en) |
WO (1) | WO1998014015A2 (en) |
Families Citing this family (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6240095B1 (en) * | 1998-05-14 | 2001-05-29 | Genroco, Inc. | Buffer memory with parallel data and transfer instruction buffering |
US6332173B2 (en) * | 1998-10-31 | 2001-12-18 | Advanced Micro Devices, Inc. | UART automatic parity support for frames with address bits |
US7107383B1 (en) * | 2000-05-03 | 2006-09-12 | Broadcom Corporation | Method and system for multi-channel transfer of data and control information |
FR2813150B1 (en) * | 2000-08-18 | 2003-05-30 | Ercom Engineering Reseaux Comm | G703 JUNCTION ANALYSIS SYSTEM |
KR100921542B1 (en) * | 2001-10-15 | 2009-10-12 | 어드밴스드 마이크로 디바이시즈, 인코포레이티드 | A peripheral interface circuit for an i/o node of a computer system |
US6725297B1 (en) | 2001-10-15 | 2004-04-20 | Advanced Micro Devices, Inc. | Peripheral interface circuit for an I/O node of a computer system |
WO2003034240A1 (en) * | 2001-10-15 | 2003-04-24 | Advanced Micro Devices, Inc. | A peripheral interface circuit for an i/o node of a computer system |
US6839784B1 (en) * | 2001-10-15 | 2005-01-04 | Advanced Micro Devices, Inc. | Control unit of an I/O node for a computer system including a plurality of scheduler units each including a plurality of buffers each corresponding to a respective virtual channel |
DE10230678A1 (en) * | 2002-07-04 | 2004-03-25 | Francotyp-Postalia Ag & Co. Kg | Arrangement for controlling printing in a mail processing device |
DE10230679A1 (en) * | 2002-07-04 | 2004-01-22 | Francotyp-Postalia Ag & Co. Kg | Method for controlling printing in a mail processing device |
DE10250820A1 (en) * | 2002-10-31 | 2004-05-13 | Francotyp-Postalia Ag & Co. Kg | Arrangement for printing a print image with areas of different print image resolution |
JP4385247B2 (en) * | 2003-08-04 | 2009-12-16 | 日本電気株式会社 | Integrated circuit and information processing apparatus |
ATE393523T1 (en) * | 2004-10-12 | 2008-05-15 | Koninkl Philips Electronics Nv | SWITCH DEVICE AND COMMUNICATIONS NETWORK HAVING SUCH A SWITCH DEVICE AND METHOD FOR SENDING DATA IN AT LEAST ONE VIRTUAL CHANNEL |
CN112631976A (en) * | 2020-12-16 | 2021-04-09 | 中国电子科技集团公司第五十八研究所 | Configurable hardware IP circuit structure |
CN113971145B (en) * | 2021-10-28 | 2022-08-19 | 金华高等研究院 | SPI-to-multi-serial port circuit with dynamic buffer area allocation and method |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
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EP0428407A2 (en) * | 1989-11-15 | 1991-05-22 | Digital Equipment Corporation | An integrated communications link having dynamically allocatable bandwidth and a protocol for transmission of allocation information over the link |
EP0447054A2 (en) * | 1990-03-15 | 1991-09-18 | International Business Machines Corporation | Integrated data link controller with synchronous link interface and asynchronous host processor interface |
DE4124761A1 (en) * | 1991-07-23 | 1993-01-28 | Audiovisuelles Marketing Und C | Card-type control device for data-processing or transmission - feeds received data to buffer memory, supplies in parallel form to processor for real=time processing |
US5184348A (en) * | 1988-12-27 | 1993-02-02 | Bull, S.A. | Isdn multiprotocol communications controller |
GB2280338A (en) * | 1993-07-16 | 1995-01-25 | Motion Media Techn Ltd | Multiple bit stream multiplexor/demultiplexor for communication channels |
Family Cites Families (16)
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US3411145A (en) * | 1966-07-01 | 1968-11-12 | Texas Instrumeuts Inc | Multiplexing and demultiplexing of related time series data records |
US4513419A (en) * | 1982-10-25 | 1985-04-23 | The Boeing Company | Digital conversion circuit and method for testing digital information transfer systems based on serial bit communication words |
EP0164105A3 (en) * | 1984-06-04 | 1988-01-27 | Siemens Aktiengesellschaft | Circuit for receiving and/or transmitting serial binary signals in a processing device comprising a microcomputer or a microprocessor |
JPH0766317B2 (en) * | 1986-04-09 | 1995-07-19 | 株式会社日立製作所 | Display control method |
US5134702A (en) * | 1986-04-21 | 1992-07-28 | Ncr Corporation | Serial-to-parallel and parallel-to-serial converter |
US4939723A (en) * | 1989-06-07 | 1990-07-03 | Ford Aerospace Corporation | Bit-channel multiplexer/demultiplexer |
US5448257A (en) * | 1991-07-18 | 1995-09-05 | Chips And Technologies, Inc. | Frame buffer with matched frame rate |
US5715248A (en) * | 1992-05-21 | 1998-02-03 | Alcatel Network Systems, Inc. | Derivation of VT group clock from SONET STS-1 payload clock and VT group bus definition |
US5651121A (en) * | 1992-12-18 | 1997-07-22 | Xerox Corporation | Using mask operand obtained from composite operand to perform logic operation in parallel with composite operand |
US5455626A (en) * | 1993-11-15 | 1995-10-03 | Cirrus Logic, Inc. | Apparatus, systems and methods for providing multiple video data streams from a single source |
US5413594A (en) * | 1993-12-09 | 1995-05-09 | Ventritex, Inc. | Method and apparatus for interrogating an implanted cardiac device |
JPH07202714A (en) * | 1993-12-28 | 1995-08-04 | Nec Ic Microcomput Syst Ltd | Parallel/series data converter circuit |
US5727233A (en) * | 1994-08-02 | 1998-03-10 | Apple Computer, Inc. | Byte-mode and burst-mode data transfer mechanism for a high-speed serial interface |
US5550381A (en) * | 1994-11-01 | 1996-08-27 | The Regents Of The University California | Event counting alpha detector |
DE4445053C2 (en) * | 1994-12-07 | 2003-04-10 | Francotyp Postalia Ag | Interface circuit internal to the franking machine |
US5680400A (en) * | 1995-05-31 | 1997-10-21 | Unisys Corporation | System for high-speed transfer of a continuous data stream between hosts using multiple parallel communication links |
-
1996
- 1996-09-24 US US08/717,173 patent/US5983291A/en not_active Expired - Fee Related
-
1997
- 1997-09-24 WO PCT/US1997/017165 patent/WO1998014015A2/en active Application Filing
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5184348A (en) * | 1988-12-27 | 1993-02-02 | Bull, S.A. | Isdn multiprotocol communications controller |
EP0428407A2 (en) * | 1989-11-15 | 1991-05-22 | Digital Equipment Corporation | An integrated communications link having dynamically allocatable bandwidth and a protocol for transmission of allocation information over the link |
EP0447054A2 (en) * | 1990-03-15 | 1991-09-18 | International Business Machines Corporation | Integrated data link controller with synchronous link interface and asynchronous host processor interface |
DE4124761A1 (en) * | 1991-07-23 | 1993-01-28 | Audiovisuelles Marketing Und C | Card-type control device for data-processing or transmission - feeds received data to buffer memory, supplies in parallel form to processor for real=time processing |
GB2280338A (en) * | 1993-07-16 | 1995-01-25 | Motion Media Techn Ltd | Multiple bit stream multiplexor/demultiplexor for communication channels |
Non-Patent Citations (1)
Title |
---|
CHATAL J: "VOLLDUPLEX-CONTROLLER FUER ISDN ZWEI MEHRKANALIGE HDLC- UND V110-CONTROLLER MIT INTEGRIERTEM KONTEXT-RAM", ELEKTRONIK, vol. 40, no. 19, 17 September 1991 (1991-09-17), pages 68 - 69, 74 - 75, XP000262959 * |
Also Published As
Publication number | Publication date |
---|---|
WO1998014015A2 (en) | 1998-04-02 |
US5983291A (en) | 1999-11-09 |
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