WO1998016005A1

WO1998016005A1 - Phase detector with explicit asynchronous reset

Info

Publication number: WO1998016005A1
Application number: PCT/US1997/017173
Authority: WO
Inventors: David R. Staab
Original assignee: Peregrine Semiconductor Corporation
Priority date: 1996-10-07
Filing date: 1997-09-25
Publication date: 1998-04-16

Abstract

An embodiment of the present invention provides a phase detector (404) with an externally accessible initiallization (1L) node (408). In this embodiment, the phase detector includes a comparison circuit that compares a reference signal (FR) and a feedback signal (FV) to provide an output signal that represents at least one of the phase difference and the frequency difference between the reference signal and the feedback signal. In the present embodiment, the comparison circuit includes a memory element that it uses to provide the output signal. In particular, the memory element is a first flip-flop (202A) and a second flip-flop (202B). Accordingly, the output signal is the output of the first flip-flop and the output of the second flip-flop. The output signal is coupled to a reset circuit (402, 406). The reset circuit is fed back to a reset input (202A, 202B) of the comparison circuit to reset the comparison circuit in response to predetermined output signal. The externally accessible initiallization (1L) node is also coupled to the reset input of the comparison circuit to provide access to the reset input external to the phase detector. By providing this external access, the initiallization node facilitates logic simulation, testing and/or fault grading of circuits containing this phase detector embodiment.

Description

PHASE DETECTOR WITH EXPLICIT ASYNCHRONOUS RESET

BACKGROUND OF THE INVENTION

1. Field of the Invention

The invention relates generally to phase locked loops, and more particularly, to phase detectors and to facilitating or improving the testing and/or simulation of circuits that use phase detectors in phase locked loops.

2. Description of the Related Art

Phase locked loop circuits are frequently used in electronic systems for clock recovery, frequency synthesis, signal demodulation, frequency multiplication, pulse synchronization and "clean" signal regeneration, for example. Phase locked loop ("PLL") circuits typically rely on a phase detector to determine the phase difference and/or frequency difference between two input signals, such as a reference signal and a feedback signal for example, and to generate an output signal that represents this phase and/or frequency difference.

Such an output signal that represents a phase/frequency difference shall be referred to as an error signal.

Variations and specific requirements of phase detectors are generally determined by the particular application. U.S. Patent No. 5,307,028, entitled, Phase-and-Frequency Mode/Phase Mode Detector with the Same Gain in Both

Modes, issued to Chen, for example, discloses a dual-mode detector which has phase-detection and phase-and-frequency-detection modes of operation. U.S. Patent No. 4,814,726, entitled, Digital Phase Comparator/Charge Pump with Zero Deadband and Minimum Offset, issued to Byrd et al, for instance, discloses a phase detector and charge pump combination for use in a digital PLL system.

In a conventional phase locked loop application, the feedback signal input to a phase detector is provided by an output of a voltage controlled oscillator ("VCO"). In this application, the phase detector may compare the phase of the VCO's output against that of the reference signal and generates an error signal whose value is proportional to the phase difference between these two signals. The error signal output by the phase detector may then be filtered to extract its mean direct current (DC) content. For example, the error signal may be used to provide input to a charge pump. In response to this input, the charge pump may control a DC output voltage. This DC output voltage may be applied to an input of the VCO, providing the VCO with feedback control.

Through its input to the charge pump, the error signal may cause the DC output voltage to increase when the feedback signal lags the reference signal or it may cause this output voltage to decrease when the feedback signal leads the reference signal. Thus, the error signal and charge pump may cause a higher voltage to be applied to the VCO to increase the frequency of the feedback signal when the feedback signal lags the reference signal. In the alternative, the error signal and the charge pump may cause a lower voltage to be applied to the

VCO to decrease the frequency of the feedback signal when the feedback signal leads the reference signal. Using this process this loop will attempt to match the phase of the feedback signal to the phase of the reference signal.

Conventional phase detectors may use memory elements, such as flip- flops for example, to compare the phase of input signals and to generate the error signal that drives the charge pump in response to the inputs in the manner described. Memory elements are not limited to a single flip-flop or to flip-flops generally. Memory elements are required for a phase frequency detector (PFD) device. Without a memory element, an PFD device would have no frequency pull-in capability. These memory elements can cause problems, however, when it comes time to test for defects in circuitry that uses them in this manner.

For example, circuit testers are typically used in production to test chips or circuits for defects. These circuit testers typically rely on "response tables." A response table is a set of input and output values associated with a chip or circuit. The output values are the outputs expected to be present at pins external to a properly functioning chip or circuit in response to application of the input values to pins external to the chip or circuit. Production testers typically apply the inputs from a response table to the pins of a chip or circuit under test. During the application of inputs, they typically compare the outputs produced by the chip or circuit under test in response to these inputs to the outputs predicted by the response table. If the actual outputs differ from the outputs predicted by the response table, the tester typically rejects the chip or identifies it as defective. Response tables typically are generated using logic simulators. A logic simulator typically uses a computer program to simulate the operation of a hardware device. By simulating the hardware circuit, logic simulators typically are able to generate outputs that should be produced by a properly functioning circuit in response to a set of inputs. But, logic simulators may be unable to simulate the response during power-up, for example, of phase-locked loop circuits that use memory elements, such as flip-flops.

For example, in conventional flip-flops, the state of the flip-flop's outputs may be unknown at power up. Accordingly, the logic simulator typically will assign an unknown state to such flip-flops because it typically will have no way to determine what the power-up states of these outputs will be in the actual device. Additionally, the power-up states of the actual device may be different with each power-up. Nevertheless, hardware chips or circuits using a phase-locked loop that comprises flip-flops, for example, typically will produce some kind of output during power-up in response to these unknown states. Because the logic simulator typically is unable to pre-determine these power-up states, however, it typically is unable to produce meaningful values for a response table.

A second difficulty that may arise as a result of this power-up uncertainty is that logic simulators often are unable to provide a meaningful response table if the state of the reset input of a flip-flop is unknown. Reset input shall refer to the input of a flip-flop, for example, which can be asserted to put a flip-flop into its reset state. When the reset pin is asserted, a flip-flop typically will not respond to signals applied to its other input pins. Accordingly, with the reset input asserted, a flip-flop's inputs typically cannot be "clocked."

"Clocking" shall refer to the process of applying a signal to an input of a flip- flop and having the flip-flop respond.

Logic simulators often are unable to clock data into a flip-flop after power-up because, as configured in phase detectors, the state of a flip-flop's reset input depends on the state of the flip-flop's outputs which are unknown.

Because a logic simulator typically will not know whether it can "clock" flip- flops under these circumstances, the logic simulator may be unable to simulate the operation of the circuit and to generate meaningful expected outputs in response to known inputs. This problem could be avoided, for example, if the logic simulator could assert a flip-flop's reset input to reset the flip-flop to a known state. In typical earlier phase detectors, however, a flip-flop's reset input ordinarily is not accessible to the logic simulator through the inputs of the circuit under test. To solve this problem, logic simulators are often configured to artificially "force" the simulated flip-flop to an arbitrary state using special software instructions which set or reset flip-flops. The simulator then proceeds to simulate the operation of the circuit and generates response tables using these forced states as starting values. These "forced states" are referred to as artificial because they do not correspond to actual signals, but merely are used to set the initial state of the circuit under test.

During testing, response tables are used to test the operation of the actual phase detector device. Unfortunately, the forced initial state of a simulated flip- flop may not match the actual power up states of the hardware flip-flop when it is powered up during testing. Accordingly, at power up, the hardware circuit may generate outputs as a result of its actual state which cannot be predicted by simulation and are inconsistent with the response tables. Thus, the response table used by the production tester may have to be modified in order to ignore these outputs until the actual circuit state matches the simulation state.

Conventional techniques have been developed to sequence a hardware circuit's phase detector into a known state after power up. However, the added time and effort required to test such circuits may be significant. In particular, unlike simulated phase detector flip-flops whose reset input is unknown at power-up, hardware flip-flops as used in phase detectors that power up with an asserted reset ordinarily will automatically reset themselves, thus de-asserting the reset signal. In other words, in hardware flip-flops as used in phase detectors, the reset input is typically de-asserted at power-up. Unfortunately, logic simulators at present generally do not account for this complex dependancy of reset inputs of phase detector flip-flops upon flip-flop outputs.

Adding such intelligence to logic simulators may be possible, but at the cost of considerable complexity and increased simulation time.

Hardware PFD's can be initialized by applying a predetermined sequence of test vectors to inputs of the hardware circuit in order to place the hardware flip-flops' outputs in a known state. A test vector is a set of input values that are applied to the external inputs of the circuit or chip being tested. Once the outputs of the hardware flip-flop reach a known state, the hardware chip or circuit typically can be tested using response tables. The need to initialize hardware phase detectors in this manner can increase the time and effort required to test hardware chips or circuits because specific sequences of test vectors typically must be developed to sequence the flip-flops into a known state. The number of test vectors required can vary depending on the design of the circuit under test. In particular, more vectors typically will be required to initialize an

"embedded" phase detector as opposed to "non-embedded" phase detector. An embedded phase detector is one that is embedded in a circuit under test such that the phase detector's inputs are not readily accessible at the circuit's inputs. A non-embedded phase detector is one that is not embedded in a circuit under test such that the phase detector's inputs are readily accessible at the circuit's inputs.

Ordinarily, initializing a non-embedded phase detector may require between approximately six to 1,000 test vectors, for example. Conversely, initializing an embedded phase detector may require as many as approximately 19,000 test vectors, for example. Thus, the need to initialize hardware phase detectors can introduce inefficiencies into the actual production testing. In particular, initializing the hardware phase detector using vectors typically increases the duration of the test process, thus increasing test cost. The increase in test time typically will be worse for an "embedded" phase detector, as opposed to a "non-embedded" phase detector, due to the larger number of test vectors. The test time increase from initialization can be compounded if initialization is required in more than one of the functional or parametric tests to which the circuit will be subjected. Initialization time may be required for each of the different tests, for example.

Moreover, the need to initialize hardware phase detectors may also cause defect free devices to be rejected. In particular, digital production testers typically use clock cycles to compare the outputs of the circuit under test with the outputs predicted by response tables. As we have indicated, phase detector circuits often will produce unpredictable outputs before the associated flip-flops are sequenced into a known state. If the production tester does not properly ignore the extraneous outputs during the time period in which the detector is being initialized, the digital tester may detect errors as a result of these extraneous outputs on a circuit that is logically correct.

The uncertainty typically associated with conventional phase detectors at power up may also pose problems in fault grading such circuits. Fault grading is a technique which is often used to determine the "testability" of a particular circuit design. "Testability" shall refer to the ability of chips implementing a circuit design to be screened for defects. Testers typically must rely on pins external to a chip to screen that chip for defects internal to the chip using a response table, for example. Fault grading is a technique which typically can determine to what extent a properly functioning chip's internal nodes can be observed at pins or nodes external to the chip. In general, the greater the percentage of internal nodes that can be observed external to the chip, the more effectively the chip can be screened in production for defects. Fault grading may become increasingly important as the amount of digital logic embedded in a circuit design increases. In particular, increased amounts of digital logic embedded in a circuit can result in a wider variety of possible errors. Accordingly, it is typically important to be able to verify that embedded digital logic can be adequately tested. A fault grader is a device that simulates a chip's design in order to evaluate its testability. "Stuck at" testing is an example of a fault grading technique. This technique may simulate a defective chip by choosing a simulated internal node of a simulated chip and tying that internal node to a high logic level ("stuck at one"), for example. It may then run a set of test vectors on the simulated chip and observe the simulated chip's external outputs. This technique may next run the same set of test vectors on the simulated chip a second time, but allow the chosen simulated internal node to behave as it would in a properly functioning hardware chip. The fault grader may then compare the external outputs resulting from the second run to those observed from the first run. If the outputs are different, the fault grader has determined that this internal node can be screened with the test vectors employed. In particular, the differing outputs indicate that production test equipment, observing pins external to the actual chip, for example, will be able to determine whether or not the hardware chip has a defect that causes this internal node to be stuck at a high logic level or "stuck at one." Typically, this "stuck at one" process is repeated for each node individually and then repeated again for each node individually, forcing a zero for "stuck at zero" testing. Fault grading techniques are generally described in Silos III User's Manual authored by Simucad Inc., Copyright 1991, pp. 5-1 to 5-44, and entitled "FAULT SIMULATION OVERVIEW", which is hereby incorporated herein by this reference.

Fault grading is based on logic simulation. As such, the state uncertainty associated with the power up of phase detectors that use flip-flops, for example, typically will hinder the fault grader in its simulation of the operation of the phase detector. Moreover, a fault grader may be unable to reset flip-flops because flip-flop reset inputs typically are not accessible to the fault grader. Unlike logic simulators, conventional fault graders will not allow the phase detector to be forced into a known state using software commands. This is due to the nature of fault grading. Fault grading attempts to observe actual performance of a chip in response only to signals applied to its input pins. Fault graders typically allow manipulation of an internal node of a chip only to simulate a defect such as a "stuck at" fault. Accordingly, the state uncertainty associated with conventional phase detectors that contain memory elements may prevent those phase detectors from being fault graded with a conventional fault grader in the desired manner thus reducing fault coverage.

Thus, there has been a need for a phase detector that uses memory elements which allows desired fault grading, and allows simplified, lower cost testing. 3. Description of Certain Illustrative Convential PLL and Phase

Detector Devices

Figure 1 illustrates a conventional phase locked loop circuit 100. As illustrated, this circuit includes a phase detector 104 which has a reference input 102 and a feedback input 132, a charge pump 106 coupled to Up line 126 and

Down line 128, a low pass filter (LPF) 116 having an input 129, a voltage controlled oscillator (VCO) 108 having an input 130 and an output 110, and a feedback loop 112 which extends from VCO output 110 to phase detector input 132. The LPF 116 connected to ground, filters the output of the charge pump 106 before this output is applied to VCO input 130.

Reference signal 118, which is applied to reference input 102, may be provided by a reference signal source 136 in any manner known in the art to be acceptable for a particular application. It may be provided by a crystal controlled oscillator, for example. If desired, an optional frequency divider 134 can be interposed between the reference signal source 136 and the input 102 to control the frequency of the reference signal 118.

Feedback signal 120 is provided to the phase detector 104 at input 132 by feedback loop 112. As illustrated, feedback signal 120 is a function of the VCO output signal 122. In this embodiment, the feedback loop 112 divides down the frequency of signal 122 using programmable divider 114. Digital control word 124 can be used to set the divider to provide the desired division ratio N.

In operation, phase detector 104 compares the reference signal 118 to feedback signal 120, and produces an output signal which varies depending upon whether the phase of signal 120 leads the phase of signal 118 or lags the phase of signal 118. This output signal is used to provide input to the VCO 108.

As illustrated in Figure 1, the output of phase detector 104 is provided through up line 126 and down line 128 to charge pump 106. Up line 126 and down line 128 operate with charge pump 106 and LPF 116 to provide input to VCO 108. For example, if the phase of feedback signal 120 leads the phase of reference signal 118, the phase detector will provide signals on up line 126 and down line 128 that cause the charge pump to reduce the voltage at input 129 of LPF 116, and ultimately to LPF 116's output. VCO 108 will respond by decreasing the frequency of feedback signal 122. This frequency decrease will shift the phase of the feedback signal 120 toward the phase of the reference signal 118.

In the alternative, if the phase of feedback signal 120 lags the phase of reference signal 118, the phase detector will provide signals on up line 126 and down line 128 that cause the charge pump to increase the voltage level to input 129 of LPF 116. VCO 108 will respond by increasing the frequency of feedback signal 122. This increase in frequency will again shift the phase of the feedback signal 120 toward the phase of the reference signal 118. This process typically operates to match the phase of feedback signal 120 with the phase of reference signal 118. Charge pumps are well known in the art. For example, certain earlier charge pumps are described in U.S. Patent No. 4,814,726, issued to Byrd et al., which is hereby incorporated herein by this reference.

Figure 2 shows an illustrative embodiment of a conventional phase detector 204 which may be used to implement phase detector 104 of Figure 1.

The phase detector compares two input signals to determine their frequency and/or phase difference and provides an output signal representative of this frequency and/or phase difference. The circuitry in the phase detector 204 for accomplishing this comparison shall be referred to as the comparison circuit of the phase detector 204. The comparison circuit of phase detector 204 comprises two memory elements, i.e., the two D flip-flops (DFFs) 202A and 202B, which are used to compare the phase and/or frequency of the feedback signal 120 to the phase of reference signal 118. The reference signal 118 is applied to a reference node 205 and coupled to the input 204A of DFF 202A. The feedback signal 120 is applied to the feedback node 207 and coupled to input 204B of DFF 202B.

Phase detector 204 also comprises a reset circuit. The reset circuit of phase detector 204 resets the memory elements (in this case flip-flops 202A and

202B) in response to the output signals of the memory elements (outputs 206 A and 206B). This phase detector reset circuit comprises NAND gate 210, the inputs 214A and 214B coupled to outputs 206 A and 206B, and the output 216 of NAND gate 210 applied to reset inputs 212A and 212B of DFFs 202 A and 202B, respectively. In this embodiment, output 206 A also corresponds to Up line 126, and output 206B also corresponds to Down line 128. Accordingly, in this embodiment, the output sugnal from output 206A is also an Up signal and the output signal from output 206B is also a Down signal.

Phase detector 204 also comprises the input 208 A of DFF 202A and the input 208B of DFF 202B each tied to a logic one reference potential 203.

Flip-flops 202A and 202B latch the logic level present at their inputs 208A and 208B to outputs 206A and 206B, respectively, on the rising edge or other first component of the input signal applied to their respective inputs 204 A and 204B, providing output signals on outputs 206 A and 206B. For example, a transition from a low logic level to a high logic level by signal 118 on input

204A will latch the high logic level present at input 208A through the flip-flop 202A to output 206A. A signal "component" shall include a high or low logic level or a rising or falling edge, for example.

Flip-flops 202 A and 202B are reset when reset inputs 212A and 212B are asserted low. After the flip-flops 202A and 202B are reset, the output signals on outputs 206A and 206B are at a logic low level, and reset inputs 212 A and 212B are de-asserted by logic high input signals. Phase detector 204 operates as a frequency detector initially upon power up and ultimately as a phase detector to achieve and maintain final loop lock. For example, using phase detector 204 of Figure 2 to implement phase detector 104 of Figure 1 enables PLL 100 to achieve final loop lock no matter how far apart the initial phase and frequency of reference signal 118 and feedback signal 120 are at power up, assuming the VCO tuning range and programmable divider allow the frequency of signal 118 to equal that of signal 120. The VCO has no memory elements, and therefore provides predictable operation at power-up.

When flip-flops 202A and 202B are first powered up, it is not known whether the initial states of the output signals on outputs 206 A and 206B are at a high logic level or at a low logic level. Thus, it typically is not known at power up whether flip-flops 202A and 202B are in their reset state with both outputs set to a logic low.

This uncertainty of not knowing the power-up state of phase detector typically does not create problems during normal circuit operation. Note, that if both flip-flops power up with outputs set to a logic high, the circuit will reset both flip-flops. Table 1 shows possible states for the output signals on outputs 206A and 206B of phase detector 204 at power up and the associated states of the input signals at reset inputs 212A and 212B.

Output Output Reset Inputs 212A and 206A 206B 212B

1 0 0 1

2 0 1 1

3 1 0 1

4 1 1 0

Table 1 Row 4 represents the only combination of states that asserts the reset inputs 212A and 212B low. In response to assertion of the reset inputs, flip-flops 202 A and 202B will be reset to the states shown by row 1 of Table 1. Accordingly, after power up, flip-flops 202A and 202B will be in a state represented by one of rows 1, 2 or 3.

The uncertainty of not knowing the power-up state of phase detector 204 flip-flops (rows 1, 2, 3), can create problems during circuit testing, however. In particular, a typical logic simulator cannot determine the state of the phase detector flip-flops (rows 1, 2, 3, 4). Similarly, a typical fault grader cannot fault grade phase detector 204 for the same reason. As can be seen in the schematic for phase detector 204 shown in Figure 2, the reset inputs 212A and 212B are not accessible external to phase detector 204. Thus, state-of-the-art logic simulators or fault graders are unable to put phase detector 204 into a known state by asserting its flip-flops' reset inputs 212A and 212B. The uncertainty of not knowing whether flip-flops 202 A and 202B are in the states represented by row 1 , 2 or 3 after power-up typically does not cause a problem during normal circuit operation as initial circuit outputs are not being compared to a response table, and the phase detector 204 will process the input signals 118 and 120 according to the phase-locked loop operation previously described regardless of the initial state of these outputs. Also, as we have indicated, phase detector 204 is designed to achieve final loop lock regardless of the initial frequency and phase difference between feedback signal 120 and reference signal 118.

Before phase detector 204 can be tested for defects using response tables, however, it typically must be initialized or put into a known state. In particular, it must be known whether phase detector 204 is in the states represented by rows 1, 2 or 3 of Table 1. Referring to Table 2, phase detector 204 can be initialized to the state represented by row 1 of Table 1 by clocking one input twice, the other input once (as illustrated below in Table 2); or to row/state 2 or 3 of Table 1 by clocking the appropriate input twice. The inputs are clocked automatically by signal 118 and 120 that are present either in a response table or embedded in the circuit under test. Table 2 shows the initialization sequence to achieve row 1 of Table 1.

Initial State: 1st: Clock 2nd: Clock : 3rd: Clock 206A 206B 204A 204A 204B 206A 206B 206A 206B 206A 206B

1 0 0 1 0 1 0 0 0

2 0 1 0 0 1 0 0 0

3 1 0 1 0 1 0 0 0

Table 2

Figure 3 shows phase detector 304, another illustrative embodiment of a conventional phase detector that may be used to implement phase detector 104 in Figure 1. Please see Motorola data sheets MC4344/MC4044 which is available from Motorola Corp., Schaumburgh, Illinois, and which is hereby incorporated herein by this reference for a general discussion of the phase detector of Figure 3.

Phase detector 304 uses Set-Reset (SR) flip-flops 302 A and 302B as its memory elements, rather than the D flip-flops used by phase detector 204. In addition to SR flip-flops 302A and 302B, phase detector 304 comprises input NAND gates 310D and 310E and output NAND gates 310B and 3 IOC. The output 308 A of input NAND gate 310D is coupled to the input 318A of SR flip- flop 302 A and is an input to output NAND gate 310B. The output 308B of input NAND gate 31 OE is coupled to the input 318B of SR flip-flop 302B and is an input to output NAND gate 3 IOC. The output 320B of output NAND gate 31 OB provides up line 126 and is also applied as an input to input NAND gate 310D using connection 322. The output 320C of output NAND gate 3 IOC provides down line 128 and is also applied as an input to input NAND gate

310E using connection 324. The reset circuit of phase detector 304 comprises NAND gate 310A, the inputs 314A, 314B, 315 A and 315B coupled to outputs 306A, 306B, 308A and 308B, respectively, and the output 316 applied as an input to NAND gates 310B and 3 IOC as well as to reset inputs 312A and 312B. Despite the differences from phase detector 204, the phase detector 304 is functionally similar and may also be used to implement the phase detector 104 of Figure 1.

SUMMARY OF THE INVENTION An aspect of the present invention is to provide a phase detector having an initialization circuit. The initialization circuit may place phase detectors embodying the present invention into a known state, eliminating the need for artificial forcing of states during logic simulation, enabling fault grading of phase detectors that use some form of memory element, facilitating fault grading of the circuits that use such phase detectors or otherwise improving testability, test complexity, and test cost of phase detectors or circuits that use them, for example.

An embodiment of the present invention, for example, provides a phase detector with an externally accessible initiallization node. In this embodiment, the phase detector includes a comparison circuit that compares a reference signal and a feedback signal to provide an output signal that represents at least one of the phase difference and the frequency difference between the reference signal and the feedback signal. In the present embodiment, the comparison circuit includes a memory element that it uses to provide the output signal. In particular, the memory element is a first flip-flop and a second flip-flop. Accordingly, the output signal is the output of the first flip-flop and the output of the second flip-flop. The output signal is coupled to a reset circuit. The reset circuit is fed back to a reset input of the comparison circuit to reset the comparison circuit in response to a predetermined output signal. The externally accessible initiallization node is also coupled to the reset input of the comparison circuit to provide access to the reset input external to the phase detector. By providing this external access, this initiallization node facilitates logic simulation, testing and/or fault grading of circuits containing this phase detector embodiment.

BRIEF DESCRIPTION OF THE DRAWINGS

Figure 1 illustrates an example of a conventional phase locked loop circuit;

Figure 2 shows a conventional phase detector that might be used in the phase locked loop circuit of Fig. 1;

Figure 3 illustrates an alternative conventional phase detector that might be used in the phase locked loop circuit of Fig. 1; Figure 4 illustrates an embodiment of a phase detector having an initialization circuit according to the present invention;

Figure 5 illustrates a phase detector having an initialization circuit and is an alternate embodiment of the present invention;

Figure 6 shows a phase detector having an initialization circuit and is an alternate embodiment of the present invention;

Figure 7 illustrates a phase detector having an initialization circuit and is an alternate embodiment of the present invention. DETAILED DESCRD?TION OF THE PREFERRED EMBODIMENTS

The present invention comprises a novel apparatus and method for facilitating or improving testing, simulation and/or fault grading of phase/frequency detectors or phase locked loop circuits that may use them. The following description is presented to enable a person skilled in the art to make and use the invention. Descriptions of specific applications are provided only as examples. Various modifications to the described embodiment will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments and applications without departing from the spirit and scope of the invention. Thus, the present invention is not intended to be limited to the described or illustrated embodiments, but should be accorded the widest scope consistent with the principles and features disclosed herein.

Figure 4 illustrates a phase detector 404 that is a presently preferred embodiment of the invention. Phase detector 404 uses a number of the same components as phase detector 204. In particular, it uses the same D flip-flops 202A and 202B, configured with the same reference voltage 203 applied to inputs 208A and 208B. It has the same reset inputs 212A and 212B.

Unlike phase detector 204, however, phase detector 404 includes an initialization circuit. The initialization circuit is used to accept using an externally accessible initialization node stimulus from a source external to a phase detector, such as from a logic simulator, a fault grader, a production tester, or other circuitry, for example, to put the phase detector into a known state. The source of external stimulus is not limited to a logic simulator, fault grader, production tester, or other embedded circuitry. Alternatively, an embedded circuit (not shown) can be employed to automatically (without requiring stimulus from a source external to the phase detector) put the phase detector into a known state at power up. However, such a power-up initialization circuit may itself be difficult to fault grade.

The initialization circuit of phase detector 404 has been integrated with its reset circuit. Embodiments of the present invention need not integrate the initialization circuit with the reset circuit, however. As illustrated in Figure 4, phase detector 404 replaces NAND gate 210 with AND gate 402 and NOR gate 406. Outputs 206 A and 206B are coupled to AND gate 402's inputs 414 A and 414B. AND gate 402's output 416 provides an input to NOR gate 406. Unlike phase detector 204, phase detector 404 includes an initialization input 408 which provides an input to NOR gate 406 through connection 412. Output 418 of NOR gate 406 is coupled to reset inputs 212A and 212B of D flip-flops 202 A and 202B.

During normal operation of a circuit in which phase detector 404 is used, the initialization circuit typically does not affect operation of the phase detector in the circuit. For example, in phase detector 404, the externally accessible initialization node 408 is tied to a low logic level such that the initialization input 408 will not affect operation of the phase detector 404. Phase detector 404 will operate similar to phase detector 204 with the AND gate 402 and NOR gate 406 behaving similar to the NAND 210 of Figure 2. Use of phase detector 404's initialization circuit, including initialization input 408, during circuit testing, can provide a variety of advantages. In particular, initialization node 408 simplifies the testing using response tables of phase detector 404 because a logic simulator can readily simulate the operation of hardware flip-flops 202A and 202B because the flip-flops can be easily set to a known state using the initialization circuit. Accordingly, for example, a logic simulator can clock data into the flip-flops and produce response tables that predict the power-up performance of phase detector 404 after initialization, without having to heavily rely on artificial forcing using specialized software commands.

During production testing, the outputs produced by a hardware circuit that uses phase detector 404 can be more easily predicted using a response table generated by logic simulation. The logic simulation determines for the production tester how many vectors are involved in asserting and de-asserting node 408 for initialization. Accordingly, modification of production test vectors to initialize phase detectors and masking of circuit responses to ignore unpredictable outputs can be more readily reduced or eliminated. As a result, embodiments of the present invention may reduce false rejections and save both test development time and production test time.

Finally, the initialization circuit of phase detector 404, including initialization node 408, facilitates fault grading of phase detectors 404 since the phase detector 404 can be easily put into a known state.

Figure 5 illustrates phase detector 504 which is an alternative embodiment of the invention. Phase detector 504 is similar to conventional phase detector 304. Components of phase detector 504 that correspond to identical components of phase detector 304 are labeled with primed reference numerals. In particular, similar to phase detector 304, phase detector 504 includes flip-flips 302A' and 302B'; input NAND gates 310D' and 31 OF, output NAND gates 310B' and 310C; outputs 308A' and 308B'; inputs 318A' and

318B'; inputs 312A' and 312B'; outputs 306A and 306B'; inputs 315 A' and 315B'; inputs 314A' and 314B'; output 316'; outputs 320B' and 320C; and connections 322' and 324'. These elements are all coupled together in the same manner described for phase detector 304, except an initialization circuit, similar to that of phase detector 404 of Figure 4, has been integrated into the reset circuit using AND gate 520 and NOR gate 506. Accordingly, an initialization input 508 along with output 316', provide an input to a NOR gate 506 through a connection 512. An output 518 of NOR gate 506 is then coupled to the input of NAND gates 31 OB' and 3 IOC.

The initialization circuit of phase detector 504, including initialization node 508, can be used in a similar manner to the initialization circuit of phase detector 404. In particular, it can be used to provide testing, simulation and/or fault grading advantages like those described above.

Figure 6 shows phase detector 604 which is another alternative embodiment of the present invention. Phase detector 604 is essentially the same as phase detector 404, except it includes a delay 602. Such a delay was described in U.S. Patent No. 4,814,726 as a mechanism useful to avoid a PLL dead band. This patent referenced a paper entitled, "AN ECL/PL FREQUENCY SYNTHESIZER FOR AM/FM RADIO WITH AN ALIVE ZONE PHASE COMPARER" by D. Presler and J. Siwinski, IEEE Transactions on Consumer Electronics, August 1981, pp. 220-226. As with U.S. Patent No. 4,814,726, this paper is also hereby incorporated herein by this reference.

Also, while the initialization circuits in the described embodiments have been implemented by changing components in a phase detector to integrate the initialization circuit with the existing phase detector reset circuit (e.g. replacing a NAND gate with an AND gate and a NOR gate), embodiments of the present invention could implement the initialization input in other ways. The phase detector 704 of Figure 7 is an embodiment of the present invention showing such an alternate implementation. Phase detector 704 is the same as the phase detector 204, except it implements the initialization node 708 using an N- channel FET 702. Each component in Figure 7 that is essentially the same as a corresponding component in Figure 2 is identified with a primed reference numeral identical to the reference numeral used to identify its corresponding component in Figure 2. The drain 706 of FET 702 is tied to reset line 216'. The source 710 of FET 702 is tied to a reference potential 712 such as ground. The initialization node 708 is coupled to gate 714 of FET 702. FET 702 can be turned on by biasing node 708 to pull reset line 216' to ground. Such a transistor could also be used in the phase detector 304 for example, to provide an initialization circuit for that detector. Embodiments of the present invention may replace parts of the described embodiments with logically equivalent circuits, for example.

While the invention has been described in terms of what is presently considered to be the preferred embodiments, the invention is not limited to or by the disclosed embodiments. The person of ordinary skill will readily appreciate that the invention can be applied beyond the particular systems mentioned as examples in this specification. The invention comprises all embodiments within the scope of the appended claims and/or supported by the disclosure.

Claims

WHAT IS CLAIMED IS:

1. A digital phase and frequency detector for use with a phase lock loop circuit responsive to a voltage controlled oscillator (VCO) feedback signal and a reference signal comprising: a first flip-flop coupled to receive the VCO feedback signal and to provide a first component of a first output signal upon receipt of a first component of the feedback signal; a second flip-flop coupled to receive the reference signal and to provide a first component of a second output signal upon receipt of a first component of the first reference signal; a reset circuit which monitors the first output signal and the second output signal and which provides a reset signal to both the first flip-flop and to the second flip-flop when the first component of the first output signal and the first component of the second output signal are provided; an externally accessible initialization node; and an initialization circuit coupled to the initialization node which provides the reset signal to both the first flip-flop and to the second flip-flop when a first component of an initialization signal provided to the initialization node.

2. The phase and frequency detector of claim 1, wherein the initialization circuit is coupled to the reset circuit to provide the reset signal to the first and second flip-flops using the reset circuit.

3. The phase and frequency detector of claim 1, wherein at least one of the flip-flops is a D-flip-flop.

4. The phase detector of claim 1, wherein the first output signal provides an up signal and the second output signal provides a down signal.

5. The phase and frequency detector of claim 1 wherein at least one of the flip-flops is an SR-flip-flop.

6. The phase and frequency detector of claim 1 wherein the reset circuit comprises: an AND gate coupled to the first and second flip-flops such that the AND gate provides a third output signal in response to the first and second output signals; a NOR gate coupled to the AND gate and the initialization circuit such that the NOR gate provides the reset signal in response to at least one of the third output signal and the initialization signal.

7. The phase and frequency detector of claim 6, wherein the initialization circuit comprises a conductive path that directly couples the initialization node and the initialization signal to the NOR gate.

8. The phase and frequency detector of claim 6, wherein at least one of the flip-flops comprises a D-flip-flop.

9. The phase and frequency detector of claim 6 wherein at least one of the flip-flops comprises an SR-flip-flop.

10. The phase and frequency detector of claim 6, wherein the reset circuit further comprises: a first NAND gate coupled to a reference node to receive the reference signal, the first NAND gate providing a fourth output signal in response to the reference signal; a second NAND gate coupled to the first NAND gate, the first flip-flop and the NOR gate such that the second NAND gate provides a fifth output signal in response to the fourth output signal, the first output signal and the reset signal and such that the first NAND gate provides the fourth output signal also in response to the fifth output signal; a third NAND gate coupled to a feedback node to receive the feedback signal, the third NAND gate providing a sixth output signal in response to the feedback signal; a fourth NAND gate coupled to the third NAND gate, the second flip- flop and the NOR gate such that the fourth NAND gate provides a seventh output signal in response to the sixth output signal, the second output signal and the reset signal and such that the third NAND gate provides the sixth output signal also in response to the seventh output signal.

11. The phase and frequency detector of claim 10, wherein the fifth output signal provides an up signal and the seventh output signal provides a down signal.

12. The phase and frequency detector of claim 10, wherein at least one of the first and second flip-flops is an SR-flip-flop.

13. The phase and frequency detector of claim 10, wherein the initialization circuit comprises a conductive path that directly couples the initialization control node to the NOR gate.

14. The phase and frequency detector of claim 6, wherein the NOR gate provides the reset signal through a delay.

15. The phase and frequency detector of claim 1 wherein the initialization circuit comprises: a transistor coupled to the reset circuit and having a control node; the initialization node is coupled to the control node such that the transistor provides the reset signal in response to the initialization signal.

16. The phase and frequency detector of claim 15, wherein the reset circuit includes a NAND gate coupled to the first and second flip-flops such that the NAND gate provides the reset signal when the first component of the first output signal and the second component of the second output signal is provided, and the initialization circuit includes a transistor coupled to the reset circuit and having a control node; the initialization node is coupled to the control node such that the transistor provides the reset signal in response to the initialization signal.

17. The phase and freguency detector of claim 16, wherein the reset circuit further comprises: a first NAND gate coupled to a reference node to receive the reference signal, the first NAND gate providing a fourth output signal in response to the reference signal; a second NAND gate coupled to the first NAND gate, the first flip-flop and the NAND gate such that the second NAND gate provides a fifth output signal in response to the fourth output signal, the first output signal and the reset signal and such that the first NAND gate provides the fourth output signal also in response to the fifth output signal; a third NAND gate coupled to a feedback node to receive the feedback signal, the third NAND gate providing a sixth output signal in response to the feedback signal; a fourth NAND gate coupled to the third NAND gate, the second flip- flop and the NAND gate such that the fourth NAND gate provides a seventh output signal in response to the sixth output signal, the second output signal and the reset signal and such that the third NAND gate provides the sixth output signal also in response to the seventh output signal.

18. A phase detector comprising: a comparison circuit having a reference input for receiving a reference signal, a feedback input for receiving a feedback signal and an output for providing an output signal that represents at least one of the phase difference and the frequency difference between the reference signal and the feedback signal; a memory element included in the comparison circuit wherein memory element is used to provide the output signal, wherein the memory element has a reset input adapted to receive a reset signal and wherein the memory element is adapted to reset upon receipt of a first component of the reset signal at the reset input; an externally accessible initialization node coupled to the reset input of the memory element such that the first component of the reset signal is provided to the reset input of the memory element upon receipt of a first component of an initialization signal at the initialization node.

19. The phase detector of claim 18, wherein the initialization node is directly coupled to the reset input of the memory element to provide the reset signal to the reset input.

20. The phase detector of claim 18, further comprising an initialization circuit wherein the initialization node is coupled to the reset input of the memory element through the initialization circuit and wherein the initialization circuit is directly coupled to reset input to provide the reset signal to the reset input.

21. The phase detector of claim 18, further comprising a reset circuit wherein the initialization node is coupled to the reset input of the memory element through the reset circuit and wherein the reset circuit is directly coupled to the reset input of the memory element to provide the reset signal to the reset input.

22. The phase detector of claim 18, wherein the memory element comprises: a first flip flop having a clock input, an output and a reset input wherein the clock input of the first flip flop provides the reference input of the comparison circuit; and a second flip-flop having a clock input, an output and a reset input wherein the clock input of the second flip flop provides the feedback input of the comparison circuit, the outputs of the first and second flip flops together provide the output of the comparison circuit and the reset inputs of the first and second flip flops together provide the reset input of the memory element.