WO1998029949A1

WO1998029949A1 - Single-phase domino time borrowing logic with clocks at first and last stages and latch at last stage

Info

Publication number: WO1998029949A1
Application number: PCT/US1997/023372
Authority: WO
Inventors: Thomas D. Fletcher
Original assignee: Intel Corporation
Priority date: 1996-12-27
Filing date: 1997-12-17
Publication date: 1998-07-09
Also published as: KR20000069742A; AU5800698A; JP2001507887A

Abstract

A domino logic circuit configuration including self-timed resets (752), a pulsed clock input terminal in a first stage (712), a self-terminating pulsed clock precharge circuit in a second stage (730) which also has a pulsed clock input terminal, and a full-keeper (734, 736) in the second stage, provides time borrowing capability and reduced sensitivity to clock jitter in high frequency designs. In an embodiment, both the evaluate of the first domino stage (718) of a block and the self-terminating precharge of the last domino stage (746) of the block are initiated by the rising edge of a pulsed clock (702). In a circuit configuration in accordance with the present invention, a time period approximately equivalent to three inverter delays is provided to turn off the inputs to a subsequent domino logic stage, thus providing adequate time to evaluate the first domino logic stage in each block.

Description

SINGLE-PHASE DOMINO TIME BORROWING LOGIC WITH CLOCKS AT FIRST AND LAST STAGES AND LATCH AT LAST STAGE

Background of the Invention

Field of the Invention

The present invention relates to high frequency circuit design for integrated circuits. More particularly, the present invention relates to domino CMOS logic circuits.

Background

Advances in semiconductor manufacturing technologies have allowed circuit designers to integrate tremendous numbers of transistors on a single die. For example, modern integrated circuits (ICs) commonly include several million transistors interconnected on a single, small substrate. Typically these are field effect transistors (FET). At the same time, computer architecture, and more particularly processor architecture, has gone in the direction of emphasizing shorter and shorter cycle times. These advances in semiconductor manufacturing and processor architecture have led designers to consider new ways of implementing basic circuit functions.

To produce ICs with shorter cycle times typically requires increasing the clock frequency at which these devices operate. Increasing clock frequencies means that fewer logic gate delays are permitted within each clock cycle. As described below, several styles of logic design have been developed to achieve high speed operation.

Static full CMOS logic requires one p-channel field effect transistor (PFET) for each n-channel field effect transistor (NFET). For complex logic gates this means either an NFET stack with a PFET OR structure, or an NFET OR structure with a PFET stack. Fig. 1(a) shows the transistor level configuration of a static full CMOS complex logic gate. Fig. 1(b) shows a logic symbol representing the logical function implemented by the circuit of Fig 1(a). The physical layout of these complex logic gate structures produces a substantial amount junction area, and thus parasitic capacitance, associated with the output node.

Reduced power, chip area and output capacitance can be obtained through the use of domino logic circuits. Domino logic reduces the layout and parasitic capacitance problems associated with static full CMOS complex logic gates. As will be understood by those skilled in the art, a reduction in parasitic capacitance permits higher speed and lower power operation. As compared to static circuits, domino circuits typically have a higher power density because they have more clock loading, and a higher activity factor per node. Further comparing static and domino circuits, domino logic circuits typically are more noise sensitive.

Domino logic refers to a circuit arrangement in which there are several series coupled logic stages having precharged output nodes. An aggregation of several series coupled domino logic stages is referred to as a domino block. Alternatively, the domino block is referred to as a pipestage, since it is often used to implement pipelined architectures in high speed CMOS logic integrated circuits. The output node of an individual logic stage is precharged to a first logic level, logic signals are then applied such that, depending on the logic function being implemented and the state of the various input signals, the output node can be switched to a second logic level. As each domino stage in the chain evaluates the output of the next stage may be enabled to switch. Since the precharged nodes "fall" in sequence, the operation has been analogized to falling dominoes, and hence the name for this type of circuit arrangement.

Many circuit configurations are possible within the general category of domino logic. Unique circuit configurations are sought by design engineers that satisfy the requirements of very high speed operation.

Various advanced forms of domino logic have been developed to increase the speed of operation. Single phase pulsed domino is one form of domino logic useful for high speed operation. Single phase pulsed domino logic can be implemented in both self-resetting and globally resetting forms. This style of logic design is susceptible to functional errors due to race conditions and therefore requires careful management of race conditions during the design process. For very high speed designs, single phase pulsed clock domino logic can be used in place of two phase domino logic. One of the problems with this type of design is that many of the conditions that were frequency dependent in two phase domino become self-timed race conditions and must be designed with additional margin to ensure functionality.

What is needed is a high speed domino logic circuit configuration that is tolerant of clock jitter, allows time-borrowing, and provides inherent race margin to ease the design of these circuits and to increase their operational reliability at the same time.

Summary of the Invention

The present invention provides circuit configurations that are operable as high speed single phase domino logic blocks that provide sufficient set-up and hold time so as to allow time-borrowing in the presence of clock jitter.

Briefly, in an embodiment, series coupled domino stages include self-timed resets, a pulsed clock input terminal in a first stage, a self-terminating pulsed clock precharge circuit in a second stage, which also has a pulsed clock input terminal, and a full-keeper in the last domino stage of a block.

In further aspects of the present invention, the first and second stages referred to above are respectively, the first and last domino stages of a domino logic block; alternatively, the first and second stages referred to above are respectively, a first and an intermediate domino stage of a domino block.

Brief Description of the Drawings

Fig. 1(a) shows the transistor level configuration of a static full CMOS complex logic gate.

Fig. 1(b) shows a logic symbol representing the logical function implemented by the circuit of Fig 1(a).

Fig. 2 shows the circuit configuration of a basic domino logic stage.

Fig. 3 shows the circuit configuration of a domino logic stage having a half keeper. Fig. 4 shows the circuit configuration of a domino logic stage having a full keeper.

Fig. 5 shows a two phase domino logic chain.

Fig. 6 shows the circuit configuration of domino logic stage having domino compatible inputs, a half-keeper, and a reset device.

Fig. 7(a) is a schematic diagram showing a domino pipestage embodying the pulsed clock inputs to first and last stages, and the latch in the last stage control mechanism of the present invention.

Fig. 7(b) is a timing diagram illustrating the timing relationship between various nodes in the circuit of Fig. 7(a).

Fig. 7(c) is a circuit diagram of a pulse extending inverter.

Detailed Description of the Invention

The detailed circuit configuration of an illustrative embodiment of the present invention is described below in the section labelled "Circuit Configuration". The operation of an illustrative embodiment of the present invention is described below in the section labelled "Circuit Operation".

Terminology

Delay unit, as used herein, refers to a time period substantially equal to one inverter delay. This time period may also be referred to as a unit delay.

The terms n-type domino, n-stack domino, and n-channel evaluate path, all refer to a domino stage in which the logical inputs to that domino stage control NFETs which create a path from the domino output node to ground. The terms p- type domino, p-stack domino, and p-channel evaluate path, all refer to a domino stage in which the logical inputs to that domino stage control PFETs which create a path from the output node to a positive voltage supply. Those skilled in the art will understand that domino circuit stages can be implemented with any suitable components and not only field effect transistors.

Evaluate, as used herein with respect to domino stages, refers to the domino output node going to an active state. This active state is a level different from the precharged state. Keeper refers to a circuit added to a dynamic node to maintain that node substantially at a predetermined voltage level. Typically, a keeper is added to a node that, in operation, will periodically be precharged high. The keeper supplies the charge necessary to compensate for the loss of charge due to various leakage paths, as well as loss of charge due to capacitive coupling of the node to other signal paths. A half-keeper is a circuit providing a switchable, direct, conductive pathway between the dynamic node and one voltage source, e.g., a positive voltage source, and therefore operable only to maintain the dynamic node at one level, e.g., a high level. A half-keeper circuit can be seen in Fig. 3. A full-keeper is a circuit providing a switchable, direct, conductive pathway between the dynamic node and two voltage sources, e.g., a positive voltage and ground, and therefore operable to maintain the dynamic node at either a high or low level. A full-keeper circuit can be seen in Fig. 4.

The term "gate" is context sensitive and can be used in two ways when describing integrated circuits. As used herein, gate refers to a circuit for reahzing an arbitrary logical function when used in the context of a logic gate. Gate refers to the insulated gate terminal of a three terminal FET when used in the context of transistor circuit configuration. Although a FET can be viewed as a four terminal device when the semiconductor substrate is considered, for the purpose of describing illustrative embodiments of the present invention, the FET will be described using the traditional gate-drain-source, three terminal model.

Jam latch refers to a circuit in which a pair of cross-coupled inverters has one of its two nodes electrically coupled to the output of a logic gate. The jam latch is also referred to as a full keeper.

Race condition refers to the operation of a circuit in which the result is dependent on the amount of delay, as measured from a common triggering event, such as a clock edge, experienced by signals as they propagate through the circuit.

Reset, in the field of digital circuit technology generally, refers to bringing an output node to a logical low, or zero. However, with respect to a domino logic stage, reset refers to bringing an output node to the "non-evaluate" state. That is, a domino stage having an n-channel evaluate path will reset to a high level, but a domino stage having a p-channel evaluate path will reset to a low level. Self-resetting domino stages are sometimes referred to as having atomic reset circuits. Alternatively, self -resetting domino are sometimes referred to as self- terminating. All these terms refer to domino stages having circuits that initiate precharging of the domino stage output node, when the output node evaluates.

Single phase refers to the operation of a domino logic circuit block, such that no time of the clock cycle is dedicated to precharging the domino output nodes. In other words, as evaluation ripples through the domino block, the stages that have passed on their output may be reset. This is in contrast to the operation of a two phase domino logic circuit block wherein a portion of the clock cycle is dedicated to resetting all the domino stages at substantially the same time.

Time borrowing, in the context of series connected, domino logic pipestages, refers to a process in which late arriving data is allowed to propagate through a latch boundary.

Zipper domino refers to a circuit configuration having a plurality of domino stages connected in series, where the domino stages are alternately n-channel evaluate path stages, and p-channel evaluate path stages.

In domino logic schemes, whether single phase or two phase, the operation of a domino gate within a clock cycle can be divided into four modes. These modes are referred to as evaluation, gapl, reset, and gap2. Evaluation refers to the period of time that the evaluate stack is turned on. Gapl refers to the period of time between the evaluate stack being turned off and the reset device being turned on. Reset refers to the period of time that the reset device is turned on. Gap2 refers to the period of time between the reset device being turned off and the evaluate stack being turned on.

Basic Domino Circuits

Figs. 2-4 illustrate basic domino logic stages, and Fig. 5 illustrates a domino logic chain.

Fig. 2 shows a conventional implementation of a 2-input NAND gate 210 in domino logic. NAND gate 210 comprises NFETs 211-213 coupled in series (i.e., an n-stack) between an output node 218 and ground, and a PFET 214 coupled between a voltage supply and output node 218. The gate of PFET 214 is coupled to the gate of NFET 211 and both gates receive input clock signal CLK. Data inputs B and A are shown coupled to the gates of NFETs 212 and 213 respectively. In operation, there are two phases, a precharge phase and evaluate phase. Alternative terms for these two phases are the precharge period and the evaluation period, respectively. In the precharge phase, output node 218 charges to a high level when CLK is low because NFET 211 is off, thus there is no conduction path to ground from output node 218 and at the same time PFET 214 is on, thus creating a conduction path from voltage supply Vcc to output node 218. For proper operation, signals A and B are expected to become stable prior to CLK going high. In the evaluate phase, CLK goes high thus turning off PFET 214 and turning on NFET 211. With NFET 211 turned on, there will be a conduction path from output node 218 to ground if both signals A and B are high. That is, if both NAND inputs are high, the output will go low during the evaluate phase, otherwise the output will remain high. Note that when output node 218 is not discharged through the n-stack during the evaluate phase, that output node 218 is "floating" high and its voltage will be subject to change due charge loss or gain though leakage currents and capacitive coupling to other signals.

Fig. 3 shows an implementation of a 2-input NAND gate 310 in domino logic including a half keeper. The half keeper overcomes the problem described above in connection with NAND gate 210 of Fig. 2, where the output node is subject to charge loss/gain while it is floating. This permits the clock frequency to be reduced and even permits the clock to be stopped while maintaining a high level at the output node of the domino logic stage. NAND gate 310 comprises NFETs 311-313 coupled in series between an output node 318 and ground, and a pair of PFETs 314-315 coupled in parallel between a voltage supply Vcc and output node 318. The gate of PFET 314 is coupled to the gate of NFET 311 and both receive input clock signal CLK. Data inputs B and A are shown coupled to the gates of NFETs 312 and 313 respectively. An inverter 317, in conjunction with PFET 315, implements the half -keeper function. Inverter 317 has its input coupled to output node 318 and its output coupled to the gate of PFET 315. In operation, when clock signal CLK rises PFET 314 turns off, but if either of inputs A or B remain low, output node 318 remains high, with PFET 315 providing the current necessary to overcome any leakage or capacitively coupled noise.

Fig. 4 shows an implementation of a 2-input NAND gate 410 in domino logic including a full keeper. Whereas the half keeper of NAND gate 310 of Fig. 3, maintains a high level at the output node of the domino logic stage, a full keeper operates to maintain, or reinforce, a high level or a low level. NAND gate 410 comprises NFETs 421-423 coupled in series between an output node 427 and ground, and a PFET 424 coupled between a voltage supply Vcc and output node 427. The gate of PFET 424 is coupled to the gate of NFET 421 and both receive input clock signal CLK. Data inputs B and A are shown coupled to the gates of NFETs 422 and 423 respectively. A cross-coupled pair of inverters 425 and 426 forms the full keeper. Inverter 426 has its output coupled to the input of inverter 425, and its input coupled to output node 427. Inverter 425 has its output coupled to output node 427.

As can be seen in Fig. 5, conventional domino circuits used with two-phase clocking, have clock ANDed NFET blocks configured to precharge in one clock phase, and to evaluate in the subsequent clock phase. An inverter typically separates the domino stages so that during precharge, the inputs to the next stage are forced low. During the evaluate phase the precharged node may transition to a low and the signal will ripple like dominos falling down through the logic. This permits the inputs to each block to come from a latch or a preceding stage of domino logic. A half keeper is typically used to hold a high level at the precharged output node of the domino logic stages.

Still referring to Fig. 5, the inputs to the domino are latched when the evaluate phase begins and open during the precharge phase. The data is setup by the end of the precharge phase before the next clock edge.

Circuit Configuration

Fig. 6 illustrates a domino logic stage 600 used to form a pipestage in an illustrative embodiment of the present invention. As will be understood by those skilled in the art, various logic functions can be implemented by variously configuring the NFETs coupled between domino output 618 and ground. In the example illustrated in Fig. 6, two parallel, two high AND stacks are used. A first AND stack is made by coupling NFETs 602, 604 in series between domino output 618 and ground as shown in Fig. 6. A second AND stack is made by coupling NFETs 606, 608 in series between domino output 618 and ground as shown in Fig. 6. Two PFETs 614, 616, are coupled in parallel between a power supply and domino output 618. PFET 616 is the reset device, and provides the charge needed to return domino output 618 from a low level to a high level. PFET 616 has a gate 612 which is coupled to a reset signal. In embodiments of the present invention at least one of the domino stages implements a self -resetting circuit, and at least one domino stage implements a self-tailored clocked reset. The half keeper function of domino logic stage 600 includes an inverter 610. The input of inverter 610 is coupled to domino output 618. The output of inverter 610 is coupled to the gate of PFET 614. Inverter 610 together with PFET 614 implement the half keeper function.

When domino output 618 is high, the output of inverter 610 goes low, and the low on the gate of PFET 614 turns on PFET 614 so that a conductive path between the power supply and domino output 618 exists. In this way, a high level is maintained at domino output 618 by the half-keeper. When domino output 618 evaluates low, the output of inverter 610 goes high, and consequently PFET 614 turns off.

When gate 612 of PFET 616 is at a high level, PFET 616 is turned off and no conductive path exists between the power supply and domino output 618. When gate 612 of PFET 616 is at a low level, PFET 616 is turned on and a conductive path exists between the power supply and domino output 618. In this way, domino output 618 is reset to a high level. As domino output 618 returns to a high level, the output of inverter 610 goes low, consequently PFET 614 turns on. Typically PFETs 614, 616, are sized such that PFET 614 has a greater on- resistance than PFET 616.

Referring to the illustrative example of Fig. 7(a), a pipestage 700 embodying the present invention is described. The logic functions shown for the domino stages and static logic stages in Fig. 7(a) are for illustrative purposes, and those skilled in the art will recognize that any logic function can be selected for each of the stages.

As can be seen in Fig. 7(a), pipestage (also called a domino block), 700 has three domino stages each coupled in series through a static inverting logic gate. A node 702 is coupled to the input of a non-inverting buffer 704 and to one input of an AND gate 710. AND gate 710 has an output 712 which is coupled to a logical function input terminal of the first domino stage in the pipestage. In this case, the logical input function terminal is the gate of an NFET 714.

The first and second domino stages each contain self-resetting circuitry. In the first domino stage of pipestage 700 the self -resetting function is accomplished by an inverter 720, an inverter 722, a PFET 724, and a PFET 726. Inverter 720 has an input coupled to the first domino stage output 718, and an output coupled to the input of inverter 722, and to the gate of PFET 724. PFET 724 is coupled between Vcc and output node 718 so as to form a switchable conductive path therebetween. Inverter 722 has an output coupled to the gate of PFET 726. PFET 726 is coupled between Vcc and output node 718 so as to form a switchable conductive path therebetween. Similarly, in the second domino stage of pipestage 700 the self-resetting function is accomplished by an inverter 734, an inverter 736, a PFET 738, and a PFET 740. Inverter 734 has an input coupled to the second domino stage output 732, and an output coupled to the input of inverter 736, and to the gate of PFET 738. PFET 738 is coupled between Vcc and output node 732 so as to form a switchable conductive path therebetween. Inverter 736 has an output coupled to the gate of PFET 740. PFET 740 is coupled between Vcc and output node 732 so as to form a switchable conductive path therebetween.

The last domino stage in pipestage 700 includes a jam latch and a data dependent, clocked reset circuit. More particularly, a pair of cross-coupled inverters 748, 750 form a jam latch with one side of cross coupled inverters 748, 750 connected to last domino stage output node 746, and the other side of cross- coupled inverter 748, 750 connected to an input of a NAND gate 752. The output of NAND gate 752 is connected to the gate of PFET 754. PFET 754 is coupled between Vcc and output node 746 so as to form a switchable conductive path therebetween for precharging output node 746. In the illustrative embodiment of the present invention shown in Fig. 7(a) first domino stage output node 718 is coupled to an AND gate 728 having an output. The output of AND gate 728 is coupled to a logical function input terminal of a second series coupled domino stage, i.e., the gate of NFET 731, so as to form node 730. An output node 732 of the second domino stage is coupled to an AND gate 742 having an output. The output of AND gate 742 is coupled to a logical function input terminal of a third series coupled domino stage, i.e., the gate of NFET 745, so as to form node 744. An output node 746 of the third domino stage is coupled to the input of an inverter 756.

In a preferred embodiment, inverter 756 is implemented as a pulse extending inverter. A circuit diagram for a pulse extending inverter is shown in Fig. 7(c).

Circuit Operation

The operation of an illustrative embodiment of the present invention is described with reference to Figs. 7(a) and 7(b). In this illustrative description, the pulse width of the initial pulse provided to pipestage 700, i.e., pulsed clock signal applied to node 702, shown in Fig. 7(a), is approximately equal to three delay units, and the various domino compatible logical inputs are assumed to be in the appropriate states for the domino chain to evaluate. Generally, a circuit configuration embodying the present invention operates such that one domino stage, within a pipestage, is evaluating while another domino stage, within the same pipestage is resetting, where both the evaluation and the reset are initiated based on the assertion of a common timing signal, and the last serially coupled domino stage within the same pipestage latches its output in parallel with transmitting its output.

The evaluation of the logical function implemented by the domino logic block shown in Fig. 7(a) begins with the application of a clock pulse to node 702. From this common point, the clock pulse is buffered by a buffer 704. At the same time, the clock pulse is applied to an input terminal of AND gate 710. The output of buffer 704 is applied to node 706 which includes an input terminal of NAND gate 752. The output of AND gate 710 is coupled to a logical function input terminal of the first domino stage of the domino logic block. For the purpose of description, it will be assumed that all the logical signals necessary for the entire domino block to evaluate will be in the appropriate states. It will be readily seen, for example, that the inputs signals coupled to both AND gate 710 and NFET 716 will need to be active (i.e., high) in order to start the domino evaluation sequence. In fact, input signal 708 and the input to NFET 716 need to be active such that there is sufficient pulse overlap at the gates of NFETs 714 and 716 to pull down the precharged output node 718. This overlap is sometimes referred to as pulse intersection or pulse coalescence. Once output node 718 goes low, the self-timed reset circuit of this domino stage begins the process of precharging the output back to a high level.

As shown in Fig. 7(b), when output node 718 goes low, the output of NAND gate 728 goes high. This high going signal is applied to node 730 which includes the gate of NFET 731. By making NFET 731 conductive (i.e., "turned on"), output node 732 is coupled to ground and therefore brought low. Node 732 going low causes node 744 to go high. As with the other domino stages described above, a high at the gate of NFET 745 causes output node 746 of this domino stage to go low, that is, to "evaluate".

In the illustrative embodiment, the last of the serially coupled domino stages, unlike the other domino stages in this domino block, does not employ a self- timed reset. The reset of this last domino stage involves a jam latch coupled on one side to output node 746 and on its other side to a first input terminal of two-input NAND 752. A second input terminal of NAND 752 is coupled to the output of buffer 704. In operation, the content of the jam latch follows the state of output node746. After the last stage evaluates and the output node is low, the reset of the output does not begin until the buffered clock pulse arrives at NAND 752. The output of NAND 752 then goes low which turns on p-channel precharge device 754. P-channel device 754 conducts current so as to bring output node 746 to a high level. When output node 746 is high, the output of inverter 748 goes low, which in turn makes the output of NAND 752 high, and consequently p-channel device 754 turns off. Conclusion

The present invention provides circuit configurations that are operable as high speed single phase domino logic blocks that provide the set-up and hold time necessary to allow time-borrowing in the presence of clock jitter. Domino logic circuit configurations embodying the present invention provide time borrowing capability and reduced sensitivity to clock jitter in high frequency designs. These embodiments typically include self-timed resets, a pulsed clock input in a first stage, a self-terminating pulsed clock precharge circuit in a second stage, which also receives the same pulsed clock as the first stage, and a full-keeper in the last domino stage of a block.

Embodiments in accordance with the present invention, typically operate such that the evaluate of the first sequential domino stage of the block, and the self- terminated precharge of a second domino stage of the block are initiated by the rising edge of the pulsed clock. A time period approximately equivalent to three inverter delays is provided to turn off the inputs to a subsequent domino logic stage, thus providing adequate time to evaluate the first domino logic stage in each block. A time period equivalent to four inverter delays is provided from the clock edge for both the evaluate and precharge turn-off to reach the last domino logic stage in each block. A full keeper in the last domino stage of the block acts to hold the data in case the pulsed clock is stopped.

Those skilled in the art will recognize that changes such as replacing the common timing signal seen by the first stage and the self-terminating reset circuit with two separate signals having similar timing characteristics or changing the logical functions implemented by the domino stages, do not depart from the disclosed invention.

It will be understood that various other changes in the details, materials, and arrangements of the parts and steps which have been described and illustrated in order to explain the nature of this invention may be made by those skilled in the art without departing from the principles and scope of the invention as expressed in the subjoined Claims.

Claims

What is claimed is:

1. A domino circuit, comprising: a plurality of domino stages coupled in series; wherein each one of the plurality of domino stages has at least one logical function input terminal; wherein at least one of the plurahty of domino stages has a reset function input terminal; and wherein at least one reset function input terminal of a first domino stage is coupled to at least one logical function input terminal of a second domino stage.

2. The circuit of Claim 1, wherein at least one of the plurahty of domino stages is self -resetting.

3. The circuit of Claim 1 , wherein the plurality of domino stages are coupled via static logic gates.

4. The circuit of Claim 1 , wherein the plurality of domino stages comprise n- type domino stages.

5. The circuit of Claim 4, wherein the n-type domino stages are coupled via p- type domino stages.

6. The circuit of Claim 1 , wherein the second one of the plurality of domino stages is the last domino stage of the series.

7. The circuit of Claim 1 , wherein the second one of the plurality of domino stages is intermediate of the first and last domino stages of the series.

8. A domino circuit, comprising: a first signal source having an output terminal; a second signal source having an output terminal; and a plurality of domino stages coupled in series; wherein each one of the plurality of domino stages has at least one logical function input terminal; wherein at least one of the plurality of domino stages has a reset function input terminal; and wherein the first signal source output terminal is coupled to a logical function input terminal of a first one of the plurality of domino circuit stages, and the second signal source is coupled to a reset input terminal of a second one of the plurality of domino circuit stages.

9. The circuit of Claim 8, wherein at least one of the plurality of domino stages is self -resetting.

10. The circuit of Claim 8, wherein the plurality of domino stages are coupled via static logic gates.

11. The circuit of Claim 10, wherein the plurality of domino stages comprise n- type domino stages.

12. The circuit of Claim 11 , wherein the n-type domino stages are coupled via p-type domino stages.

13. The circuit of Claim 8, wherein the second one of the plurality of domino stages is the last domino stage of the series.

14. The circuit of Claim 8, wherein the second one of the plurality of domino stages is intermediate of the first and last domino stages of the series.

15. The circuit of Claim 8, wherein the first signal source and the second signal source are each operable to produce at their respective output terminals, signals having active-going edges at substantially the same time.

16. A method of operating a domino circuit having a plurality of domino stages coupled in series, wherein each one of the plurality of domino stages has at least one logical function input terminal, and at least one of the plurality of domino stages has a reset function input terminal, the method comprising the steps of: a) producing a first signal and a second signal; b) applying the first signal to the functional input terminal of least one domino stage; and c) applying the second signal to the reset input terminal of the second domino stage.

17. The method of Claim 16, wherein the first signal and the second signal are pulses occurring substantially simultaneously; the functional input terminal of step (b) is in the first domino stage of the series coupled plurality of domino stages, and the reset input terminal of step (c) is in the last domino stage of the series coupled plurality of domino stages.

18. A method of operating a domino logic block, the method comprising the steps of: a) resetting a first domino stage in the pipestage; and b) at substantially the same time, evaluating a second domino stage in the domino block.

19. The method of Claim 18, wherein said first domino stage is the first domino stage in said domino block and said second domino stage is the last domino stage in said domino block.

20. The method of Claim 18, further comprising the step of self-resetting said second domino stage.