WO1998036446A2 - A method for fabricating a small area of contact between electrodes - Google Patents
A method for fabricating a small area of contact between electrodes Download PDFInfo
- Publication number
- WO1998036446A2 WO1998036446A2 PCT/US1997/017711 US9717711W WO9836446A2 WO 1998036446 A2 WO1998036446 A2 WO 1998036446A2 US 9717711 W US9717711 W US 9717711W WO 9836446 A2 WO9836446 A2 WO 9836446A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- conductive layer
- accordance
- chalcogenide
- integrated circuit
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/066—Patterning of the switching material by filling of openings, e.g. damascene method
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8418—Electrodes adapted for focusing electric field or current, e.g. tip-shaped
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/50—Resistive cell structure aspects
- G11C2213/52—Structure characterized by the electrode material, shape, etc.
Definitions
- the present invention relates generally to semiconductor fabrication techniques and, more particularly, to a method for fabricating a small contact area between an upper and lower electrode for use in phase changeable memory devices such as, for
- chalcogenide memory cells For example, chalcogenide memory cells.
- phase change materials i.e., materials that can be electrically switched between generally amorphous and generally crystalline states or between different resistive states while in crystalline form, for
- phase change materials is disclosed, for example, in U.S. Patent No. 5,296,716, in the names of Ovshinsky et al., the disclosure of which is incorporated herein by reference.
- U.S. Patent No. 5,296,716 is believed to indicate generally the state of the art, and to
- phase change materials can be electrically switched between a first structural state where the material is generally amorphous and a second structural state where the material has a generally
- the material may also be electrically switched between different detectable states of local order across the entire spectrum between the completely amorphous and the completely crystalline states. That is, the switching of such materials is not required to take place between completely amorphous and completely crystalline states, but rather, the material can be switched in incremental steps reflecting changes of local order to provide a "gray scale" represented by a
- the material upon its state. For example, in its amorphous state the material exhibits lower
- chalcogenide memory cells requires that a region of the chalcogenide memory material
- the chalcogenide active region be subjected to a current pulse typically with a
- current density may be accomplished by first creating a small opening in a dielectric
- the second dielectric layer is typically about 40 Angstroms thick.
- chalcogenide material is then deposited over the second dielectric and into the opening.
- the chalcogenide material provided from the chalcogenide material to the lower electrode material by forming a.
- Firing involves passing an initial high current pulse through the structure that
- the active regions of the chalcogenide memory cells within the pores are
- pore dimensions i.e., diameter, thickness and volume
- the present invention is directed at overcoming, or at least reducing the effects
- the electrodes are further selected to provide
- the memory cells may be made smaller to
- the invention comprises a method of manufacturing a semiconductor
- the present invention comprises an integrated circuit device
- a substrate having a primary surface comprising: a substrate having a primary surface; a conductive layer provided on the
- the conductive layer having a raised portion; an insulative layer
- the present invention comprises an integrated circuit
- a first electrode having a first portion and a second portion, a width of the
- first electrode narrowing continuously in a direction from the second portion to the first
- FIG. 1 is a fragmentary cross sectional view of the deposition of a layer of
- FIG. 2 is a fragmentary cross sectional view of the deposition of a layer of
- FIG. 3 is a fragmentary cross sectional view of a contact pattern that is etched
- FIG. 4(a) is an overhead view of a generally rectangular contact pattern formed
- FIG. 4(b) is an overhead view of a generally circular contact pattern formed
- FIG. 5 is fragmentary cross sectional view of the device after the resist material
- FIG. 6 is a fragmentary cross sectional view of a portion of the layer of
- FIG. 7 is a fragmentary cross sectional view of the device after the contact
- FIG. 8 is a fragmentary cross sectional view of the depositing of a layer of
- Fig. 9 is a fragmentary cross sectional view of planarization of the layer of
- CMP chemical mechanical planarization
- FIG. 10 is a fragmentary cross sectional view of a chalcogenide material layer
- FIG. 11 is a fragmentary cross sectional view of a layer of conductive material
- FIG. 12 is a fragmentary cross sectional view of the layer of chalcogenide
- FIG. 13 is a fragmentary cross sectional view of a second layer of insulative
- FIG. 14 is a fragmentary cross sectional view of the second layer of insulating
- FIG. 15 is a fragmentary cross sectional view of the complete chalcogenide
- chalcogenide memories is presented that provides an area of contact with the lower
- electrode with the upper electrode is formed by creating a tip on the lower electrode.
- the lower electrode having a minimum area of contact as small as
- the total current passing through the chalcogenide active region is two
- the preferred embodiment allows the memory cells to be made smaller and thus allow the production of denser memory
- FIGs. 1 to 15 a preferred embodiment
- CVD chemical vapor deposition
- the layer 22 of conductive material may have a substantially
- uniform thickness ranging from 5000 to 7000 Angstroms, and preferably will have a
- Substrate 20 may
- a conductive material such as, for example, silicon, TiN, Carbon,
- WiSi x or Tungsten, and preferably will be comprised of silicon.
- the substrate 20 will be comprised of silicon.
- a lower electrode grid (not shown) used for accessing an
- a layer 23 of silicon oxide is deposited onto the substrate 22, preferably by
- the layer 24 of resist material preferably will have a substantially uniform thickness of
- a contact pattern 26, is then etched in the resist layer 24 and the silicon oxide
- the contact pattern 26 may be formed from the resist
- FIG. 4(a) or as a substantially circular block as shown in FIG. 4(b).
- pattern 26 is preferably formed using a conventional contact hole mask resulting in the
- contact pattern 26 preferably will be approximately 0.4 ⁇ m.
- the resist layer 24 is then removed using conventional stripping techniques
- oxide layer 23 contact pattern is used as a masking layer when the polysilicon layer 22
- the base of the tip 30 preferably will have a base rninimum lateral dimension of
- Tip 30 will preferably have a height of approximately 2000 Angstroms.
- the removal of the silicon oxide layer pattern 23 is accomplished using conventional
- a layer 32 of insulative material is deposited onto the polysilicon layer 22,
- CVD to isolate the polysilicon layer 22, including the tip 30, as illustrated in
- the layer 32 of insulative material may have a substantially uniform thickness
- Layer 32 of insulative material may be comprised of silicon oxide
- silicon nitride or silicon nitride, and preferably will be comprised of silicon oxide.
- the layer 32 of insulative material is then preferably planarized using a
- CMP chemical mechanical planarization
- the CMP process is performed to expose the top surface 24 of the tip 30 formed on the
- polysilicon layer 22 that may also be referred to as the lower electrode.
- the chalcogenide memory cell is then formed incorporating the tip 30 of the
- polysilicon layer 22 using conventional semiconductor processing techniques such as,
- the chalcogenide memory cell preferably includes a layer 34 of chalcogenide
- ILD interconnect dielectric
- the chalcogenide material layer 34 may be deposited using conventional thin
- chalcogenide compositions preferably is approximately 500 Angstroms thick.
- Concentrations of Ge are typically above about 15 % and range from a low of about
- the chalcogenide compositions for these memory are particularly preferred.
- cells comprise a Te concentration of about 56%, a Ge concentration of about 22% , and
- the materials are typically characterized as
- Te.Ge b Sb l0(Ha+b) where a is equal to or less than about 70% and preferably between
- the carbon layer 35 is preferably 600 Angstroms thick and is provided over the
- chalcogenide layer 34 using conventional thin film deposition techniques, as shown in
- Layer 36 of conductive material is deposited over the carbon layer 35 using conventional deposition techniques, as further shown in FIG. 11.
- the layer 36 of conductive material is preferably titanium nitride (TiN), but may
- the ILD layer 38 is then applied using conventional thin
- the ILD layer 38 preferably is approximately 3500
- the ILD layer 38 is then etched back,
- Upper conductive grid interconnect 40 may be formed by first
- the upper conductive grid 40 material may comprise materials such as,
- Ti titanium
- TiN titanium
- aluminum preferably it will comprise aluminum
- diodes are further provided in series with the chalcogenide memory cells
- the present invention includes the
Abstract
Description
Claims
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP53133898A JP4747231B2 (en) | 1996-10-02 | 1997-10-02 | Method for manufacturing a small area contact between electrodes |
AT97955058T ATE238605T1 (en) | 1996-10-02 | 1997-10-02 | DEVICE AND METHOD FOR PRODUCING A SMALL-AREA CONTACT BETWEEN ELECTRODES AND DEVICE THEREFOR |
DE69721306T DE69721306T2 (en) | 1996-10-02 | 1997-10-02 | DEVICE AND METHOD FOR PRODUCING A SMALL AREA CONTACT BETWEEN ELECTRODES, AND DEVICE THEREFOR |
AU80525/98A AU8052598A (en) | 1996-10-02 | 1997-10-02 | A method for fabricating a small area of contact between electrodes |
EP97955058A EP0946975B1 (en) | 1996-10-02 | 1997-10-02 | A device and method for fabricating a small area of contact between electrodes |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/724,816 US6147395A (en) | 1996-10-02 | 1996-10-02 | Method for fabricating a small area of contact between electrodes |
US08/724,816 | 1996-10-02 |
Publications (3)
Publication Number | Publication Date |
---|---|
WO1998036446A2 true WO1998036446A2 (en) | 1998-08-20 |
WO1998036446A3 WO1998036446A3 (en) | 1998-10-22 |
WO1998036446A9 WO1998036446A9 (en) | 1999-02-04 |
Family
ID=24912031
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1997/017711 WO1998036446A2 (en) | 1996-10-02 | 1997-10-02 | A method for fabricating a small area of contact between electrodes |
Country Status (8)
Country | Link |
---|---|
US (12) | US6147395A (en) |
EP (3) | EP1296377B1 (en) |
JP (1) | JP4747231B2 (en) |
KR (1) | KR100466675B1 (en) |
AT (3) | ATE238605T1 (en) |
AU (1) | AU8052598A (en) |
DE (3) | DE69739678D1 (en) |
WO (1) | WO1998036446A2 (en) |
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JP2002540605A (en) * | 1999-03-25 | 2002-11-26 | オヴォニクス インコーポレイテッド | Electrically programmable memory device with improved junction |
WO2003050872A1 (en) * | 2001-12-12 | 2003-06-19 | Matsushita Electric Industrial Co., Ltd. | Nonvolatile memory |
US6607974B2 (en) | 2000-07-14 | 2003-08-19 | Micron Technology, Inc. | Method of forming a contact structure in a semiconductor device |
EP1369925A2 (en) * | 2002-05-10 | 2003-12-10 | Hewlett-Packard Company | A phase change material electronic memory structure |
WO2005011011A1 (en) * | 2003-07-21 | 2005-02-03 | Unaxis Usa Inc. | Etching method for making chalcogenide memory elements |
US6900517B2 (en) | 2002-04-09 | 2005-05-31 | Matsushita Electric Industrial Co., Ltd. | Non-volatile memory with phase-change recording layer |
DE102004031742A1 (en) * | 2004-06-30 | 2006-01-19 | Infineon Technologies Ag | Production of a sub-lithographic contact structure of a memory cell in a semiconductor component comprises preparing a front-end-of-line semiconductor wafer with an electrical contact, depositing an insulating layer and further processing |
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