WO1998038732A1

WO1998038732A1 - Quadrature modulation and demodulation circuit for an oscillating waveform

Info

Publication number: WO1998038732A1
Application number: PCT/CA1998/000148
Authority: WO
Inventors: David Ian Hoult
Original assignee: National Research Council
Priority date: 1997-02-27
Filing date: 1998-02-27
Publication date: 1998-09-03
Also published as: AU6085198A

Abstract

A circuit is disclosed which can be used in quadrature analysis of modulated waveform, in a modulation system for generating the waveform or in a filter circuit which uses both demodulation and modulation. The demodulation system generates in-phase and quadrature-phase values respectively of the waveform, by repeatedly sampling in respective ones of a plurality of sampling time periods an amplitude of the waveform and generating a series of sequential output values dependent upon the sampled amplitude, with each output value being associated with a respective one of the sampling time periods. The sampling means comprises a switch which is responsive to a periodic timing signal to determine said sampling time periods. Further switches are provided for switching communication of the output values for switched time periods alternately between output terminals, the switches also being responsive to a periodic timing signal to determine said switched time periods. The timing signals are generated such that the sampling switch is actuated such that each sampling time period is shorter than the respective switched time period, commences after the start time of the respective switched time period and ceases prior to the end time of the respective switched time period.

Description

QUADRATURE MODULATION AND DEMODULATION CIRCUIT FOR AN OSCILLATING WAVEFORM

This invention relates to electronic circuits which can be arranged, using the same principles, to effect either highly accurate in-phase and quadrature-phase (l-Q) modulation or highly accurate l-Q demodulation of an oscillating waveform.

The above modulator and de-modulator circuits can also be used in combination in an apparatus for nuclear magnetic resonance imaging of a sample.

In accordance with another aspect, the above modulator and demodulator circuits can be used in combination together with low frequency filters to create a radio frequency filter of a character unattainable with conventional radio frequency circuitry. Background information is disclosed in the following books and papers:

1. C-N. Chen and D. I. Hoult, "Biomedical Magnetic Resonance Technology", Adam Hilger, Bristol, U.K. , 1989.

2. C. Olmstead and M. Petrowski, "Digital IF Processing", RF Design, September, 1994.

3. B. Brannon, "Using Wide Dynamic Range Converters for Wide Band Radios", RF Design, May, 1995.

4. Mini-Circuits "RF/IF Designer's Handbook", Mini-Circuits Division of Scientific Components, Brooklyn, NY, 1992.

5. D. I. Hoult, "The NMR Receiver: A Description and Analysis of Design", Progress in NMR Spectroscopy, 12, 41, 1978.

It has been known for many years that both phase and amplitude information can be impressed on an oscillating waveform by suitable modulation techniques. It is also well-known that the original information can be extracted from the impressed waveform by suitable demodulation. When phase and amplitude information is represented diagrammatically by two independent and perpendicular vector variables - an in-phase component I and a quadrature phase component Q, the resulting sum vector has an amplitude A = _|2 + Q2 while the phase is θ = arctan[Q/l], as shown in the Figures described hereinafter. Such orthogonal variables are often conveniently represented as a complex number C = I + iQ, where i is the square root of minus one. Thus, when presented with an oscillating waveform of type V = A cos (ωot + θ), and, for purposes of comparison, two reference voltages of type R = cos ωot and S = sin ωot, either of which effectively defines time t = 0, so-called l-Q demodulation recovers as two separate voltages the original signals I = A cos θ and Q = A sin θ. Conversely, given the two voltages I and Q and simple oscillating reference signals cos ωot and sin ωot, l-Q modulation generates the waveform of type V. It is common for amplitude A and phase θ to be dynamic variables rather than static constants. For example, A may vary as exp[- kt^], where k is a constant, while θ may vary as θ = ωit, where ωi can be positive or negative. In this instance, signals I and Q also vary; they change in amplitude and also oscillate with frequency α>ι. l-Q modulation and l-Q demodulation are used in many branches of electronics, usually as part of a chain of frequency changing and amplification such as is used in radio communications equipment, nuclear magnetic resonance imagers etc. l-Q modulation normally occurs at the commencement of a transmitter chain before the first frequency change, whereas demodulation normally occurs at the end of a receiver chain and is applied to the final intermediate frequency. However, many other uses are possible.

In practice l-Q demodulation is problematic when a large dynamic range is needed, and it is partly to get round the problems that the communications industry is turning to intermediate frequency sampling.

One problem is that zero frequency - DC - is part of the demodulated spectrum. Thus any offsets on the detected voltages I and Q, such as can be created by imperfect operation of the demodulation process, give a spurious signal at zero frequency.

A second problem is that it is notoriously difficult with conventional l-Q demodulators (e.g. diode ring mixers) to preserve a 90° phase difference between the two sinusoidal references R and S, and hence between the supposedly perpendicular resultant signals I and Q. For example, reference 4 above quotes a specified maximum phase error of 3° for a commercially available l-Q demodulator, and describes this value as "good" (pages 11-13). Even when the phase difference is initially set very accurately, with temperature change and over time there may be drift and even a phase error of 1° can have serious consequences in many applications.

When the phase θ of the signal to be demodulated varies with time, for example as θ = ωit, an error in the phase difference between the two reference signals generates a spurious signal or "ghost" at the negative frequency -ωi that can be confused with a genuine signal. The problems disappear when the final l-Q demodulation is avoided and the prior intermediate frequency is sampled with an analogue-to-digital converter (ADC), and excellent articles on this subject can be found in references 2 and 3 set forth above. The price paid, however, is a loss of dynamic range because the resolution of ADCs drops considerably with the necessary higher sampling frequencies needed. For example, two 16 bit ADCs, such as Analog Devices' AD1382, sampling l-Q data may have a maximum sampling rate of 500 kSPS (kilo samples per second) and a bandwidth of ± 250 kHz, i.e. 500 kHz. When sampling at 40 MSPS with a single ADC, a bandwidth 40 times greater can be accommodated and thus the noise floor is _40 times, or nearly 3 bits, larger. Thus to maintain the same dynamic range, a 13 bit ADC is needed. However, at the moment, typically only a 10 bit ADC can function this quickly, and so there is a loss of approximately 18 dB in dynamic range. Thus there is a need for a more accurate l-Q demodulation process so that high- resolution ADCs can again be employed. l-Q modulation presents concomitant problems, and drift of the two reference signals' phase difference coupled with gain errors in the modulator can result in inaccurate values of amplitude A and phase θ in the resultant modulated waveform. Thus there is also a need for a more accurate l-Q modulation process.

It is one object of the present invention to provide a circuit for use in in- phase and quadrature-phase demodulation of a complex waveform such that highly accurate values of the in-phase and quadrature phase components of that waveform may be obtained.

It is a further object of the present invention to provide a circuit useful for highly accurate in-phase and quadrature-phase modulation of a required waveform from signals representative of the in-phase and quadrature values of that waveform.

It is a yet further object of the present invention to provide a apparatus for use in nuclear magnetic resonance imaging which is improved relative to those presently available and uses the techniques set forth in the above modulator and de-modulator circuits.

It is a yet further object of the present invention to provide a radio frequency filter which is improved relative to those presently available and uses the techniques set forth in the above modulator and de-modulator circuits.

According to a first aspect of the invention there is provided a circuit for use in quadrature analysis of a first signal, defined by a modulated waveform, and for producing second and third signals defining in-phase and quadrature-phase values respectively of the first signal, the circuit comprising: a first input terminal for the first signal, a second output terminal for the second signal, a third output terminal for the third signal; sampling means for sampling in respective ones of a plurality of sampling time periods an amplitude of the first signal and for generating a series of sequential output values dependent upon the sampled amplitude, with each output value being associated with a respective one of the sampling time periods, the sampling means being responsive to a periodic timing signal to determine said sampling time periods; switching means for switching communication of the output values for switched time periods alternately between the second and third terminals, the switching means being responsive to a periodic timing signal to determine said switched time periods; timing signal generating means for generating said periodic timing signals for application to the sampling means and the switching means; the timing signal generating means being arranged such that the timing signals determine the respective switched time periods between a respective start time and a respective end time; the timing signal generating means being arranged such that the timing signals actuate the sampling means such that each sampling time period is shorter than the respective switched time period, commences after the start time of the respective switched time period and ceases prior to the end time of the respective switched time period.

Preferably the sampling means comprises a switch having a first path for effecting connection to the switching means and a second path for effecting disconnection from the switching means.

Preferably the circuit includes a low pass filter at the first and second terminals for filtering out high frequency components from the second and third signals.

Preferably the circuit is arranged for producing a fourth signal defining an inverted in-phase value and a fifth signal defining an inverted quadrature-phase value and including a fourth output terminal for the fourth signal, and a fifth output terminal for the fifth signal; wherein the switching means includes: a first switch, a second switch, a third switch, each switch having an actuating input, a first contact and two second contacts and arranged so that application of a signal at the actuating input effects switching of communication through the switch from a first route between the first contact and one of the second contacts to a second route between the first contact and the other of the second contacts and an arrangement of conductors defining: a first circuit path from the sampling means, through the first route of the first switch, through the first route of the second switch, to the second output terminal; a second circuit path from sampling means, through the first route of the first switch, through the second route of the second switch, to the fourth output terminal; a third circuit path from the sampling means, through the second route of the first switch, through the first route of the second switch, to the third output terminal; a fourth circuit path from the sampling means, through the second route of the first switch, through the second route of the second switch to the fifth output terminal.

Preferably the circuit is arranged for producing a fourth signal defining an inverted in-phase value and a fifth signal defining an inverted quadrature-phase value and including a fourth output terminal for the fourth signal, and a fifth terminal for the fifth output signal; wherein there is provided a first comparator arranged to receive the second and fourth signals and to effect subtraction of the fourth signal from the second signal and wherein there is provided a second comparator arranged to receive the third and fifth signals and to effect subtraction of the fifth signal from the third signal, each of the comparators including a low pass filter for filtering out high frequency components from the signals.

Preferably the timing signal generating means includes means for receiving a clock pulse signal and means for calculating the timing signals from the clock pulse signal such that the timing signals for the sampling means and the timing signals for the switching means are both related to the clock pulse signal.

Preferably a timing signal for the switching means is calculated by dividing the clock pulse signal by a first number and the timing signals for the sampling means are calculated by dividing the clock pulse signal by a second number smaller than the first number and by generating a timing offset in the timing signals of the sampling means relative to the timing signals of the switching means so as to lie between the timing signals of the switching means.

Preferably the circuit is arranged for producing a fourth signal defining an inverted in-phase value and a fifth signal defining an inverted quadrature-phase value and including a fourth output terminal for the fourth signal and a fifth output terminal for the fifth signal; wherein the switching means includes: a first switch, a second switch, a third switch, each switch having an actuating input, a first contact and two second contacts and arranged so that application of a signal at the actuating input effects switching of communication through the switch from a first route between the first contact and one of the second contacts to a second route between the first contact and the other of the second contacts and an arrangement of conductors defining: a first circuit path from the sampling means, through the first route of the first switch, through the first route of the second switch, to the second terminal; a second circuit path from sampling means, through the first route of the first switch, through the second route of the second switch, to the fourth terminal; a third circuit path from the sampling means, through the second route of the first switch, through the first route of the second switch, to the third terminal; a fourth circuit path from the sampling means, through the second route of the first switch, through the second route of the second switch to the fifth terminal; wherein first and second timing signals for the switching means are calculated by dividing the clock pulse signal by a first number and a second larger number respectively and wherein the timing signals for the sampling means are calculated by dividing the clock pulse signal by a second number smaller than the first number and the second number and by generating a timing offset in the timing signals of the sampling means relative to the timing signals of the switching means so as to lie between the timing signals of the switching means.

According to a second aspect of the invention there is provided a circuit for generating a first signal, defined by a modulated waveform, from second and third signals defining in-phase and quadrature-phase values respectively of the first signal, the circuit comprising: a first terminal for the first signal, a second terminal for the second signal, a third terminal for the third signal; waveform assembling means for taking values of the second signal and the third signal and for assembling the values sequentially to form the first signal, each value being taken for a respective one of a plurality of set time periods, the assembling means being responsive to a timing signal to determine said set time periods; conductor means for defining paths each connecting to the assembling means from a respective one of the second terminal and the third terminal; switching means for switching for a switched time period between each of the paths in turn, the switching means being responsive to a timing signal to determine said switched time periods; timing signal generating means for generating said timing signals for application to the assembling means and the switching means; the timing signal generating means being arranged such that the timing signals determine the respective switched time periods between a respective start time and a respective end time; the timing signal generating means being arranged such that the timing signals actuate the assembling means such that each set time period is shorter than the respective switched time period, commences after the start time of the respective switched time period and ceases prior to the end time of the respective switched time period.

Preferably the assembling means comprises a switch having a first path for effecting connection to the switching means and a second path for effecting disconnection from the switching means.

Preferably there is provided a band pass filter arranged to pass only the frequency of the modulated waveform.

Preferably the circuit includes: means for generating at a fourth terminal from the second signal an inverted second signal having an amplitude dependent upon the second signal; means for generating at a fifth terminal from the third signal an inverted third signal having an amplitude dependent upon the third signal; wherein the conductor means defines four paths each connecting to the assembling means from a respective one of the second, third, fourth and fifth terminals.

Preferably the switching means includes: a first switch, a second switch, a third switch, each switch having an actuating input, a first contact and two second contacts and arranged so that application of a signal at the actuating input effects switching of communication through the switch from a first route between the first contact and one of the second contacts to a second route between the first contact and the other of the second contacts and an arrangement of conductors defining: a first circuit path from the second terminal, through the first route of the second switch, through the first route of the first switch, to the assembling means; a second circuit path from the third terminal, through the first route of the third switch, through the second route of the first switch, to the assembling means; a third circuit path from the fourth terminal, through the second route of the second switch, through the first route of the first switch, to the assembling means; a fourth circuit path from the fifth terminal, through the second route of the third switch, through the second route of the first switch to the assembling means.

Preferably a timing signal for the switching means is calculated by dividing the clock pulse signal by a first number and the timing signals for the assembling means are calculated by dividing the clock pulse signal by a second number smaller than the first number and by generating a timing offset in the timing signals of the assembling means relative to the timing signals of the switching means so as to lie between the timing signals of the switching means.

Preferably the timing signals for the switching means are calculated by dividing the clock pulse signal by a first number and the timing signals for the assembling means are calculated by dividing the clock pulse signal by a second number smaller than the first number and by generating a phase offset in the timing signals of the assembling means so as to lie between the timing signals of the switching means.

According to a third aspect of the invention there is provided an apparatus for use in detection of nuclear magnetic resonance signals which uses the modulation and de-modulation circuits defined above.

According to a fourth aspect of the invention there is provided a filter for an oscillating waveform which uses the modulation and de-modulation circuits defined above.

Embodiments of the invention as applied to, but not limited to, the discipline of nuclear magnetic resonance, will now be described in conjunction with the accompanying drawings in which:

Figure 1 is a schematic illustration of the vector nature of amplitude and phase showing their resolution into in-phase and quadrature components.

Figure 2 is a schematic illustration of the architecture of a nuclear magnetic resonance imaging spectrometer. Figure 3 is a schematic illustration of a circuit according to the present invention for effecting l-Q demodulation.

Figure 4 is a timing diagram for the timing signals of the circuit of Figure 3.

Figure 5 is a schematic illustration of a circuit according to the present invention for effecting l-Q modulation.

Figure 6 is a timing diagram for the timing signals of the circuit of Figure 5.

Figure 7 is a schematic illustration of a circuit according to the present invention for effecting intermediate frequency filtering with the circuits of Figures 3 and 5.

In Figure 2 is shown a schematic layout for a nuclear magnetic resonance imaging system. The architecture of this system is well known to those skilled in the art and familiar to those skilled in other branches of radio frequency (RF) electronics. This system includes a high power superconducting magnet 16 within which a sample 17 (which may be a human) is located, and a transmitter and receiver that include respectively an l-Q modulator 2, an l-Q demodulator 28 and a heterodyne frequency- changing assembly 7. At a location on the sample to be imaged is provided a transmitting and receiving radio frequency probe 18 generally in the form of a coil. Signals to and from the coil are communicated through an RF transmit/receive switch 15 so that the coil can act both as a transmitter for transmitting signals derived from the l-Q modulator 2 and can act as a receiver for receiving signals for transmission to the l-Q demodulator 28.

While for clarity, a conventional schematic representation of l-Q modulator 2 is herein shown, the l-Q modulator 2 is of the type shown in more detail in Figure 5 and described hereinafter. The l-Q demodulator 28 (also conventionally represented for clarity) is of the type shown in Figure 3 and also described in more detail hereinafter.

The l-Q modulator 2 receives the two analogue signals lm and Qm at two input terminals 3 and 4 from two digital-to-analogue converters (DACs) 1 that are under computer control, and in the conventional representation shown, in-phase and quadrature phase reference signals R and S from a frequency source 35. The l-Q modulator 2 acts to generate a signal, controlled in amplitude and phase and shown schematically at 5, which is supplied to an output terminal 6 of the l-Q modulator 2. The signal 5 at the terminal 6 is then changed in frequency to the nuclear magnetic resonance operating frequency and its power boosted, by passage through filter 8, mixer 9, filter 10, mixer 11, filter 12, and power amplifier 13. It is felt that these elements of frequency changing and amplification are sufficiently well-known that further description is unnecessary.

As is well known, the transmission of the boosted signal 14, which may be a shaped pulse, to the sample 17 through the probe 18 acts to induce in the probe 18 a resultant radio frequency signal 19 from the sample which is amplified by low-noise amplifier 20. The received signal is then changed in frequency in the heterodyne assembly comprising mixer 23, filter 24, mixer 25 and filter 26 until it is submitted to the l-Q demodulator 28 as the waveform 27 to be demodulated. Again, it is felt that the architecture of a heterodyne receiver is sufficiently well known that further description is unnecessary. The output from the filter 26 is applied to an input terminal 29 of the l-Q demodulator 28, which in this conventional representation also receives in-phase and quadrature phase reference signals R and S from frequency source 35. The l-Q demodulator 28 supplies output signals Id and Qd at terminals 30 and 31. After filtering in identical filters 32 and 33, the received signals are passed to dual analogue-to-digital converters 34, which in turn render the received signals available for processing in a computer.

Turning now to Figures 3 and 4, the construction and operation of the l-Q demodulator circuit are shown in detail. The demodulator circuit of Figure 3 can be used for nuclear magnetic resonance imaging systems as shown in Figure 2 but also has other uses.

The demodulator of Figure 3 comprises the terminals 29, 30 and 31 as previously described. The intermediate frequency input waveform 27 at the terminal 29 is applied to a buffer 40 of conventional construction. The signal from the buffer 40 is applied to a sampling means 41 that has the form of a switch 42. The circuit further includes a switching system generally indicated at 47 including individual switching elements 48, 49 and 50.

Switch 42 defines a first path from an input contact 43 to a first output contact 44 and a second path from the input contact 43 to a second output contact 45. A switching action from the first path to the second path is effected by application of a timing signal to an input terminal 46.

The sampling means defined by the switch 42 therefore provides an output value at the output contact 44 which is dependent upon the instantaneous amplitude of the waveform input signal at the terminal 29 with that output value being applied to the contact 44 for a period of time dependent upon the application of the timing signal at the input terminal 46. When the timing signal is not applied at the input terminal 46, the waveform signal from terminal 29 is unused, being connected through the second path to the output contact 45 and thence to ground via a 10 kΩ resistor.

Each of the switching elements 48, 49 and 50 is similar in construction to the switch 42 in that each defines a first path from an input contact to a first output contact and a second path from the input contact to a second output contact. A switching action from the first path to the second path is effected by application of a timing signal to an input terminal.

The switching means 47 provides, through the first switch 48 of the switching means and through the second and third switches 49 and 50 of the switching means, four separate paths for communication of the sample from the output contact 44 through to four separate output contacts 53, 54, 55 and 56. The path to the output contact 53 is communicated through the first path of the switch 48 and through the first path of the switch 49. The path to the output contact 54 is communicated through the first path of the switch 48 and through the second path of the switch 49. The path to the output contact 55 is communicated through the second path of the switch 48 and through the first path of the switch 50. The path to the output contact 56 is communicated through the second path of the switch 48 and through the second path of the switch 50. The output terminals 53 and 54 of the switching system are connected so as to provide input signals to a first analyzer element 60 and the outputs 55 and 56 of the switching system are connected so as to provide input signals to a second analyzer element 70. The analyzers are identically constructed and each of the analyzer elements 60 and 70 comprises a precision instrumentation amplifier 61 , 71 of the highest quality which is arranged to provide an output at terminals 30 and 31 which is proportional to the difference between its input signals.

The amplifier 61 includes a compensation network defined by an adjustable resistor Rc 62 and adjustable capacitor Cm 63. Resistors R_c and capacitors Cm allow the frequency characteristic of the amplifier 61 to be adjusted. The ratio of resistors R_s 64 and RG 65 defines a gain for the amplifier. Components 71 , 72, 73 and 74 perform the same function for analyzer 70, allowing the two analyzers to be accurately matched with regard to their frequency characteristics. Resistors Rs 64, 74 can be changed by up to 1 % to allow the gains of analyzer elements 60 and 70 to be set equal. The outputs from the respective amplifiers 60 and 70 are communicated to the respective output terminals 30, 31, thence to the respective filters 32 and 33 (if needed, q.v.) and to the analogue-to-digital converters.

Timing signals for the switches, including the sampling switch 42 and the switching switches 48, 49 and 50, are provided by a timing signal generation system 80, and temporal relations are shown in Figure 4. The system includes a terminal 81 to which is applied an oscillating signal which can be generated with accurate frequency. The signal from the terminal 81 is transmitted through a square wave generating system 82 which acts to convert the oscillating signal at the terminal 81 into a square wave. The system 82 includes a Schmitt trigger 83 the input to which is biased by a capacitor resistor arrangement 84. The square wave from the Schmitt trigger 83 is indicated as a signal CLK (clock) and this is applied to a binary counter 86. The binary counter provides four outputs (with the prefix 'D' for demodulator) indicated as DO, D1, D2 and D3, each of which is defined by a division of the input CLK signal by a selected power of two, as shown in Figure 4. Thus the output signal DO is a division of the clock signal by two, the output signal D1 is a division of the clock signal by four, the signal D2 is a division of the clock signal by eight and the output signal D3 is a division of the clock signal by sixteen.

The same output signals are communicated to the l-Q modulator as schematically indicated at 87.

The output signal D1 is communicated to a D-type flip-flop 88 along with the signal DO. An input control signal DOFF/ for actuating the circuit is indicated at terminal 89.

The output signal DSAM from the D-type flip-flop 88 is supplied to the sampling switch 42 via terminal 46. As indicated in the timing diagram Figure 4, this output signal has the same frequency as signal D1 but is offset in phase by 90°.

The signal D2 or its inverse D2/ is applied to the switch 48 through the exclusive-OR gate 91 and terminal 51. The choice of D2 or D2/ is determined by the control signal DCONJ/ applied at terminal 90. The signal D3 is applied to both switches 49 and 50 via terminal 52.

It will be noted by inspection of the timing diagram that the signal DSAM provides, at each application, a sampling of the input IF signal for a relatively short time period. At each application, this time period starts at point P and ends at point Q. It will be further noted that the switch 48 is switched from a first path to a second path by the signal D2, or from a second path to a first path by signal D2/, and that this switching occurs outside the sampling periods as defined between the timing points P and Q in Figure 4. Similarly the switching of the switches 49 and 50 occurs under control of the signal D3 at times outside the sampling periods.

In other words the switching system 47 is actuated by the control signals so as to switch in a given order between the four paths defined heretofore and to effect that switching prior to the time point P at which sampling commences and subsequent to the time point Q at which sampling terminates. Thus the switching is in place before the sampling is effected and remains in place for the duration of the sampling.

The design therefore samples analogically the 5 MHz intermediate frequency (IF) signal 27 available at terminal 29 at four times its frequency, but then routes the analogue samples appropriately to the two instrumentation amplifiers 61 and 71 with the aid of GaAs RF switches 48, 49 and 50. Using fast TTL logic, the 74F163 binary counter 86 divides the 80 MHz reference signal at terminal 81 from a high stability source (in our case, a frequency synthesizer) to obtain the three controls, DSAM at 20 MHz, D2 at 10 MHz and D3 at 5 MHz, for the Mini-Circuits YSWA-2-50DR absorptive GaAs single pole, double throw switches 42, 48, 49 and 50.

The use of 80 MHz with division by 16, rather than 40 MHz with division by 8, is for the use of a phase-shifting facility in the modulator, and will be discussed later.

These switches have rise times of typically 1.5 ns, and so the routing performed by switches 48, 49 and 50 is well in place before switch 42 opens for 25 ns. Figure 4 shows how the four outputs from the switches, terminals 53 - 56, each receive a sample of the IF signal 27 once per cycle. With the control DCONJ/ set high, sampled signals A, B, C, D, etc. are passed to the instrumentation amplifiers in the following order: sample A to terminal 53; sample B to terminal 55; sample C to terminal 54; sample D to terminal 56; sample E to terminal 53 and so on.

As the instrumentation amplifiers (Analog Devices AMP-01) that follow cannot pass frequencies above about 200 kHz, they put out at terminal 30 the signal Id that is the average of the difference A minus C, and at terminal 31 the signal Qd that is the average of the difference B minus D, in other words, direct voltages insofar as input waveform 27 is of constant amplitude and at exactly 5 MHz. Thus the instrumentation amplifiers also perform a filter function corresponding to filters 32 and 33 of Figure 2. However, if lower frequency filtering is required for some reason, for example slow ADCs, additional filters must be added. Clearly, with the phase relationships shown in Figure 4 between the IF signal and the switch controls (which could be considered to constitute the references R and S for the detector 28 in Figure 2), there is a positive output at terminal 30 and a smaller positive output at terminal 31. However, at a later time, if the IF input signal 27 at terminal 29 is not exactly 5 MHz, the phase relationships will have altered, and with them the voltages at terminals 30 and 31. A full analysis (not set out herein as it is not necessary for a full understanding of the invention) shows that a normal l-Q demodulator has been made where the outputs at terminals 30 and 31 depend on the cosine and sine of the phase difference between the input waveform 27 and a 5 MHz reference whose time origin, shown in Figure 4, may be considered to be the mid-point of signal DSAM, signals D2/ and D3 being high. The key point is that because of the exactly repetitive sampling at four times the intermediate frequency for time durations during which switching means 47 is not changing, the two outputs are exactly 90° apart in phase. Further, as the instrumentation amplifiers are high quality, low noise devices with very little offset and drift, the outputs are highly stable and of very accurately equal gains.

It is apparent that other permutations, combinations and deletions of the switching scheme described above may be applied and are envisaged to be within the scope of the invention.

In one example, the switching means 47 is replaced by a single pole, four- way switch.

In another possible application, which is technically inferior, the outputs of terminals 54 and 56 are not employed, and the instrumentation amplifiers 61 and 71 are replaced by unbalanced amplifiers.

As a further example, with the control DCONJ/ at terminal 90 set low, control D2 is not inverted before being passed to the switch 48, and sampled signal is passed to the instrumentation amplifiers in the order sample A to terminal 55; sample B to terminal 53; sample C to terminal 56; sample D to terminal 54; sample E to terminal 55 and so on. Clearly, with the phase relationships shown in Figure 4, there now is a small positive output at terminal 30 and a larger positive output at terminal 31. A full analysis shows that, if the two outputs at terminals 30 and 31 are considered to be the real and imaginary part respectively of a complex number, then, when DCONJ/ is asserted low, that number becomes the complex conjugate C*, with a 90° phase change, of the original output C which is produced with control DCONJ/ set high . The circuit, in common with most designs of demodulator, responds to odd harmonics of the intermediate frequency, so a filter 26 in Figure 2 is needed before the demodulator, if any higher frequency spurious signals or noise are present. The RF switches 42, 48, 49, and 50 should pass only small currents to avoid non-linear on- resistance effects. Thus 10 kΩ resistors 66, 67, 76 and 77 are included between the switches and the instrumentation amplifiers 61 and 71 to minimize high frequency currents that could be passed by the amplifiers' input capacitances. Capacitors to ground should not be placed at terminals 53 through 56 in an attempt to filter the signals. Such capacitors would charge and discharge through the switches, and if the various time constants in the two channels differ, the average voltage output amplitudes will also differ. At first sight, this behavior seems bizarre, for any lowpass filter must surely give the average voltage as its output. However, because switching can change the source impedance, a simple linear analysis cannot be applied - the circuit is non-linear and the high-frequency behavior "mixes" with the low frequency behavior.

When the intermediate frequency of the input waveform 27 departs significantly from 5 MHz, causing oscillating signals to be emitted by the l-Q demodulator, the phase difference between the two signals Id and Qd at terminals 30 and 31 can depart from 90° if the instrumentation amplifiers 61 and 71 are unmatched. Lack of matching causes errors to be greatest at high frequencies of about 100 kHz close to the amplifiers' cut-off frequency. However, the greatest dynamic range is obtained by running the following ADCs 34 at or close to their maximum sampling rate, and then using digital signal processing methods to reduce the bandwidth to that desired. Thus a compensation network 62, 63 and 72, 73 is included with the gain resistor R_g 65, 75 of each amplifier. Adjustment of the capacitor C_m 63, 73 changes slightly the mid-frequency gain and phase (say at 50 kHz) while the value of the resistor R_c 62, 72 determines the bandwidth. With the values shown, the conversion gain is about +17 dB with a maximum output of ±5 V and a cut-off frequency (-3 dB) of 250 kHz. The addition of resistor R_c 62, 72 not only tailors the frequency response to the ADC

Nyquist frequency, but also prevents 5 MHz components in the switched signals from overloading the front ends of the amplifiers. The spectrum of magnetic resonance signals typically covers much less than the available ADC bandwidth of 500 kHz, and within a spectral range of ±10 kHz, the phase error is less than the current measurement accuracy of ±0.2°. A 1% gain trim is included with the instrumentation amplifiers, and this allows the gains of the two signal channels to be set to considerably better than 0.1%. The DC offsets on the outputs were -2.7 mV and -0.3 mV and changed by less than 0.3 mV when the demodulator was turned off with the aid of control line DOFF/. If desired, these offsets can easily be annulled by the addition of a potentiometer to the AMP-01 instrumentation amplifiers' nulling connections. Finally the mostly low- frequency noise on the outputs is less than 200 μV.

Thus, over the desired bandwidth of ±10 kHz, the sampling l-Q demodulator described above effectively reduces the ghost and DC artifacts to less than -60 dB relative to the signal, the residual error being mainly due to drift in the gains of the two amplifiers.

Exactly the same sampling principles can be used in reverse to build a precision, narrow-band l-Q modulator, and a schematic representation is shown in Figure 5 with its corresponding timing diagram in Figure 6. To facilitate comparison with Figure 3, the circuit should be followed from right to left, rather than the more usual left to right.

In Figure 5 is shown the l-Q modulator 2 which acts to generate the modulated waveform at terminal 6 from control inputs applied at terminals 3 and 4 also shown in Figure 2. The in-phase and quadrature signals at terminals 3 and 4 respectively are applied to two identical differential buffers 100 and 101 which comprise four high quality operational amplifiers 102, 103, 104 and 105 arranged such that the in- phase input signal lm at terminal 3 is duplicated at the output of buffer amplifier 102, the inverted in-phase input signal -l_m is generated at the output of buffer amplifier 103, the quadrature phase signal Qm is generated at the output of buffer amplifier 104 and the inverted quadrature phase signal -Q_m is generated at the output of buffer amplifier 105. Variable resistors 106 and 107 allow the gains of buffer amplifiers 103 and 105 to be set each to -1 with great accuracy. Variable resistors 108 and 109 allow adjustment of the output offsets of buffer amplifiers 103 and 105 respectively so that in the absence of the in-phase and quadrature signals lm and Qm, the constant DC output of buffer 102 is the same as the constant DC output of buffer 103 and the constant DC output of buffer 104 is the same as the constant DC output of buffer 105. It will then become apparent that in the absence of inputs at terminals 3 and 4, the amplitude of the modulated waveform at terminal 154 is correctly zero.

The four signals l , -lm, Qm and -Q are applied through attenuators 110 and 111 as inputs to the switching system 120 which is in effect identical to the switching system 47 of the l-Q demodulator in that it includes switches 128, 129 and 130 arranged as previously described for switches 48, 49 and 50 and controlled by inputs with the prefix 'M' for modulator M2 or M2/ and M3 as previously described for inputs D2 or D2/ and D3 through duplicate exclusive-OR gate 166. Thus the switching means 120 has available at its output 125 one of the four input signals. A difference between the I- Q demodulator and the l-Q modulator therefore lies merely in the direction in which signals are passed through the switching system. In the l-Q demodulator of Figure 3, the sampled intermediate frequency signal is distributed by the switching system to terminals 53, 54, 55 and 56 in the specified order; in the l-Q modulator of Figure 5, the in-phase and quadrature signals l_m and Q_m and their inverses are presented from terminals 121, 122, 123 and 124 by the switching system to terminal 125 and thence to a waveform assembling element, which is defined by a sampling means 140, in the appropriate order and with the appropriate timing as shown in Figure 6.

The values applied as inputs to the switching system 120 are applied in turn as an input to the waveform assembling element 140. That element comprises a switch 141 with output terminal 144 and input terminals 142 and 143. The output of the switching system 120 available at terminal 125 is passed as input to terminal 142 of the switch 141 while input terminal 143 is connected to ground via a 56 Ω resistor. The assembled sampled waveform is generated at the contact 144 of the switch 141 and is applied through a buffer generally indicated at 150 to the output terminal 6. The control signal MSAM from duplicate flip-flop 165 for the assembling element 140 and the control signals M2 or M2/ and M3 for the switching system 120 are supplied from the timing signal generating system 160 which is substantially symmetrical to the system 80 of the demodulator of Figure 2, but with the addition of phase control circuitry 163, 164 and 169. Thus the system includes a binary counter 161 which operates from the same clock signal CLK generated by the system 82 of the demodulator. Indeed, controls MSAM, M2 or M2/ and M3 could be replaced with signals DSAM, D2 or D2/ and D3 without loss of functionality of the modulator.

The signal from the l-Q modulator at terminal 6 is passed to a bandpass filter 8 (Figure 2) that removes harmonics present in the assembled waveform and the output is present at terminal 154. It is felt that the construction of such bandpass filters is sufficiently well known that a description is not needed.

The modulator includes a phase control system as part of the timing signal generation system. The phase control system comprises a comparator 169 which receives the binary control signals DO, D1, D2 and D3 schematically shown at 162 from the demodulator and binary control signals PO, P1 , P2 and P3 schematically shown at 163 supplied by the user. The output of the comparator at terminal 170 is passed through inverter 164 to binary counter 161 at the 'Clear¹ input terminal 171. Application of a low voltage at terminal 171 synchronously resets the binary counter to zero with the next clock CLK pulse, and levels MO, M1, M2 and M3 become low.

Once again, therefore, three control lines MSAM, M2 or M2/ and M3 govern the switches 141, 128, 129 and 130, selecting in turn, from the OP-16 buffers 102, 103, 104 and 105, samples of voltages +l_m, +Q_m, -l_m and -Q_m to be presented to an AD811 buffer amplifier. Again, the paths through the 4-way switch 120 are in place before the sampling switch 141 closes, and they remain in place until after sampling has ceased. Thus there is no corruption of the sampled voltages and because the sampling is at four times the intermediate frequency of 5 MHz, the 5 MHz component of the assembled waveform associated with voltage l_m is extremely accurately in quadrature phase with the 5 MHz component of the assembled waveform associated with voltage Q_m. The modulator is followed by a 5 MHz, 6-pole elliptic bandpass filter (8, not shown in detail) at the intermediate frequency that removes harmonics and leaves a pure sinusoid of the desired amplitude and phase as shown in Figure 6. Note that the buffer amplifier outputs 102 - 105 are attenuated (110, 111) as a simple means of protecting the GaAs FET switches 129 and 130 from excess voltage. The in-phase and quadrature components of the 5 MHz signal are accurately 90° apart to the limit of our measurement accuracy of ±0.2° and the gain trim resistors 106 and 107 allow adjustments of the two components' amplitudes to better than 0.1%. The output of the l-Q modulator is adjusted to 7 dBm maximum into 50 Ωwith the aid of resistors 151 and 152 that adjust the gain of the output buffer amplifier, and this level is obtained when either input voltage is ±5 V. The non-linearity at this maximum level is less than 0.5%.

The phase of the modulator output 5 (Figure 2) may be changed in discrete increments, relative to the phase of the l-Q demodulator reference, by clearing the counter 161 in Figure 5 at a selected point in the counting cycle of the counter 86 in Figure 3. The 74F85 comparator 169 compares the state of the demodulator count DO - 3 (162) with a 4 bit control byte P0 - 3 (163) and when the two are the same, a high level is present at terminal 170 of the comparator. This is inverted in inverter 164, and the resulting low level resets the 74F163 counter 161 at the next clock pulse. Thus the timing diagram of Figure 6 has its temporal origin an integral number of clock pulses following that of the timing diagram of Figure 4 as determined by the user, and the phase of the modulator output (and ultimately that of the transmitter of Figure 2) may hence be set in 22.5° increments. Implementation of this facility is the reason the 80 MHz clock is divided by 16 to obtain controls D3 and M3. If the phase shifting facility is not needed, controls MSAM, M2 or M2/ and M3 can be replaced by control signals DSAM D2 or D2/ and D3 with no loss of modulative ability, and only a 40 MHz clock is needed: the initial division by two to obtain DO can be dispensed with. Alternatively, as the maximum frequency tolerated by the logic circuitry is about 100 MHz, the IF can then be as high as 12.5 MHz.

Once again, it is apparent that other permutations, combinations and deletions of the switching scheme described above may be applied and are envisaged to be within the scope of the invention.

As the specifications of the demodulator and modulator are superior, a joint use of them is to make an IF bandpass filter with a specific symmetrical transfer function that can be as narrow as desired. The minimum bandwidth is determined only by the stability of the 80 MHz local oscillator. In Figure 7, the l-Q modulator and l-Q demodulator are shown in block form and an intermediate frequency waveform is applied at input terminal 29. However, the DC or low frequency (0 - 200 kHz) outputs I and Qd of the demodulator at terminals 30 and 31 are passed through audio or low frequency filters 180 and 181 having a desired transfer function and thence passed to the two input terminals 3 and 4 of the l-Q modulator. The modulator regenerates a signal at the intermediate frequency and passes it to the output terminal 6. This arrangement impresses the filter characteristics upon the signal in a band centered on the intermediate frequency. In a demonstrative implementation, the transfer function of this arrangement was examined with a Hewlett Packard network analyzer using as before an oscillator frequency of 80 MHz and an input signal of nominal frequency 5 MHz. When two simple RC filters of nominal time constant 200 μs were employed as filters 180 and 181 , the measured transfer function was Lorentzian centered at 5.0000 MHz with the expected width at the -3 dB points of 1.56 kHz and an effective Q-factor of 3200. Clearly, this scheme is not restricted to the use of RC filters and any filter type may be envisaged.

Since various modifications can be made in my invention as herein above described, and many apparently widely different embodiments of same made within the spirit and scope of the claims without departing from such spirit and scope, it is intended that all matter contained in the accompanying specification shall be interpreted as illustrative only and not in a limiting sense.

Claims

I CLAIM:

1. A circuit for use in quadrature analysis of a first signal, defined by a modulated waveform, and for producing second and third signals defining in-phase and quadrature-phase values respectively of the first signal, the circuit comprising: a first input terminal for the first signal, a second output terminal for the second signal, a third output terminal for the third signal; sampling means for sampling in respective ones of a plurality of sampling time periods an amplitude of the first signal and for generating a series of sequential output values dependent upon the sampled amplitude, with each output value being associated with a respective one of the sampling time periods, the sampling means being responsive to a periodic timing signal to determine said sampling time periods; switching means for switching communication of the output values for switched time periods alternately between the second and third terminals, the switching means being responsive to a periodic timing signal to determine said switched time periods; timing signal generating means for generating said periodic timing signals for application to the sampling means and the switching means; the timing signal generating means being arranged such that the timing signals determine the respective switched time periods between a respective start time and a respective end time; the timing signal generating means being arranged such that the timing signals actuate the sampling means such that each sampling time period is shorter than the respective switched time period, commences after the start time of the respective switched time period and ceases prior to the end time of the respective switched time period.

2. The circuit according to Claim 1 wherein the sampling means comprises a switch having a first path for effecting connection to the switching means and a second path for effecting disconnection from the switching means.

3. The circuit according to Claim 1 including a low pass filter at the first and second terminals for filtering out high frequency components from the second and third signals.

4. The circuit according to Claim 1 arranged for producing a fourth signal defining an inverted in-phase value and a fifth signal defining an inverted quadrature-phase value and including a fourth output terminal for the fourth signal, and a fifth output terminal for the fifth signal; wherein the switching means includes: a first switch, a second switch, a third switch, each switch having an actuating input, a first contact and two second contacts and arranged so that application of a signal at the actuating input effects switching of communication through the switch from a first route between the first contact and one of the second contacts to a second route between the first contact and the other of the second contacts and an arrangement of conductors defining: a first circuit path from the sampling means, through the first route of the first switch, through the first route of the second switch, to the second output terminal; a second circuit path from sampling means, through the first route of the first switch, through the second route of the second switch, to the fourth output terminal; a third circuit path from the sampling means, through the second route of the first switch, through the first route of the second switch, to the third output terminal; a fourth circuit path from the sampling means, through the second route of the first switch, through the second route of the second switch to the fifth output terminal.

5. The circuit according to Claim 1 arranged for producing a fourth signal defining an inverted in-phase value and a fifth signal defining an inverted quadrature-phase value and including a fourth output terminal for the fourth signal, and a fifth terminal for the fifth output signal; wherein there is provided a first comparator arranged to receive the second and fourth signals and to effect subtraction of the fourth signal from the second signal and wherein there is provided a second comparator arranged to receive the third and fifth signals and to effect subtraction of the fifth signal from the third signal, each of the comparators including a low pass filter for filtering out high frequency components from the signals.

6. The circuit according to Claim 1 wherein the timing signal generating means includes means for receiving a clock pulse signal and means for calculating the timing signals from the clock pulse signal such that the timing signals for the sampling means and the timing signals for the switching means are both related to the clock pulse signal.

7. The circuit according to Claim 6 wherein a timing signal for the switching means is calculated by dividing the clock pulse signal by a first number and the timing signals for the sampling means are calculated by dividing the clock pulse signal by a second number smaller than the first number and by generating a timing offset in the timing signals of the sampling means relative to the timing signals of the switching means so as to lie between the timing signals of the switching means.

8. The circuit according to Claim 6 arranged for producing a fourth signal defining an inverted in-phase value and a fifth signal defining an inverted quadrature-phase value and including a fourth output terminal for the fourth signal and a fifth output terminal for the fifth signal; wherein the switching means includes: a first switch, a second switch, a third switch, each switch having an actuating input, a first contact and two second contacts and arranged so that application of a signal at the actuating input effects switching of communication through the switch from a first route between the first contact and one of the second contacts to a second route between the first contact and the other of the second contacts and an arrangement of conductors defining: a first circuit path from the sampling means, through the first route of the first switch, through the first route of the second switch, to the second terminal; a second circuit path from sampling means, through the first route of the first switch, through the second route of the second switch, to the fourth terminal; a third circuit path from the sampling means, through the second route of the first switch, through the first route of the second switch, to the third terminal; a fourth circuit path from the sampling means, through the second route of the first switch, through the second route of the second switch to the fifth terminal; wherein first and second timing signals for the switching means are calculated by dividing the clock pulse signal by a first number and a second larger number respectively and wherein the timing signals for the sampling means are calculated by dividing the clock pulse signal by a second number smaller than the first number and the second number and by generating a timing offset in the timing signals of the sampling means relative to the timing signals of the switching means so as to lie between the timing signals of the switching means.

9. A circuit for generating a first signal, defined by a modulated waveform, from second and third signals defining in-phase and quadrature-phase values respectively of the first signal, the circuit comprising: a first terminal for the first signal, a second terminal for the second signal, a third terminal for the third signal; waveform assembling means for taking values of the second signal and the third signal and for assembling the values sequentially to form the first signal, each value being taken for a respective one of a plurality of set time periods, the assembling means being responsive to a timing signal to determine said set time periods; conductor means for defining paths each connecting to the assembling means from a respective one of the second terminal and the third terminal; switching means for switching for a switched time period between each of the paths in turn, the switching means being responsive to a timing signal to determine said switched time periods; timing signal generating means for generating said timing signals for application to the assembling means and the switching means; the timing signal generating means being arranged such that the timing signals determine the respective switched time periods between a respective start time and a respective end time; the timing signal generating means being arranged such that the timing signals actuate the assembling means such that each set time period is shorter than the respective switched time period, commences after the start time of the respective switched time period and ceases prior to the end time of the respective switched time period.

10. The circuit according to Claim 8 wherein the assembling means comprises a switch having a first path for effecting connection to the switching means and a second path for effecting disconnection from the switching means.

11. The circuit according to Claim 8 wherein there is provided a band pass filter arranged to pass only the frequency of the modulated waveform.

12. The circuit according to Claim 9 including: means for generating at a fourth terminal from the second signal an inverted second signal having an amplitude dependent upon the second signal; means for generating at a fifth terminal from the third signal an inverted third signal having an amplitude dependent upon the third signal; wherein the conductor means defines four paths each connecting to the assembling means from a respective one of the second, third, fourth and fifth terminals.

13. The circuit according to Claim 12 wherein the switching means includes: a first switch, a second switch, a third switch, each switch having an actuating input, a first contact and two second contacts and arranged so that application of a signal at the actuating input effects switching of communication through the switch from a first route between the first contact and one of the second contacts to a second route between the first contact and the other of the second contacts and an arrangement of conductors defining: a first circuit path from the second terminal, through the first route of the second switch, through the first route of the first switch, to the assembling means; a second circuit path from the third terminal, through the first route of the third switch, through the second route of the first switch, to the assembling means; a third circuit path from the fourth terminal, through the second route of the second switch, through the first route of the first switch, to the assembling means; a fourth circuit path from the fifth terminal, through the second route of the third switch, through the second route of the first switch to the assembling means.

14. The circuit according to Claim 13 wherein there is provided a band pass filter arranged to pass only the frequency of the modulated waveform.

15. The circuit according to Claim 9 wherein a timing signal for the switching means is calculated by dividing the clock pulse signal by a first number and the timing signals for the assembling means are calculated by dividing the clock pulse signal by a second number smaller than the first number and by generating a timing offset in the timing signals of the assembling means relative to the timing signals of the switching means so as to lie between the timing signals of the switching means.

16. The circuit according to Claim 15 wherein the timing signals for the switching means are calculated by dividing the clock pulse signal by a first number and the timing signals for the assembling means are calculated by dividing the clock pulse signal by a second number smaller than the first number and by generating a phase offset in the timing signals of the assembling means so as to lie between the timing signals of the switching means.

17. An apparatus for use in detection of nuclear magnetic resonance signals comprising: a magnet arranged for receiving a sample therein; a transmitter for transmitting a modulated waveform into the sample; a receiver for receiving a sample signal from the sample generated in response to the magnetic field and the oscillating waveform; a modulating circuit for generating the modulated waveform as a first signal from second and third input signals defining in-phase and quadrature-phase values respectively of the first signal, the circuit comprising: a first terminal for the first signal, a second terminal for the second signal, a third terminal for the third signal; waveform assembling means for taking values of the second signal and the third signal and for assembling the values sequentially to form the first signal, each value being taken for a respective one of a plurality of set time periods, the assembling means being responsive to a timing signal to determine said set time periods; conductor means for defining paths each connecting to the assembling means from a respective one of the second terminal and the third terminal; switching means for switching for a switched time period between each of the paths in turn, the switching means being responsive to a timing signal to determine said switched time periods; timing signal generating means for generating said timing signals for application to the assembling means and the switching means; the timing signal generating means being arranged such that the timing signals determine the respective switched time periods between a respective start time and a respective end time; the timing signal generating means being arranged such that the timing signals actuate the assembling means such that each set time period is shorter than the respective switched time period, commences after the start time of the respective switched time period and ceases prior to the end time of the respective switched time period.; and a de-modulating circuit for use in quadrature analysis of the sample signal and for producing second and third output signals defining in-phase and quadrature-phase values respectively of the signal, the circuit as claimed in Claim 1.

18. The apparatus according to Claim 17 wherein the sampling means and the assembling means each comprises a switch having a first path for effecting connection to the respective switching means and a second path for effecting disconnection from the respective switching means.

19. The apparatus according to Claim 14 wherein the de-modulating circuit is arranged for producing a fourth signal defining an inverted in-phase value and a fifth signal defining an inverted quadrature-phase value and including a fourth output terminal for the fourth signal, and a fifth output terminal for the fifth signal; wherein the switching means includes: a first switch, a second switch, a third switch, each switch having an actuating input, a first contact and two second contacts and arranged so that application of a signal at the actuating input effects switching of communication through the switch from a first route between the first contact and one of the second contacts to a second route between the first contact and the other of the second contacts and an arrangement of conductors defining: a first circuit path from the sampling means, through the first route of the first switch, through the first route of the second switch, to the second output terminal; a second circuit path from sampling means, through the first route of the first switch, through the second route of the second switch, to the fourth output terminal; a third circuit path from the sampling means, through the second route of the first switch, through the first route of the second switch, to the third output terminal; a fourth circuit path from the sampling means, through the second route of the first switch, through the second route of the second switch to the fifth output terminal.

20. A filter for an oscillating waveform comprising: an input terminal for receiving a signal in the form of an oscillating waveform for filtering; an output terminal for supplying an output signal in the form of the oscillating waveform after filtering; a de-modulating circuit for quadrature analysis of the signal and for producing second and third output signals defining in-phase and quadrature-phase values respectively of the signal, the circuit as claimed in Claim 1 ; a first filter for receiving the second output signal for filtering out from that signal frequencies which are lower than those of the oscillating waveform and providing a second filter signal; a second filter for receiving the third output signal for filtering out from that signal frequencies which are lower than those of the oscillating waveform and providing a third filter signal; and a modulating circuit for generating the oscillating waveform after filtering from the second and third filter signals, the circuit comprising: a first terminal for output of the oscillating waveform after filtering, a second terminal for the second filter signal, a third terminal for the third filter signal; waveform assembling means for taking values of the second filter signal and the third filter signal and for assembling the values sequentially to form the output signal, each value being taken for a respective one of a plurality of set time periods, the assembling means being responsive to a timing signal to determine said set time periods; conductor means for defining paths each connecting to the assembling means from a respective one of the second terminal and the third terminal; switching means for switching for a switched time period between each of the paths in turn, the switching means being responsive to a timing signal to determine said switched time periods; timing signal generating means for generating said timing signals for application to the assembling means and the switching means; the timing signal generating means being arranged such that the timing signals determine the respective switched time periods between a respective start time and a respective end time; the timing signal generating means being arranged such that the timing signals actuate the assembling means such that each set time period is shorter than the respective switched time period, commences after the start time of the respective switched time period and ceases prior to the end time of the respective switched time period.