WO1998038771A2

WO1998038771A2 - Flow control in switches

Info

Publication number: WO1998038771A2
Application number: PCT/SE1998/000355
Authority: WO
Inventors: Krzysztof Kaminski
Original assignee: Telefonaktiebolaget Lm Ericsson (Publ)
Priority date: 1997-02-27
Filing date: 1998-02-27
Publication date: 1998-09-03
Also published as: WO1998038771A3; AU6642798A; SE9700714L; SE9700714D0

Abstract

The present invention relates to a method of controlling the flow of data packets in a switching unit that includes a number of ingress-selector stages (11, 12, ..., 1n), a number of egress-selector stages (21, 22, ..., 2n), a selector core (3), a number of queue buffers (111, 112, ..., 11n) related to respective ingress-selector stages, a number of output buffers (21B, 22B, ..., 2nB) of which at least one is related to a respective egress-selector stage, and a flow control unit (4). Information-carrying data packets can be stored temporarily in queue buffers (111) related to an ingress-selector stage (11), whereafter these data packets can be transferred to and thereafter stored in one of the output buffers (21B) via the selector core (3). The flow control unit (4) functions to control the data packet flow between the queue buffers (111, 112, ..., 11n) and the output buffers (21B, 22B, ..., 2nB). This control is achieved by allowing the transfer of data packets between the queue buffers (111, 112, ..., 11n) and the output buffers (21B, 22B,..., 2nB) solely in response to the issuance of an order from the flow control unit (4), and totally in accord with said order. The present invention also relates to a switching unit which is adapted to function in accordance with the inventive method.

Description

TITLE OF INVENTION: A CONTROL METHOD FOR A SWITCHING UNIT AND

A SWITCHING UNIT ADAPTED TO FUNCTION IN ACCORDANCE WITH THE METHOD

FIELD OF INVENTION

The present invention relates, on the one hand, to a method of controlling the flow of data packets within a switching unit intended for and adapted to serve a plurality of subscribers that have varying requirements, such as the transmission of speech, video and/or data signals. The present invention also relates to a switching unit adapted to function in accordance with the method.

An inventive switching unit includes, among other things, a plurality of ingress-selector stages allocated to a respective subscriber, a plurality of egress-selector stages allocated to a respective subscriber, and a selector core. The switching unit also includes a plurality of queue buffers related to respective ingress-selector stages, at least one output buffer related to respective egress-selector stages, and a flow control unit.

When setting up a connection from a first subscriber to a second subscriber, information carrying data packets can be stored temporarily in queue buffers related to an ingress- selector stage allocated to the first subscriber, whereafter the data packet can be transferred to and thereafter stored in one of the output buffers, via the selector core, and then finally transferred to the second subscriber from the output W - - 2 -

buffer via an egress-selector stage allocated to the second subscriber.

The flow control unit is adapted to control the flow of the data packet between the queue buffers and the output buffers.

The present invention finds particular application in ATM switching units that operate with standardized data packets or data cells, although it will be understood that the invention is not restricted specifically to use with ATM switching units, and that it can also be applied with other types of switching units that operate with some type of standardized data packet.

BACKGROUND OF THE INVENTION

Different methods of controlling or guiding the flow of data packets through a selector core in an ATM switching unit have long been known to the art.

Since the volume of data packets transferred through a switching unit that serves subscribers having different types of requirements and that transfers data packets of different service classes or different priority levels varies very widely in time, it is difficult to dimension those buffers that are usually related both to ingress-selector stages, egress-selector stages and/or the selector core in a manner which will enable the capacity of the selector core and the transfer capacity between selector core and respective ingress-selector stages and egress-selector stages to be utilized in the most effective manner possible and as optimally as possible, when desiring to avoid very large, and therewith expensive, memory spaces, which, in turn, require large circuit board areas. This problem is well known to the art.

It is also difficult to distribute traffic through a selector core between traffic of different priority levels, in a manner to utilize available capacity in the best possible way.

Examples of different priority levels are real-time related traffic, such as the transmission of sound and pictures in real time, which can be considered to be highly prioritized traffic, and traffic that can wait when the switching unit is heavily loaded, such as the transmission of data files or electronic mail, which can be considered to constitute traffic of lower priority.

It is thus known to divide traffic into different priority levels or service classes, partly in relation to how long the traffic can be allowed to wait, and partly in relation to whether or not it is permitted to scrap certain data packets.

It is also known to evaluate the extent of the coverage of those buffers that are related to the egress-selector stages, and to attempt to guide the flow of data packets through a selector unit on the basis of the information thus obtained while taking the various priorities of the data packet into account .

By the extent of buffer coverage is meant how much of a buffer is covered or occupied, and therewith also how much of a buffer is available or free. Examples of different types of devices and methods associated with this technology are described and illustrated in the following publications.

GB-A2 288 095:

This publication describes an ATM system that includes ingress-stage related buffers and egress-stage related buffers, and means for controlling the flow of data cells between these buffers. The flow control is based on a system disclosed in the following publication. - A -

EP-A2-0 624 015:

This publication describes an ATM switching unit where the buffer memory, related to input ingress stages orders a given bandwidth, or transfer capacity, for traffic to different egress stages before data transmission takes place, in order to establish whether or not sufficient capacity is available to receive data in the egress stages.

The system includes a queue arrangement for different bandwidth queries, where queries are placed in a queue, or in line, during periods when capacity is insufficient. When sufficient capacity is available, available capacity is released in accordance with a predetermined order in relation to the queue arrangement .

EP-A2-0 681 385:

This publication describes an ATM switching unit which is adapted to divide data cells into different priority levels or service classes. Each data cell is allocated destination-related information, a certain delay-class and a certain loss- class. A number of logic queues are related to the ingress side of the switching unit, and the incoming data cells are placed in different queues in accordance with destination and in accordance with delay-class and loss-class respectively.

The extent of the coverage in different buffers decides whether data cells of different delay classes can be transferred from the ingress-side to the egress-side or not.

In the case of very high loads, it is permissible to lose certain data cells in accordance with the loss-class allocated thereto. EP-A2-0 526 104 :

This publication describes an ATM switching unit that is intended to handle data cells having a number of different priority levels.

Each egress stage is allocated a number of queues, one for each priority level. Each queue is allowed to consume the whole of its buffer memory. In the event of further incoming data cells for which no space is found in the buffer memories, the length of the queues is summated for each egress stage individually, and a comparison is made to determine which egress stage has the largest number of buffered data cells.

It is permitted to lose a buffered data cell from the lowest prioritized non-empty queue within the egress stage. Incoming data cells are then stored in the resultant available storage space.

US-A-5,062,106:

This publication describes an ATM switching unit in which data cells are stored in different buffers in accordance with their destination.

A number of different queue buffers are used to handle a time delay control. Overload control is made possible by virtue of data-cell loss control when an egress stage is overloaded, this control being based on the number of data cells waiting in the queue buffers.

SUMMARY OF THE INVENTION

TECHNICAL PROBLEMS

With respect to a data packet transfer switching unit intended to serve a number of subscribers and including a number of ingress-selector stages allocated to respective subscribers, a number of egress-selector stages allocated to respective subscribers, a selector core, a number of queue buffers related to respective ingress-selector stages, a number of output buffers, at least one related to respective egress-selector stages, and a flow control unit, whereby information carrying data packets from a first subscriber to a second subscriber can be stored temporarily in queue buffers related to an ingress-selector stage allocated to said first subscriber, whereafter the data packets can be transferred to and thereafter stored in one of the output buffers via the selector core, and finally transferred to the other subscriber from the output buffer via an egress-selector stage allocated to the second subscriber, wherein the flow control unit is adapted to control the flow of data packets between the queue buffers and the output buffers, it will be seen that a problem resides in realizing the possibilities that can be afforded by utilizing the capacity available in the selector core during those time intervals during which high priority traffic, such as real time traffic, does not take-up the full capacity of the selector core, and to establish the extent to which this capacity is utilized at each time interval.

It will also be seen that a technical problem is one of rea- lizing how the transfer capacity between ingress-selector stages and the selector core can be utilized optimally.

It will also be seen that a technical problem is one of finding a solution to the problem of enabling the capacity of the selector core to be utilized to a very large extent, without needing to utilize techniques that permit certain data packets to be lost.

Another technical problem resides in realizing the possibi- lities of providing a flow control, via a method and/or a control unit, for controlling the total flow of data packets through the selector core at each time interval, and for also controlling the flow of data packets permitted to pass through the selector core within the capacity afforded additionally to the high priority traffic, such as real-time related traffic.

It will also be seen that a technical problem resides in realizing how the limited transfer capacity available between respective ingress-selector stages and the selector core can be utilized optimally, or at least almost optimally, during each individual time interval .

Another technical problem is one of realizing the possibilities that are afforded by a method based on solely permitting a flow of data packets between queue buffers and output buffers in response to, and always in response to, an order delivered from a flow control unit.

Another technical problem is one of realizing the possibilities that are afforded when the flow control unit includes an order issuing unit and when respective ingress- selector stages include an order receiving unit, wherewith the flow of data packets between the queue buffers and the output buffers can be controlled through the medium of an order from the order issuing unit to the order receiving units.

It will also be understood that a technical problem resides in realizing the advantages that are afforded when respective ingress-selector stages include an information-collecting unit which is adapted to deliver part of the necessary information to the order issuing unit, and when the order issuing unit is able to procure certain information on its own accord.

A further technical problem is one of realizing which information is required to compile an order when available capacity can be utilized optimally, or at least almost optimally.

It will also be seen that a technical problem is one of realizing how a flow control unit shall be designed in order to be able to procure and compile necessary information.

Yet another technical problem is one of realizing how the various requirements of each queue buffer for transferring data packets within following time intervals shall be placed in relation to each other and presented in a simple and effective manner, and particularly how this can be presented when said queue buffers are allocated different priority levels and divided into subordinate priority-related queue buffers.

It will also be seen that a technical problem is one of realizing how this information can be presented in matrix form in a total status matrix for all queue buffers that are included, and the advantages thus afforded.

When the queue buffers include subordinated priority-related queue buffers, where first subordinated queue buffers are related to a first priority level that is a highest priority level, such as real-time related traffic, and a second subordinated queue buffer is related to a second priority level that is a lower priority level, such as traffic of lower priority than real-time related traffic, and so on through a number of available priority levels, it will be seen that a further technical problem is one of realizing how the various requirements of each subordinated queue buffer for transferring data packets within subsequent time intervals and the priority levels of respective data packets can be represented within this presentation.

Another technical problem is one of realizing how the need to send a specific number of data packets wthin following time intervals and also the priority status of said data packets can be represented within this presentation.

Another technical problem is one of realizing how this information can be presented in matrix form in a three-dimensional matrix, a total status matrix for all included subordinate queue buffers that represent different priority levels, and the advantages afforded hereby.

Another technical problem is one of realizing how such a three-dimensional matrix can be compressed to solely two dimensions while retaining the information necessary for compiling an order that provides optimized control of the data packet flow.

A further technical problem is one of realizing how an order that indicates to each buffer the number of data packets that may be transferred during subsequent time intervals shall be designed in an effective and simple manner.

Another technical problem is one of realizing how the order to send a specific number of data packets within subsequent time intervals can be represented within this presentation.

It will also be seen that a technical problem resides in realizing how this information can be presented in matrix form, in an order matrix which is common to all queue buffers that are included, and the advantages afforded thereby.

It will also be seen that a technical problem is one of realizing the possibility of using the same type of two-dimensional order matrix irrespective of whether respective queue buffers include a plurality of subordinate priority-related queue buffers or not.

When the queue buffers are placed physically in the ingress- selector stages to which they are related, it will be seen that a technical problem is one of realizing how the number of data packets which, in accordance with an order, are able to be transferred from respective ingress-selector stages during a time interval while being controlled so as not to exceed the maximum possible number of bits that can be transferred from an ingress-selector stage to the selector core during a chosen time interval .

Another technical problem is one of realizing how the number of data packets that are able to be transferred to an output buffer from input buffers belonging to different ingress- selector stages in accordance with an order can be controlled so as not to exceed the total number of data packets that can be accommodated in an output buffer.

In those cases when respective output buffers are placed physically in the egress-selector stage to which it is related, it will be seen that a technical problem is one of realizing how the number of data packets that are able to be transferred to respective egress-selector stages during a time interval in accordance with an order can be controlled so as not to exceed the maximum possible number of bits that can be transferred from the selector core to an egress-selector stage during a time interval .

Another technical problem is one of realizing how an order matrix shall be constructed for maximum utilization of the transfer capacity between respective ingress-selector stages and the selector core while taking into consideration that the number of queue buffers that include buffered data packets related to an ingress-selector stage can be much smaller than the number of queue buffers that include buffered data packets related to another ingress-selector stage.

A further technical problem is one of realizing how this consideration can be taken into account when forming an order matrix in the case when respective queue buffers include a plurality of subordinated priority-related queue buffers.

Another technical problem is one of realizing how the flow of information in a network that is intended to be coupled to a number of nodes, where a number of nodes are connected to each other either directly or indirectly, whereby information- carrying data packets from one or more first nodes can be transferred to a second node, where a flow control unit is adapted to control the flow of data packets between the nodes, can be controlled so as to optimize the transfer capacity between the nodes, particularly when traffic is of a burst character and/or when traffic of different service classes or priority levels occurs between the nodes.

SOLUTION

With the intention of solving one or more of the aforesaid technical problems, the present invention takes as its starting point a method of controlling the flow of data packets within a switching unit of the kind defined in the first paragraph of this document.

With the intention of enabling the capacity of the selector core and the transfer capacity between ingress-selector stages and egress-selector stages and the selector core to be utilized in the best possible manner, the invention proposes in particular that the transfer of data packets from queue buffers to output buffers is controlled by the flow control unit by virtue of permitting such transfer subsequent to receiving an order from the flow control unit, and to effect said transfer totally in accordance with said order.

In accordance with proposed embodiments that lie within the scope of the present invention, it is proposed that one such order is compiled on the basis of information that includes the instantaneous need to send data packets from the queue buffers to the output buffers, and on the basis of information relating to the instantaneous extent of the coverage of said output buffers.

The information will also include the number of data packets that are stored in the queue buffers at that moment in time, and to which output buffer respective buffered data packets are intended to be transferred.

Respective queue buffers are thus given an order as to how many data packets shall be transferred during subsequent time intervals, this order being based on, and in consideration of, the extent of the coverage of the other output buffers and the need to transfer data packets from respective queue buffers, therewith enabling the flow control to be effected without application of the technique in which the application of lost data packets is permitted.

According to one embodiment of the invention, the number of queue buffers related to respective ingress-selector stages corresponds to the number of egress-selector stages.

With the intention of preparing a simple and effective manner of presenting this information, and of providing one such structure in the switching unit, it is proposed in accordance with the present invention that the information concerning the queue buffers related to respective ingress-selector stages is compiled in vector form in a so-called status vector, and that a status matrix is structured from the status vectors from all ingress-selector stages.

The number of rows in a status matrix will thus correspond to the number of output buffers, and the number of columns will correspond to the total number of ingress-selector stages, where respective columns are comprised of a status vector which is adapted to represent each associated ingress-selector stage, and respective rows are adapted to each represent its output buffer.

Furthermore, respective positions in a column of a status matrix are adapted to represent the number of data packets buffered in a queue buffer related to the ingress-selector stage belonging to said column and intended for transfer to the output buffer that is represented by the row belonging to said position during a next-following time interval.

Each position within a status matrix is allocated a specific number of data bits that represent at least the maximum possible number of data packets that can be transferred within a time interval.

When more data packets are buffered in a queue buffer, the data bits in a position allotted to the queue buffer represent the maximum possible number of data packets that can be transferred.

Different time intervals can be used. A so-called three packet interval implies a time interval which is corresponded by the time taken to transfer three data packets from an ingress- selector stage to the selector core. In this case, the data bits in one position are two in number, since two data bits can represent up to three data packets. Two data bits may also represent a shorter time interval, for instance a time interval that accommodates two data packets, a so-called two packet interval .

The selectable duration of the time interval is thus quantized to be n-one packet interval, where n is a positive integer and the packet interval is the time taken to send one data packet. It is also assumed that all data packets forwarded through the switching unit have a size or bit length that does not exceed a chosen largest permitted size or bit length.

When the number of data bits is one, each position may represent one data packet, therewith enabling a so-called single packet interval to be used.

The choice of time interval will depend, among other things, on the length of time required to collect necessary information transfer the information from respective ingress- selector stages to the flow control unit, to combine the information and compile an order, to send the order from the flow control unit, and to receive the order in respective queue buffers. The time required in this respect sets the limit for a smallest possible time interval.

Shorter time intervals place a greater demand on the requisite bandwidth in the transmission of the information to be sent to and from the flow control unit. Longer time intervals give a lower bandwidth requirement, but also result in a system that has longer delays and slower feedbacks.

With the intention of providing a simple and effective method of presenting requisite information when respective queue buf- fers are divided into a number of subordinated priority- related queue buffers, where the total number of subordinate queue buffers is corresponded by the number of different priority levels that can be handled by the switching unit, the present invention proposes the compilation of a priority- related status vector for each priority level and thereto related subordinated queue buffers related to respective ingress-selector stages.

By way of example of different priority levels, it can be men- tioned that a first priority level could be corresponded by data packets of the highest priority, such as data packets intended to forward data in real time, while a second priority level may correspond to data packets whose priority is lower than the priority level of the first priority level, such as data packets with which a given waiting time is permitted.

There is nothing to prevent data packets having different priority levels or service classes being handled on the same priority level internally within the switching unit, and being handled separately externally of said unit. Thus, by different priority levels is meant data packets that are handled in different ways internally within the switching unit, which in no way prevent several different priority levels or service classes being applied externally of the switching unit.

It is also proposed that a status matrix related to an ingress-selector stage is composed of the priority-related status vectors for respective ingress-selector stages, where respective positions in a column belonging to a status matrix related to an ingress-selector stage are adapted to represent the number of data packets that are buffered within a subordinated queue buffer by the priority level to which the priority-related status vector is related, these data packets being intended for transfer to the output buffer to which the subordinated queue buffer is related, during a next-following time interval.

It is proposed in this case that the status matrices related to the ingress-selector stage are used to form a three- dimensional status matrix.

With the intention of enabling a necessary part of the information available in the aforesaid three-dimensional status matrix to be presented readily, the present invention proposes that a two-dimensional matrix is formed in accordance with the case where the queue buffers do not include subordinate prio- rity-related queue buffers, but where respective positions in a column belonging to one such status matrix are adapted to represent the number of data packets found buffered within a subordinate priority-related queue buffer related to the ingress-selected stage belonging to said column, intended for transfer to the output buffer that is represented by rows belonging to said positions during a next-following time interval, and to which priority level these data packets belong.

Thus, each position within the status matrix shall be adapted to include a specific number of data bits, where the bit number is adapted to represent at least the maximum possible number of data packets that can be transferred within a time interval, and the number of available priority levels represented by subordinate priority-related queue buffers.

Despite the additional data space required for priority- related information in each position of the status matrix, it is nevertheless capacity-saving in relation to a three- dimensional status matrix, where the third dimension represents the priority level concerned.

In this type of priority-indicating, two-dimensional matrix, the present invention proposes that information located in respective positions shall be related to the subordinate priority-related queue buffer that represents the highest priority level of the subordinate priority-related queue buffers that contain at least one buffered data packet.

With the intention of providing a simple, but effective, solution to the compilation of the order or command to be delive- red, the present invention proposes that this order is compiled in matrix form in a so-called order matrix, where the number of rows corresponds to the total number of output buffers, and where the number of columns corresponds to the total number of ingress-selector stages.

In such an order matrix, respective columns may each be intended for a respective ingress-selector stage, and respective rows may each be intended for a respective second output buffer.

According to the present invention, respective positions in an order matrix column may be adapted to represent the number of data packets to be transferred from a queue buffer, related to the ingress-selector stage belonging to said column, to the output buffer that is represented by the row belonging to said position during a next-following time interval. As in the case of the status matrix, each position in the order matrix includes a specific number of data bits, this number being adapted to be able to represent at least the maximum possible number of data packets that can be transferred within a time interval.

With the intention of enabling the same simple order matrix to be used also when wishing to handle several different priority levels, there is proposed in accordance with the invention a method in which this need not be taken into consideration when compiling the order matrix, since solely the highest priority within respective queue buffers is considered when compiling said order matrix, therewith enabling the order to be executed solely with respect to data packets that have the highest priority in respective queue buffers.

With the object of enabling the maximum possible transfer capacity to be achieved between respective ingress-selector stages and the selector core, there is proposed in accordance with the present invention a method wherein when respective queue buffers are placed physically in the ingress-selector stages to which they are related, the order matrix is compiled so that the sum of the number of data bits in all positions in respective columns belonging to said order matrix will be equal to or less than the maximum possible number of data packets that can be transferred from respective ingress- selector stages to said selector core during a time interval .

With the object of taking into consideration the maximum possible number of data packets that can be stored in an output buffer, it is proposed in accordance with one method of the invention that the order matrix is compiled so that the sum of the number of data bits in all positions in respective rows belonging to the order matrix is equal to, or less than the maximum possible number of data packets that can be stored in an output buffer. In order to enable the maximum possible transfer capacity between the selector core and respective egress-selector stages to be taken into consideration, it is proposed in accordance with the present invention that when respective output buffers are placed physically in the egress-selector stage to which said buffer is related, the order matrix is compiled so that the sum of the number of data bits in all positions in respective rows belonging to the order matrix are equal to, or less than, the maximum possible number of data packets that can be transferred from the selector core to respective egress-selector stages during a time interval.

In order to enable the manner in which ingress-selector stages that are loaded to mutually different extents, i.e. have mutu- ally different numbers of queue buffers with buffered data packets, shall be serviced in a manner which enables the optimal use of the transfer capacity between ingress-selector stages and the selector core to be taken into consideration, there is proposed in accordance with the invention a method wherein the order matrix is adapted to give priority to the transfer of data packets from an ingress-selector stage that has data packets buffered in a few queue buffers over the transfer of data packets from an ingress-selector stage that has data packets buffered in a plurality of queue buffers.

In the case when respective queue buffers include a plurality of subordinated priority-related queue buffers, there is proposed in accordance with the invention a method in which the order matrix is adapted to give priority to the transfer of data packets from a subordinated queue buffer related to a high priority level, over the transfer of data packets from a subordinated queue buffer related to a lower priority level, and wherein when handling subordinated queue buffers of the same priority level, the order matrix is adapted to give priority to the transfer of data packets from an ingress- selector stage that has data packets buffered in a few subordinated priority-related queue buffers over the transfer of data packets from an ingress-selector stage that has data packets buffered in a plurality of subordinated priority- related queue buffers.

The aforedescribed method illustrates the principle of how status matrices and order matrices are compiled and sent to and from the flow controlling unit, and is described as though these matrices were compiled in their entirety prior to being sent. It will be understood, however, that in practice the status matrices may very well be sent to the flow controlling unit as the matrix is being compiled, and that the flow controlling unit processes information from the partially compiled status matrix as soon as it arrives, and thus begins to compile the order matrix while still receiving the status matrix, and that the order matrix is sent to receiving ingress-selector stages as the order matrix is being compiled. Thus, parts of the order matrix may begin to arrive at the ingress-selector stages whilst the status matrix is still being compiled, and sent from the ingress-selector stages to the flow controlling unit.

The invention also relates to a switch unit adapted to function in accordance with the aforesaid method and based on the switch unit defined in the introduction.

In accordance with the invention, the switching unit is adapted so that the requisite flow control unit will include an order issuing unit, that respective ingress-selector stages will include an order receiving unit, and that the flow of data packets between queue buffers and output buffers can be controlled through the medium of an order sent by the order issuing unit to respective order receiving units, where a data packet transfer is permitted solely upon receipt of the order from the order issuing unit and executed totally in accordance with said order.

By way of further embodiments of an inventive switching unit that lie within the scope of the invention, it is proposed that respective ingress-selector stages will include an information-collecting unit which functions to collect information relating to the instantaneous or current status of those queue buffers belonging to respective ingress-selector stages, that the flow control unit will include a coverage evaluating unit adapted to establish the current extent of the coverage of respective output buffers, and that the flow control unit will also include an information receiving unit that functions to receive the information collected by respective information collecting units.

It is also proposed that the order issuing unit will function to compile and send the order, on the basis of the information collected and the extent of said coverage, and that respective order receiving units are operable to receive transmitted orders during a time interval and to execute said order during a following time interval.

Respective information collecting units are adapted to compile information with this content and in a manner described in the aforesaid method.

Thus, the information receiving unit is also adapted to compile a status matrix on the basis of the information collected by respective information collecting unit in accordance with said method. This status matrix may be a two- dimensional matrix or a three-dimensional matrix, all in accordance with the various method embodiments described.

It is also proposed that the number of queue buffers related to respective ingress-selector stages will correspond to the number of egress-selector stages, thereby enabling the switching unit to function in accordance with said method.

With the intention of enabling handling of data packets that have been allocated mutually different priority levels, it is proposed in accordance with the present invention that respective queue buffers will be adapted to include a number of subordinated priority-related queue buffers, that respective subordinated queue buffers will be adapted to forward data packets that are allocated a specific priority level, that a first subordinated queue buffer will be adapted to forward data packets of a first priority level, that a second subordinated queue buffer will be adapted to forward data packets of a second priority level, and so on, wherewith the total number of subordinated queue buffers corresponds to the number of different priority levels that can be handled by the switching unit.

According to the invention, the order issuing unit functions to compile the order in matrix form, in a so-called order matrix in accordance with the aforesaid method.

Switching units may be constructed in different ways, and when respective queue buffers are placed physically in the ingress- selector stages to which the queue buffer is related, the order issuing unit is adapted to compile the order matrix so that the sum of the number of data bits in all positions in respective columns belonging to said order matrix is equal to, or smaller than, the maximum possible number of data packets that can be transferred from respective ingress-selector stages to the selector core during a time interval .

The order issuing unit is also adapted to compile the order matrix so that the sum of the number of data bits in all positions in respective rows belonging to said order matrix is equal to or smaller than the maximum possible number of data packets that can be stored in an output buffer.

Similarly, when respective output buffers are placed physically in an egress-selector stage to which said output buffer is related, the order issuing unit is adapted to compile the order matrix so that the sum of the number of data bits in all positions in respective rows belonging to said order matrix is equal to or smaller than the maximum possible number of data packets that can be transferred from the selector core to respective egress-selector stages during a time interval .

Thus, the order issuing unit is also adapted to give priority to the transfer of data packets from an ingress-selector stage in which data packets are buffered in a few queue buffers, and primarily the transfer of data packets from an ingress- selector stage that has data packets buffered in a plurality of queue buffers, when compiling order matrices.

When respective queue buffers include a plurality of subordi- nated priority-related queue buffers, the order issuing unit functions to give priority to the transfer of data packets from a subordinated queue buffer related to a higher priority level over the transfer of data packets from a subordinated queue buffer related to a lower priority level, when compiling the order matrices.

In respect of the management, or handling, of subordinated queue buffers of mutually the same priority level, the order issuing unit is adapted to give priority to the transfer of data packets from an ingress-selector stage that has data packets buffered in a few subordinated priority-related queue buffers over the transfer of data packets from an ingress selector stage that has data packets buffered in a plurality of subordinated priority-related queue buffers.

With the intention of enabling the flow of information to be controlled in a network which is intended to interconnect a plurality of nodes, where a plurality of nodes are connected to each other either directly or indirectly, therewith enabling information-carrying data packets to be transferred from one or several first nodes to a second node, wherein a flow control unit is adapted to control the flow of data packets between said nodes, it is proposed in accordance with the present invention that the transfer of data packets from the first nodes to the second node can be controlled by the flow control unit by permitting the transfer of data packets to take place solely in response to an order from the flow control unit and totally in accordance with said order.

In accordance with the present invention, it is particularly proposed that such an order can be compiled on the basis of information that discloses the current need to transmit data packets from the first nodes to the second node.

ADVANTAGES

Those advantages that are primarily obtained with a method and a switching unit according to the present invention reside in the possibility of effectively controlling the flow of data packets in a relatively simple and cost-effective manner without needing to utilize methods that accept lost data packets, and enabling the coverage capacity afforded by the selector unit alongside high priority traffic, such as realtime traffic, to be used in a higher degree.

This achieved by virtue of an inventive method or inventive switching unit providing the possibility of utilizing the capacity of the ingress-selector stages to transfer data packets to the selector core optimally, and to keep the output buffers filled to a maximum.

The inventive method enables the flow control unit to know precisely what number of data packets are on route to the selector core from respective ingress-selector stages and from said selector core to respective egress-selector stages. The size of the output buffers can thus be minimized. For instance, a one-packet interval will enable the use of output buffers that have a storage capacity of one data package, which is difficult to achieve, if not impossible to achieve, with known methods.

The main characteristic features of an inventive method are set forth in the characterizing clause of Claim 1, whereas the main characteristic features of an inventive switching unit are set forth in the characterizing clause of the following Claim 26.

BRIEF DESCRIPTION OF THE DRAWINGS

An adapting unit which functions in accordance with the aforesaid method and has properties associated with the present invention will now be described with reference to an exemplifying embodiment thereof and also with reference to the accompanying drawings, in which

Figure 1 is a highly schematic and very simplified illustration of a known switching unit that has two ingress-selector and egress-selector stages, and, e.g., subscribers connected thereto;

Figure 2 is a more detailed, schematic illustration of a switching unit supplemented with the inventive devices;

Figure 3 illustrates a first embodiment of a status matrix, a two-dimensional status matrix;

Figure 4 shows an example of a status matrix related to an ingress-selector stage and including three different priority levels;

Figure 5 illustrates a second embodiment of a status matrix, a three-dimensional status matrix;

Figure 6 illustrates an example of a queue buffer that includes three mutually different, subordinated priority-related queue buffers;

Figure 7 illustrates one example of an order matrix;

Figure 8 is a schematic illustration of a switching unit, where a plurality of ingress-selector and egress-selector stages are not included in a flow control according to the invention; and

Figure 9 illustrates an example of a network that has a number of mutually coacting nodes.

DETAILED DESCRIPTION OF EMBODIMENTS AT PRESENT PREFERRED

The present invention relates both to a method of controlling the flow of data packets through a switching unit, and to a switching unit that functions in accordance with said method.

In order not to load the descriptive part of this document unnecessarily, a description of an inventive switching unit will be given in the following even where the method is described per se. Certain explanatory passages relating to the method will be given as required.

Figure 1 is a schematic illustration of the fundamental units of a switching unit A that is intended to serve a plurality of subscribers B, C and that includes a plurality of subscriber- allocated ingress-selector stages 11, 12, a plurality of subscriber-allocated egress-selector stages 21, 22, and a selector core 3.

In order to simplify the description, reference is made generally to a subscriber which is exemplified in Figure 1 in the form of a telephone handset, although it will be understood that reference to a subscriber implies equipment connected to the switching unit, which, in practice, may include everything from an individual subscriber, such as a data server or a company internal telephone exchange, to a plurality of individual subscribers (telephone handsets) that share a respective ingress-selector stage and an egress- selector stage. More generally, it can be said that all equipment that utilizes data packets of a specific format can be connected and form a subscriber. Traffic from these subscribers is concentrated to the traffic that enters or leaves a switching unit, or a combination thereof.

Figure 2 illustrates an inventive switching unit that includes a plurality of queue buffers 111, 112, ..., lln related to respective ingress-selector stages 11, 12, ..., In, and a plurality of output buffers 21B, 22B, ... , 2nB of which at least one is related to respective egress-selector stages 21, 22, ... , 2n.

In the illustrated embodiment, different queue buffers 111, 112, ..., lln are placed physically in connection with an ingress-selector stage 11, and the various output buffers 21B, 22B, ... , 2nB, are placed physically in connection with the selector core 3.

This is the most advantageous positioning of the various buffers in respect of certain applications, although it will be understood that the present invention can also be applied in a switching unit where the different queue buffers are placed physically in connection with the selector core and/or where the different output buffers are placed physically in connection with the egress-selector stages.

Although not mentioned in this description, the switching unit may also include other buffers that do not influence the application of the present invention. The number (n) of queue buffers related to respective ingress- selector stages 11, 12, ..., In is corresponded by the number of egress-selector stages 21, 22, ..., 2n.

The switching unit also includes a flow control unit 4.

When a connection is established between the first and the second subscribers, information carrying data packets from a first subscriber B to a second subscriber C can be stored temporarily in queue buffers 111 related to an ingress- selector stage 11 allocated to the first subscriber B, whereafter these data packets can be transferred to and thereafter stored in one of the output buffers 21B through the selector core 3 and then transferred to the second subscriber C from the output buffer 21B, via an egress-selector stage 21 allocated to the second subscriber. The egress-selector stages also include buffers that are required for controlling the flow of data packets from respective egress-selector stages to respective connected subscribers . The present invention is not concerned with this transfer of data packets, and will not therefore be shown or described.

The utilization of the capacity of a switching unit of this kind is limited in several respects.

One such limitation is found in the transfer capacity in the connection 311, 312, ..., 31n between respective ingress- selector stages 11, 12, ..., In and the selector core 3. For instance, in the case of a standard ATM switching unit, this transfer capacity may be in the order of 155 Mbit/s. In this case, the flow of input data to an ingress-selector stage will never exceed 155 Mbit/s because a part of the incoming data packet must sometimes be buffered, for instance due to the extent of the coverage in the output buffers 21B, 22B, ... , 2nB, which per se constitute a limitation. There may be a later occasion where the need to transfer data packets from the various queue buffers can exceed the available capacity, meaning that further data packets must be buffered.

The transfer capacity from the selector core 3 to respective egress-selector stages 21, 22, ..., 2n is limited in the same way.

Thus, it can be necessary to buffer data packets in a queue buffer 111 related to a first ingress-selector stage 11 and intended for transfer to a first egress-selector stage 21 via a first output buffer 21B, this necessity arising because data packets from a first queue buffer 121 related to a second ingress-selector stage 12 and intended for transfer to the same first egress-selector stage 21 via the same first output buffer 21B and because the first output buffer 21B is full or because the transfer capacity in the conductor 311 has been utilized to the full in the transfer of data packets from output buffers 112, ... , lln.

The purpose of the flow control unit 4 is to ensure that the available capacity through the selector core 3 and over the connections 311, 312, ..., 31n; 321, 322, ..., 32n between respective ingress-selector and egress-selector stages and the selector core is utilized as optimally as possible.

The flow control unit 4 is thus adapted to control the flow of data packets between the queue buffers and the output buffers.

The flow control unit 4 includes an order issuing unit 41, and respective ingress-selector stages 11, 12, ..., 2n includes an order receiving unit 113, 123, ..., In3.

The flow control unit 4 functions by virtue of controlling the flow of data packets between the queue buffers 111, 112, ..., lln and the output buffers 21B, 22B, ... , 2nB through the medium of an order issued to the order receiving units 112, 123, ..., In3 from the order issuing unit 41. Respective ingress-selector stages 11, 12, ..., In include an information collecting unit 114, 124, ..., In4 which functions to collect information relating to the current status of the queue buffers 111, 112, ..., lln belonging to respective ingress-selector stages 11.

The flow control unit 4 also includes a unit 42 which evaluates the extent of coverage and which functions to establish the current extent of coverage of respective output buffers 21B, 22B, ..., 2nB.

This evaluation of the status of the buffers, or their extent of coverage, is achieved in a known manner and will not therefore be described in detail in this document.

The flow control unit 4 also includes an information receiving unit 43 which functions to receive the information collected by respective information collecting units 114, 124, ln4.

The order issuing unit 41 functions to compile and send an order on the basis of the collected information relating to the status of the queue buffers and the status of the output buffers, whereafter respective order receiving units 113, 123, ... , ln3 function to receive and carry out the order .

The information collected by respective information collecting units 114, 124, ..., In4 includes the number of data packets that are currently stored in respective queue buffers 111, 112, ..., lln.

One effective way of compiling the information is to design respective information collecting units 114, 124, ..., In4 to compile said information in vector form, in a so-called queue buffer status vector.

The information receiving unit 42 then compiles a status matrix from the status vectors. Figure 3 shows an example of how a status matrix "sm" can be compiled. The number of rows (eight rows in Figure 3 ) in a status matrix "sm" corresponds to the number of output buffers 21B, 22B, ... , 2nB related to respective egress-selector stages 21, 22, ..., 2n, while the number of columns ( eight columns in Figure 3 ) corresponds to the total number of ingress-selector stages 11, 12, ..., In.

Thus, respective columns kl, k2, ..., k8 are comprised of a status vector and are each intended to represent a respective ingress-selector stage 11, 12, ..., In, whereas respective rows rl, r2, ..., r8 are each intended to represent a respective output buffer 21B, 22B, ...2nB.

One position kl, rl in a column kl belonging to the status matrix "sm" is intended to represent the number of data packets buffered in a queue buffer 111 related to the column kl belonging to the ingress-selector stage 11 intended for the transfer of data packets to the output buffers 21B that is represented by the position belonging to row rl, during a coming time interval.

For instance, the information in position sm75 (row 7, column 5 ) corresponds to the number of data packets that can be transferred from a queue buffer related to ingress-selector stage number 5 to the output buffer related to egress-selector stage number 7 during coming time intervals.

Each position in the status matrix "sm" includes a specific number of data bits, this number being able to represent at least the maximum possible number of data packets that can be transferred within a time interval.

For instance, if the time interval used corresponds to the time that it takes to transfer three data packets, a so-called three-packet interval, the number of data bits will thus be at least two. Two data bits can also be used in a so-called two- packet interval. When a single-packet interval is used, the data bits in respective positions will be at least one in number .

The aforedescribed embodiment is based on the assumption that all data packets are allocated one and the same priority level. However, it is not unusual to divide traffic into a number of different priority levels.

In such a case, respective queue buffers will include two or more subordinated priority-related queue buffers, where respective subordinated priority-related queue buffers are adapted to forward data packets that have a specific priority level or status.

Figure 4 illustrates an example in which respective information collecting units 114, 124, ..., In4 are adapted to compile priority-related status vectors pi, p2, p3 , one for each subordinated queue buffer. This example concerns traffic having three different priority levels that can be managed by the subordinated priority-related queue buffers.

Respective information collecting units 114 are also adapted to compile from the priority-related status vectors pi, p2, p3 a status matrix "ism" related to ingress-selector stages, where each column pi, p2, p3 represents one priority level and row rl, r2, ..., r8 represents a queue buffer 111, 112, ..., lln with associated priority levels.

Respective positions in a column of the status matrix "ism" related to said ingress-selector stages are intended to represent the current number of data packets buffered in a queue buffer 111, 112, ..., lln by the priority level to which the priority-related status vector pi, p2, p3 is related, belonging to the queue buffer 111, 112, ..., lln related to the row rl, r2, ..., r8 and intended for transferring data packets to the output buffer to which this queue buffer is related, during a coming time interval. In this case, the information receiving unit 43 functions to compile a three-dimensional status matrix "3dsm" from the status matrices "ism" related to the ingress-selector stages; see Figure 5.

Respective positions in the three-dimensional status matrix "3dsm" are also in this case allocated a specific number of data bits, this number being able to represent at least the maximum possible number of data packets that dan be transferred within one time interval.

For instance, the information in position 3dsm212 (column 2, line 1 and priority level 2 ) corresponds to the current number of data packets buffered in a queue buffer subordinated to queue buffer 121 related to ingress-selector stage 12 number 2 having priority level 2 and intended for transfer to egress- selector stage 21 via output buffer 21B.

Figure 3 can also be considered to illustrate a further possible embodiment that can be used when respective queue buffers include a plurality of different subordinated priority-related buffers.

In this respect, respective positions in a column kl , k2, ..., k8 belonging to a typical two-dimensional status matrix "sm" are adapted to represent the number of data packets buffered in a subordinate queue buffer of a given priority level, related to the ingress-selector stages 11, 12, ..., In belonging to said column, these data packets being intended for transfer to the output buffer 21B, 22B, ..., 2nB represented by the row rl, r2, ..., r8 belonging to this position during a coming time interval, and to which priority levels pi, p2, p3 the data packets belong.

In this case, respective status matrix positions include a specific number of data bits which are able to represent at least the maximum possible number of data packets that can be transferred within a time interval, and also the number of priority levels available to the subordinated priority-related queue buffers.

Thus, when a three-packet interval is used and three different priority levels are represented by respective queue buffers, respective positions will include four data bits, i.e. two for representing up to three transferrable data packets and two for denoting one of the three possible priority levels. It will be seen from this that it is possible to denote four different priority levels.

Since it is only possible to deliver information relating to the number of buffered data packets for a subordinated priority-related queue buffer per queue buffer in this particular case, the information in respective positions will be related to the subordinated priority-related queue buffer that represents the highest priority level of the subordinated priority-related queue buffers that contain at least one buffered data packet in one queue buffer.

Figure 6 shows an example of a queue buffer 111 that includes three different subordinated priority-related queue buffers lllpl, lllp2, lllp3. The buffered data packets are marked with a cross in Figure 6, from which it will be seen that no data packets are currently buffered in priority level one, two data packets are currently buffered in priority level two, and four data packets are currently buffered in priority level three.

Figure 6 shows a principle construction of a queue buffer with subordinated priority-related queue buffers by way of explanation. These queue buffers can be formed in different ways. For instance, the various subordinated priority-related queue buffers can be given different sizes, since the need to buffer data cells will probably vary with different priority levels.

The information in the position that represents a queue buffer according to Figure 6 may thus be "1010", wherein "10" represents two transferrable data packets, and "10" denotes that these are allocated priority level two.

This example shows the possibility of coding transfer requirements and priority levels. It is also possible to use four data bits for representing fifteen different states, where :

- a first state "0" denotes that no data packet is buffered in the buffer;

state "1", "2" and "3" denote that one, two and three or more data packets of a first priority;

states " A " , "5" and "6" denote one, two and three or more data packets of a second priority;

states "7", "8" and "9" denote one, two and three or more data packets of a third priority;

states "10", "11" and "12" denote one, two and three or more data packets of a fouth priority; and

- states "13", "14" and "15" denote one, two and three or more data packets of a fifth priority.

In a presentation such as this, a requirement according to Figure 6, i.e. the requirement to transfer two data packets having priority level two, would be represented by the state "5" or "0101".

The two-dimensional status matrix "sm" will thus only contain information relating to those data packets that are buffered in a subordinated priority-related queue buffer of the highest priority level. Information relating to buffered data packets of lower priority levels is thus unavailable when compiling the order. However, since data packets of higher priority level always take precedence over data packets of lower priority levels, this information is not required when compiling the order.

Irrespective of which of the above embodiments is used, a common embodiment can be used to compile necessary orders. This embodiment will be described below.

The order issuing unit 4 is adapted to compile an order in matrix form, a so-called order matrix "om", this matrix being shown in Figure 7.

The number of rows in an order matrix "om" corresponds to the total number of output buffers and the number of columns corresponds to the total number of ingress-selector stages, where respective columns kl , k2, ..., k8 are each intended for a respective ingress-selector stage 11, 12, ..., In, and where respective rows rl, r2, ..., r8 are each intended for a respective output buffer 21B, 22B, ..., 2nB .

The order matrix shown in Figure 7 is adapted to serve eight ingress-selector stages and eight egress-selector stages.

A position in a column belonging to the order matrix represents the number of data packets that, in accordance with the order, shall be transferred from a queue buffer related to the column-associated ingress-selector stage 11, 12, ..., In to the output buffer 21B, 22B, ..., 2nB that is represented by the row rl, r2, ..., r8 belonging to said position, during a next-following time interval.

An order matrix position includes a number of data bits that are able to represent at least the maximum possible number of data packets that can be transferred within a time interval . In one embodiment in which respective queue buffers represent a plurality of subordinated priority-related queue buffers, the order in respective positions in the order matrix "om" solely concerns those data packets that belong to the highest priority level, i.e. that queue buffer of the subordinated, priority-related queue buffers that contains buffered data packets and that represents the highest priority level .

In compiling the order matrix, certain criteria are used to ensure that the issued order will not utilize higher bandwidths on the conductors 311, 312, ..., 31n than are available, or that the issued order takes the coverage status of the output buffers 21B, 22B, ... , 2nB into consideration.

When respective queue buffers are placed physically in the ingress-selector stages to which the queue buffer is related, as in the case according to Figure 2, one such criterion is that the order issuing unit is adapted to compile the order matrix "om" so that the sum of the number of data bits in all positions in respective columns kl, k2, ..., k8 of the order matrix is equal to or smaller than the maximum possible number of data packets that can be transferred from respective ingress-selector stages 11, 12, ..., In to the selector core 3 during a time interval .

When respective output buffers are placed physically in the egress-selector stage to which a respective buffer is related, another criterion is that the order issuing unit will be adapted to compile the order matrix "om" so that the sum of the number of data bits in all positions in respective rows rl, r2, ..., r8 of the order matrix will be equal to or smaller than the maximum possible number of data packets that can be transferred from the selector core 3 to respective egress-selector stages 21, 22, ..., 2n during a time interval.

The sum of the number of data bits in all positions in respective rows rl, r2, ..., r3 may not exceed the number of data packets that can be accommodated in an output buffer 21B, 22B, ... , 2nB.

A further criterion is that when the order matrix "om" is compiled, the order issuing unit 4 will give priority to the transfer of data packets from an ingress-selector stage that has data packets buffered in a few queue buffers over the transfer of data packets from an ingress-selector stage that has data packets buffered in a plurality of queue buffers.

When respective queue buffers include a plurality of subordinated priority-related queue buffers, the order issuing unit, when compiling the order matrix "om", will give priority to the transfer of data packets from a subordinated queue buffer related to a higher priority level over the transfer of data packets from a subordinated queue buffer related to a lower priority level, and, when dealing with subordinated queue buffers of the same priority level, will give priority to the transfer of data packets from an ingress-selector stage that has data packets buffered in a plurality of subordinated priority-related queue buffers over the transfer of data packets from an ingress-selector stage that has data packets buffered in a plurality of subordinated priority-related queue buffers .

The time interval used will depend on different factors. Some of the factors included in this respect are the time required to compile the status matrix "sm", "3dsm", the time needed to transfer information from respective information collecting units 114, 124, ..., In4 to the information receiving unit 43, the time taken to compile the order matrix "om" and then send the order matrix from the order issuing unit 41 to respective order receiving units 113, 123, ..., In3.

It is desirable for these time intervals to be as short as possible, so as to obtain the fastest possible control of data packet transfer. The flow control unit 4 can be implemented in different ways, for instance with the use of a simple processor and associated software, a specially designed integrated circuit and associated software, or solely a specially designed integrated circuit where all functions are implemented with hardware, in the absence of software.

In view of the construction of the status matrix "sm", "3dsm" and the order matrix "om" respectively, a specially designed integrated circuit, or chip, having a plurality of parallel processors adapted to evaluate each row in the status matrix in parallel and thereafter form each column in the order matrix in parallel, will probably constitute the absolute fastest application, since a traditional simple processor is unable to carry out such parallel operations.

It will be obvious to the person skilled in this art that the various buffers referred to in this description may be comprised of separate physical buffers and/or various logic buffers within a common physical buffer. Thus, it is probable that queue buffers will constitute physical buffers on circuit boards belonging to respective ingress-selector stages, whereas subordinated priority-related queue buffers can be comprised of different logic buffers within a physically implemented queue buffer.

An ingress-selector stage and an egress-selector stage will normally form two parts of a common selector stage in a switching unit, even though these stages have been shown as two separate units in the Figures for the sake of simplicity.

The above description deals with the manner in which different units operate in accordance with a certain method. This method may also be applied with hardware of a slightly different construction or configuration. The present invention thus also relates to a method for managing data packet flow in accordance with the above description. One method according to the present invention is mainly based on the second queue buffers solely transferring information in accordance with an order received from the flow control unit.

The method is also based on the principle construction of a status matrix and an order matrix, where the status matrix is used as a basis for the later compiled order matrix, in accordance with the above description.

The aforesaid matrices have been described with rows and columns related to different buffers and selector stages in a specific manner. It will be understood, however, that matrices where the illustrated rows form columns and the illustrated columns form rows will also provide a solution to the problem mentioned with the same technical effect.

It will also be understood that the order of priority shown here for an explanatory reason, with a first subordinated queue buffer that represents a first priority level which, in turn, is the highest priority level, can also be reversed or given some other designation, for instance that the priority level which is given the highest number is considered to have the highest priority.

A highest priority level has been exemplified as real-time related traffic. However, the present invention can equally as well be applied in a switching unit constructed for data packet transfer where real-time related traffic does not occur at all, or only in exceptional circumstances, such as with so- called data-routers, for instance, such routers being adapted to control traffic within a local area network.

For the sake of simplicity, all ingress-selector stages and egress-selector stages belonging to the switching unit have been included by the flow control according to the present invention. There is nothing to prevent, however, one or more parts of a switching unit to be controlled by a flow control in accordance with the present invention permanently, or to be excluded from such control when required.

An example of this is shown in Figure 8, which shows the functioning of one or more ingress-selector stages and egress- selector stages that are not included by the flow control as described here.

Figure 8 is a schematic illustration of an exemplifying embodiment that includes a selector core 3 having eight ingress-selector stages il, i2, ..., i7, i8 and eight egress- selector stages el, e2, ..., e7, i8. Six ingress-selector stages and egress-selector stages il, i2, ..., i6; el, e2, ... , e6 are included by a flow control according to the present invention. The other two ingress-selector stages i7, i8 and egress-selector stages e7, e8 are not included by said flow control.

For instance, there may be found on dedicated ingress-selector stages and dedicated egress-selector stages that are always available to a specific subscriber, irrespective of other traffic through the switching unit and which need not therefore be included by an inventive flow control .

Neither is it necessary for an entire ingress-selector stage or an entire egress-selector stage to lie outside the flow control, since it is also possible for a part of the transfer capacity or bandwidth of an ingress-selector stage or an egress-selector stage to be dedicated and lie outside the flow control.

For instance, a subscriber may subscribe to a service that includes a given transfer capacity or bandwidth, which need not necessarily seize the entire capacity of an ingress- selector stage or egress-selector stage that is always at the disposal of the subscriber irrespective of other traffic through the switching unit and which need not therefore be included by the flow control . Necessary resources in output buffers and respective egress-selector stages must then also be reserved for such a subscriber.

Although the above description is restricted to a switching unit, it will be understood that the general concept of the invention can also be applied in the flow control of information-carrying data packets between nodes of a network, such as between computers in a data network, for instance.

Figure 9 shows a network "N" which is intended to be interconnected with several nodes Nl , N2, N3, N4, N5, N6 , N7, where these nodes are connected to each other either directly or indirectly.

The application of the present invention in a network is illustrated by a traffic situation in which information- carrying data packets shall be transferred from one or more first nodes Nl , N2, N3 to a second node N7, in the illustrated case via the node N4.

A flow control unit Fl functions to control the flow of data packets between all nodes Nl , N2, ..., N7, and in this specific traffic situation especially the nodes Nl, N2, N3 and N7.

It is necessary to control, or check, the transfer of data packets from the first nodes Nl, N2, N3 to the second node N7, because the first nodes Nl, N2, N3 need not necessarily be aware that a plurality of nodes communicate with the second node N7 simultaneously, and because the capacity to transfer information, i.e. the bandwidth, is limited between node N4 and the second node N7. A flow control is thus necessary.

Each node includes buffers of some kind in which information- carrying data packets are stored until they can be transferred to the next node. With the intention of simplifying an under- standing of this application of the present invention, nodes and associated buffers can be likened to the components in the application of a switching unit, such as the aforedescribed unit.

Using this comparison, buffers Bl in the first node Nl can be likened to the queue buffers 111, 112, ..., lln that are related to ingress-selector stage 11, buffers B2 in the first node N2 can be likened to queue buffers 121, 122, ..., 12n that are related to ingress-selector stage 12, buffers B3 in the first node N3 can be likened to queue buffers 131, 132, ..., 13n that are related to ingress-selector stage 13, buffers B4 in the node N4 can be likened to output buffer 21B in the selector core 3, and node N7 can be likened to egress- selector stage 21.

According to the aforedescribed method relating to flow control in a switching unit, this flow control can also be based on the transfer of data packets being permitted solely in response to an order from the flow control unit Fl and effected totally in accordance with said order.

Such an order may appropriately be compiled on the basis of information that includes the current need to send data packets from the first nodes Nl, N2, N3 to the second node N7.

Thus, the requirement for respective first nodes Nl , N2, N3 to send data packets to the second node N7 during a next- following time interval is compiled in a status matrix and an order specifying which transfer shall take place can be compiled in an order matrix in accordance with the application in a switching unit. Since the manner in which these matrices are compiled has been well-described with reference to application in a switching unit, the present description will not be burdened with a more specified explanation of how these latter matrices are formed. The flow control unit Fl may be allocated a position in a server or router in the network. One or more nodes may also include a flow control unit, irrespective of whether the node or nodes functions as a router or not.

When a node does not include a flow control unit, it must nevertheless be adapted to understand and to respond to a status query when compiling a status matrix, and also to receive and to act in accordance with an order received from the flow control unit. In the Figure 9 illustration, a flow control unit Fl is allocated a position in the node N4.

In the case of a flow control in a switching unit, respective status and order matrices will be symmetrical, as a result of the construction of the switching unit and the symmetry between the number of ingress-selector stages and egress- selector stages. This is not necessarily the case in a network, even though it may be so.

For instance, if the aforedescribed traffic situation is one in which the flow control unit Fl solely takes current traffic requirements into consideration and not the nodes N4, N5, N6 that are not included by the traffic, the matrices will obtain the formats 1x3 or 3x1. The matrix format can thus be changed with each new traffic situation.

It is also possible to take into consideration in each traffic situation all nodes that are served by a flow control unit, irrespective of which of said nodes needs to send information, which in the case illustrated in Figure 9 would result in a matrix format of 7x7, where the determinant is always zero.

Shown in the above example is a situation in which the first nodes are comprised of three nodes Nl , N2 , N3 and in which the second node is comprised of a node N7. It will be understood that in another situation, the nodes Nl and N4 may constitute first nodes that shall transfer information to a second node. for instance node N2.

Thus, the nodes that constitute first and second nodes respectively, and the number of first nodes in such a relationship, will change continuously in accordance with current traffic situations.

It will be evident to one skilled in this art that within a network a node can constitute both a first node Nl , with the intention of sending information to a second node N3 , and a second Nl, with the intention of receiving information from several first nodes N2, N4, in one and the same traffic situation. It will also be evident that all communication between the nodes may be bi-directional. Thus, the picture of first and second nodes respectively becomes highly complex in a network that includes a plurality of nodes. The afore-given example has therefore been greatly simplified, with the intention of illustrating the inventive concept.

The complexity and the continuously changing traffic situation also makes the collection and compilation of a status matrix and the calculation and dispatch of an order matrix highly complex. It is therefore probable that the time intervals required in this application will be longer than the time intervals required when applying the invention in a switching unit. Because traffic in network between, e.g., computers and the changes in traffic situations are both slower than those in a switching unit, a slower regulation of data flow can be permitted, therewith making longer time intervals acceptable.

However, there is a limitation to acceptable time interval durations, since traffic involved in a following traffic situation must wait until current or prevailing traffic situations have been dealt with. Such waiting times may not therefore be too long.

It will be understood that the invention is not restricted to the aforedescribed exemplifying embodiments thereof and that modifications can be made within the scope of the inventive concept as illustrated in the following Claims.

Claims

1. A method of controlling the flow of information in a switching unit which is intended to serve a plurality of subscribers and which includes a plurality of ingress-selector stages to which one or more respective subscribers are connected, a plurality of egress-selector stages to which one or more respective subscribers is connected, a selector core, a plurality of queue buffers related to respective ingress- selector stages, a plurality of output buffers of which at least one is related to respective egress-selector stages, and a flow control unit, wherein information-data packets from a first subscriber to a second subscriber can be stored temporarily in a queue buffer related to an ingress-selector stage allocated to a first subscriber, whereafter said data packets can be transferred to and thereafter stored in one of said output buffers via said selector core, and finally transferred to said second subscriber from said output buffer via an egress-selector stage allocated to said second subscriber, and wherein said flow control unit functions to control the flow of data packets between said queue buffers and said output buffers, characterized by controlling the transfer of said data packets from said queue buffers to said output buffers with the aid of said flow control unit by permitting said transfer of data packets to take place solely in response to an order from said flow control unit and to carry out said data packet transfer totally in accordance with said order.

2. A method according to Claim 1, characterized by compiling said order on the basis of information that includes the current need to send data packets from said queue buffers to said output buffers, and information relating to the current coverage status of said output buffers.

3. A method according to Claim 1 or Claim 2, characterized by including in said information the number of data packets that are currently stored in said queue buffers, and by also including in said information the identity of the output buffer to which respective buffered data packets shall be transferred.

4. A method according to Claims 1 to 3 , characterized in that the number of queue buffers related to respective ingress-selector stages corresponds to the number of egress- selector stages.

5. A method according to Claim 3, characterized by compiling the information relating to said queue buffers that are related to respective ingress-selector stages in vector form, in a so-called status vector; compiling a status matrix from said status vectors; compiling said status matrix so that the number of rows in said matrix will correspond to the number of output buffers; compiling said status matrix so that the number of columns in said matrix will correspond to the total number of ingress-selector stages; forming respective columns from a status vector that is adapted to represent an individual ingress-selector stage; and adapting respective rows so that each row will represent a respective output buffer.

6. A method according to Claim 5, characterized by adapting respective positions in a column of said status matrix to represent the number of data packets that are currently buffered in a queue buffer, related to the column-associated ingress-selector stage, from which data packets shall be transferred to the output buffer that is represented by the position-associated row during a coming time interval.

7. A method according to Claim 6, characterized by allocating a specific number of data bits to said position in said status matrix, wherein said number of data bits represents at least the maximum possible number of data packets that can be transferred within said time interval.

8. A method according to Claim 7, characterized in that said bit number is two; and in that said time interval corresponds to the time taken to transfer three data packets, a so-called three-packet interval.

9. A method according to Claim 7, characterized in that said number of one, and in that said time interval corresponds to the time taken to transfer one data packet, a so-called single-packet interval.

10. A method according to Claims 1 to 4, characterized by dividing respective queue buffers into a plurality of subordinated priority-related queue buffers; adapting respective subordinated queue buffers to transfer data packets that have been allocated a specific priority level; adapting a first subordinated queue buffer to forward data packets having a first priority level that corresponds to data packets of the highest priority, such as data packets that forward data in real time; adapting a second subordinated queue buffer to forward data packets of a second priority level that corresponds to data packets whose priority is lower than the first priority level, such as data packets with which a certain waiting time is allowable, and so on, wherein the total number of subordinated queue buffers corresponds to the number of different priority levels that can be managed by said switching unit.

11. A method according to Claim 10, characterized by compiling a priority-related status vector for each priority level and subordinated queue buffers related thereto and to respective ingress-selector stages; compiling an ingress- selector stage related status matrix from said priority- related status vector for respective ingress-selector stages; adapting respective positions in a column belonging to one of said ingress-selector stage related status matrices so as to represent the number of data packets currently buffered in a subordinated queue buffer of the priority level to which a current priority-related status-vector relates, said data packet being intended for transfer to the output buffer to which said subordinated queue buffer is related during a coming time interval; and by compiling a three-dimensional status matrix from said status matrices that are related to said ingress-selector stages.

12. A method according to Claim 11, characterized by allocating a specific number of data bits to respective positions in said three-dimensional status matrix; and adapting said number of data bits to represent at least the maximum possible number of data packets that can be transferred within said time interval.

13. A method according to Claims 1 to 5 and Claim 10, characterized by adapting respective positions in a column belonging to said status matrix to represent the number of data packets currently buffered in a subordinated priority-related queue buffer related to the column belonging to the ingress-selector stage, said data packets being intended for transfer to the output buffer that is represented by the row associated with said position during a coming time interval and to which priority level said data packet belongs.

14. A method according to Claim 13, characterized by adapting said position in said status matrix to include a specific number of data bits; and adapting said number to represent at least the maximum possible number of data packets that can be transferred in said time interval and the number of available priority levels represented by subordinated priority-related queue buffers.

15. A method according to Claims 13 and 14, characterized by relating the information in respective positions to the sub- ordinated queue buffer that represents the highest priority level of the subordinated queue buffers that contain at least one buffered data packet.

16. A method according to Claim 5, 6 or 10, characterized by compiling said order in a matrix form, in a so-called order matrix, wherein the number of order matrix rows corresponds to the number of output buffers, and the number of order matrix columns corresponds to the total number of ingress-selector stages, wherein each column relates to a respective ingress- selector stage and each row relates to a respective output buffer.

17. A method according to Claim 16, characterized by adapting respective positions in a order matrix column to represent the number of data packets that can be transferred in accordance with said order from a queue buffer that is related to the columna-associated ingress-selector stage to the output buffer that is represented by said position-associated row, during a next following time interval.

18. A method according to Claim 17, characterized by adapting said position in said order matrix to include a specific number of data bits, and by adapting said number of data bits to represent at least the maximum possible number of data packets that can be transferred in a time interval.

19. A method according to Claim 18, characterized in that said number is two, and in that the time interval corresponds to the time taken to transfer three data packets, a so-called three-packet interval.

20. A method according to Claim 18, characterized in that said number is one, and in that said time interval corresponds to the time taken to transfer one data packet, a so-called single-packet interval .

21. A method according to Claim 18, characterized in that when respective queue buffers are physically placed in the ingress-selector stages to which said queue buffers are related, said order matrix is compiled so that the sum of the number of data bits in all positions in respective columns belonging to said order matrix will be equal to or smaller than the maximum possible number of data packets that can be transferred from respective ingress-selector stages to said selector core during a time interval .

22. A method according to Claim 18, characterized in that the sum of the number of data bits in all positions in respective rows is equal to or smaller than the maximum possible number of data packets that can be accommodated in an output buffer.

23. A method according to Claim 18, characterized in that when respective output buffers are placed physically in the egress-selector stage to which the output buffer is related, said order matrix is compiled so that the sum of the number of data bits in all positions in respective rows belonging to said order matrix will be equal to or smaller than the maximum possible number of data packets that can be transferred from said selector core to respective egress-selector stages during a time interval .

24. A method according to Claim 16, characterized by adapting said order matrix to give priority to the transfer of data packets from an ingress-selector stage that has data packets buffered in only a few queue buffers over the transfer of data packets from an ingress-selector stage that has data packets buffered in a plurality of queue buffers.

25. A method according to Claim 16, characterized in that when respective queue buffers include a plurality of subordinated priority-related queue buffers, the order matrix is adapted to give priority to the transfer of data packets from a subordinated queue buffer related to a high priority level over the transfer of data packets from a subordinated queue buffer related to a lower priority level; and in that when handling subordinated queue buffers of mutually the same priority level, said order matrix is adapted to give priority to the transfer of data packets from an ingress-selector stage that has data packets buffered in only a few subordinated priority-related queue buffers over the transfer of data packets from an ingress-selector stage that has data packets buffered in a plurality of subordinated priority-related queue buffers .

26. A switching unit intended for serving a plurality of subscribers, comprising a plurality of ingress-selector stages to which one or more subscribers is/are connected, a number of egress-selector stages to which one or more subscribers is/are connected, a selector core, a number of queue buffers related to respective ingress-selector stages, a number of output buffers of which at least one is related to respective egress- selector stages, and a flow control unit, wherewith information-carrying data packets from a first subscriber to a second subscriber can be stored temporarily in a queue buffer related to an ingress-selector stage allocated to said first subscriber, said data packets being transferrable to and thereafter storable in one of said output buffers via said selector core, so as to be transferrable to said second subscriber from said output buffer via an egress-selector stage allocated to said second subscriber, and wherewith said flow control unit is adapted to control the flow of data packets between said queue buffers and said output buffers, characterized in that the flow control unit includes an order issuing unit, in that respective ingress-selector stages include an order receiving unit, and in that the flow of data packets between said queue buffers and said output buffers can be controlled via an order from said order issuing unit to said order receiving units and in that the transfer of data packets is permitted solely upon receipt of said order from the order issuing unit and is carried out totally in accordance with said order.

27. A switching unit according to Claim 26, characterized in that respective ingress-selector stages include an information collecting unit; in that respective information collecting units are adapted to collect information relating to the current status of those queue buffers that belong to respective ingress-selector stages; in that said flow control unit includes a coverage status evaluating unit; in that said coverage status evaluating unit is adapted to establish the current degree of coverage afforded by respective output buffers; in that said flow control unit includes an information receiving unit; in that the information receiving unit is adapted to receive the information collected by respective information collecting units; in that said order issuing unit is adapted to compile and send said order on a basis from the collected information and on the coverage status of said output buffers, and in that respective order receiving units are adapted to receive and to carry out said order.

28. A switching unit according to Claims 26 or 27, characterized in that the information collected by the information collecting unit includes the number of data packets currently stored in said queue buffers; and in that said information also includes the identity of the output buffer to which respective buffered data packets shall be transferred.

29. A switching unit according to Claim 26, characterized in that the number of queue buffers related to respective ingress-selector stages corresponds to the number of egress- selector stages.

30. A switching unit according to Claim 28, characterized in that respective information collecting units function to compile said information in vector form, in a so-called status vector; in that the information receiving unit is adapted to compile a status matrix from said status vectors; in that the number of rows in said status matrix corresponds to the number of output buffers; in that the number of columns in said status matrix corresponds to the total number of ingress- selector stages; in that respective columns are comprised of a status vector which is adapted to represent an ingress- selector stage; and in that respective rows are adapted to each represent a respective output buffer.

31. A switching unit according to Claim 30, characterized in that respective positions in a column belonging to said status matrix are adapted to represent the number of data packets currently buffered in a queue buffer that is related to the column-associated ingress-selector stage, said data packets being intended for transfer to the output buffer that is represented by the row associated with said position, during a coming time interval.

32. A switching unit according to Claim 31, characterized in that said position in said status matrix includes a specific number of data bits; and in that said number of data bits is adapted so as to be able to represent at least the maximum possible number of data packets that can be transferred in said time interval.

33. A switching unit according to Claim 32, characterized in that said number is two; and in that said time interval corresponds to the time taken to transfer three data packets, a so-called three-packet interval.

34. A switching unit according to Claim 33, characterized in that said number is one, and in that said time interval corresponds to the time taken to transfer one data packet, a so- called single-packet interval.

35. A switching unit according to Claims 26 to 29, characterized in that respective queue buffers are adapted to include a number of subordinated priority-related queue buffers; in that respective subordinated queue buffers are adapted to transfer data packets that are allocated a specific priority level; in that a first subordinated queue buffer is adapted to forward data packets having a first priority level that corresponds to data packets of the highest priority, such as data packets intended to forward data in real time; in that a second subordinated queue buffer is adapted to forward data packets that have a second priority level corresponding to data packets belonging to a lower priority than said first priority level, such as data packets with which a certain delay is permitted, and so on, wherein the total number of subordinated queue buffers corresponds to the number of different priority levels that can be managed by the switching unit.

36. A switching unit according to Claim 35, characterized in that respective information collecting units are adapted to compile a priority-related status vector for each priority level and subordinated queue buffers related thereto and to respective ingress-selector stages; in that respective information collecting units are adapted to compile from said priority-related status vectors a status matrix related to an ingress-selector stage; in that respective positions in a column belonging to one of said status matrices related to said ingress-selector stage are adapted to represent the number of data packets currently buffered in a subordinated queue buffer of the priority to which the priority-related status vector concerned relates, these data packets being intended for transfer to the output buffer to which said subordinated queue buffer is related during a coming time interval; and in that said information receiving unit is adapted to compile a three-dimensional status matrix from said status matrices that are related to respective ingress- selector stages.

37. A switching unit according to Claim 36, characterized in that respective positions in said three-dimensional status matrix are allocated a specific number of data bits; and in that said number of data bits is adapted to be able to represent at least the maximum possible number of data packets that can be transferred in said time interval.

38. A switching unit according to Claims 26 to 30 and to Claim 35, characterized in that respective positions in a column belonging to said status matrix are adapted to represent the number of data packets currently buffered in a subordinated queue buffer of given priority level and related to the ingress-selector stage belonging to said column, said data packets being intended for transfer to the output buffer that is represented by the row belonging to said position during a coming time interval, and to which priority level said data packets belong.

39. A switching unit according to Claim 38, characterized in that said position in said status matrix includes a specific number of data bits; and in that said number is adapted to be able to represent at least the maximum possible number of data packets that can be transferred in said time interval and the number of available priority levels represented by subordinated priority-related queue buffers.

40. A switching unit according to Claims 38 and 39, characterized in that the information in respective positions is related to the subordinated priority-related queue buffer that represents the highest priority of the subordinated queue buffers that contain at least one buffered data packet.

41. A switching unit according to Claim 30, 31 or 35, characterized in that said order issuing unit is adapted to compile said order in matrix form, in a so-called order matrix; in that the number of rows in the order matrix corresponds to the total number of output buffers; in that the number of columns in said order matrix corresponds to the total number of ingress-selector stages; in that respective columns are each intended for a respective ingress-selector stage; and in that respective rows are each is intended for a respective output buffer.

42. A switching unit according to Claim 41, characterized in that respective positions in a column belonging to said order matrix are adapted to represent the number of data packets that are to be transferred from a queue buffer related to the column-associated ingress-selector stage to the output buffer represented by the row belonging to said position in accordance with said order, during a next coming time interval .

43. A switching unit according to Claim 42, characterized in that said position in said order matrix includes a specific number of data bits; and in that said number of data bits is adapted to be able to represent at least the maximum possible number of data packets that can be transferred in a time interval .

44. A switching unit according to Claim 43, characterized in that said number is two; and in that said time interval corresponds to the time taken to transfer three data packets, a so- called three-packet interval.

45. A switching unit according to Claim 43, characterized in that said number is one; and in that said time interval corresponds to the time taken to transfer one data packet, a so- called single packet interval.

46. A switching unit according to Claim 43, characterized in that when respective queue buffers are placed physically in the ingress-selector stages to which said buffer is related, the order issuing unit is adapted to conform said order matrix so that the sum of the number of data bits in all positions in respective columns belonging to said order matrix will be equal to or smaller than the maximum possible number of data packets that can be transferred from respective ingress- selector stages to said selector core during a time interval.

47. A switching unit according to Claim 43, characterized in that said order issuing unit is adapted to compile said order matrix so that the sum of the number of data bits in all positions in respective rows belonging to said order matrix will be equal to or smaller than the maximum possible number of data packets that can be accommodated in an output buffer.

48. A switching unit according to Claim 43, characterized in that when respective output buffers are placed physically in the egress-selector stage to which a respective buffer is related, the order issuing unit is adapted to compile said order matrix so that the sum of the number of data bits in all positions in respective rows belonging to said order matrix will be equal to or smaller than the maximum possible number of data packets that can be transferred from said selector core to respective egress-selector stages during a time interval.

49. A switching unit according to Claim 41, characterized in that in compiling said order matrix said order issuing unit functions to give priority to the transfer of data packets from an ingress-selector stage that has data packets buffered in only a few queue buffers over the transfer of data packets from an ingress-selector stage that has data packets buffered in a plurality of queue buffers.

50. A switching unit according to Claim 41, characterized in that when respective queue buffers include a plurality of subordinated, priority-related queue buffers, said order issuing unit functions to give priority to the transfer of data packets from a subordinated queue buffer related to a higher priority level over the transfer of data packets from a subordinated queue buffer related to a lower priority level, when compiling said order matrix; and in that when handling subordinated queue buffers of mutually the same priority level, said order issuing unit functions to give priority to the transfer of data packets from an ingress-selector stage that has data packets buffered in only a few subordinated, priority-related queue buffers over the transfer of data packets from an ingress-selector stage that has data packets buffered in a plurality of subordinated, priority-related queue buffers, when compiling said order matrix.

51. A method of controlling the flow of information in a network which is intended to interconnect a plurality of nodes, where a number of nodes are mutually interconnected, either directly or indirectly, whereby information-carrying data packets can be transferred from one or several first nodes to a second node, characterized by adapting a flow control unit to control the flow of data packets between said nodes; and by controlling the transfer of said data packet from said first node or nodes to said second node by virtue of allowing the transfer of data packets solely in response to an order from said flow control unit and in total accordance with said order.

52. A method according to Claim 51, characterized in that said order is compiled on the basis of information that includes the current need to send data packets from the first node or nodes to said second node.