WO1998039777A2 - Self-test for integrated memories - Google Patents
Self-test for integrated memories Download PDFInfo
- Publication number
- WO1998039777A2 WO1998039777A2 PCT/IB1998/000217 IB9800217W WO9839777A2 WO 1998039777 A2 WO1998039777 A2 WO 1998039777A2 IB 9800217 W IB9800217 W IB 9800217W WO 9839777 A2 WO9839777 A2 WO 9839777A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- test
- data
- background
- gate
- data word
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/10—Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/36—Data generation devices, e.g. data inverters
Definitions
- the invention relates to an integrated circuit comprising: (1) a read/write memory having a plurality of memory locations for N-bit wide data words which are each accessible by means of unique memory addresses; (2) a test circuit for testing said memory, which test circuit includes a test controller for successively writing, on series of memory locations, a test data word and reading out a response data word, said test data word in a first phase corresponding to a data background and, in a second phase, to an inverse of said data background, and test logic for bit-wise checking whether the contents of the response data word is correct.
- the invention further relates to a method of testing a read/write memory for N-bit wide data words by means of a test circuit which is fixedly coupled to the memory, which method comprises the following steps: (1) writing an N-bit wide data background on a memory location; (2) reading out a response data word at said memory location; (3) bit-wise checking whether the contents of the response data word is correct; (4) repeating steps (1) through (3) for an inverse of the data background.
- IC integrated circuit
- the IC described therein comprises a memory which can be subjected to a test in accordance with the Built-in Self-Test (BIST) principle.
- BIST Built-in Self-Test
- a test circuit is integrated on the IC which can independently test the memory.
- the test circuit writes a series of test data words (consisting of one or more so-called data backgrounds and the inverses thereof) in the memory, whereafter response data words are read out and compared with the written test data words.
- Correspondence between the response data words and the test data words confirms the proper functioning of the memory.
- the data backgrounds must be such that a large number of frequently occurring defects are detected.
- the known IC comprises a test circuit of unlimited flexibility as regards the data backgrounds to be used.
- a problem with such an approach is that the test logic takes up a relatively large surface area.
- an IC in accordance with the invention is characterized in that the test logic intrinsically comprises patterns of the data background and of the inverse of the data background, and in that the test logic is embodied so as to simultaneously employ both patterns to check the response data word.
- a test circuit in accordance with the invention is optimized for one data background and the inverse thereof. It has been found that one suitably selected data background (and the inverse thereof) is sufficient to detect the most frequent defects. As a result, supplying the written test data word to the test logic can be omitted.
- step (3) includes: carrying out a logical function on the response data word, said function being predetermined by patterns of the data background and of the inverse of said data background, and both patterns being used simultaneously. Consequently, unlike the method described in said United States patent specification, there is no bit- wise comparison between the response data word and the written test data word.
- the data background and the inverse thereof are incorporated in the logical function which is carried out on the response data word.
- test logic is provided with a bus comprising N data lines for receiving the response data word, a first and a second circuit being connected in parallel to the bus to check whether the contents of the response data word match the data background and the inverse of the data background, respectively.
- the first circuit comprises an OR gate and the second circuit comprises an AND gate, each gate being provided with at least N inputs.
- Each data line which conveys a first value if the response data word corresponds to the data background is coupled via an inverter to a corresponding input of the OR gate and to a corresponding input of the AND gate, while each of the other data lines is directly coupled to a corresponding input of the OR gate and to a corresponding input of the AND gate.
- these gates can be implemented much more advantageously than the test logic of the known IC.
- NAND and NOR gates For example, only two important conditions are to be met, namely that the first circuit as such should be capable of carrying out an AND function, and that the second circuit as such should be capable of carrying out an OR function, the results being passed on inverted or unin verted.
- a more advanced variant of the last-mentioned embodiment is characterized in that the AND gate and the OR gate both comprise an input connected to the test controller, for receiving a signal originating from the test controller, which signal respectively has a second value or the first value if, as anticipated, the response data word corresponds, respectively, to the data background or the inverse of the data background.
- This has the advantage that if a response data word corresponds to the inverse of what was expected, this can be distinguished from the case in which the response data word corresponds to what is expected. This enables a higher error covering ratio to be achieved.
- An embodiment of the IC in accordance with the invention is characterized in that adjoining bits of the data background have complementary values.
- This data background has the advantage that, in addition to the so-called stuck-at faults, also specific coupling faults within a memory location and between adjoining memory locations are activated.
- test controller comprises a shift register for storing the data background.
- FIG. 1 schematically shows the IC in accordance with the prior art
- Fig. 2 schematically shows the relevant part of a first embodiment of an IC in accordance with the invention
- FIG. 3 schematically shows the relevant part of a second embodiment of an IC in accordance with the invention.
- Fig. 1 schematically shows the IC in accordance with the prior art.
- the IC 100 comprises a read/write memory 102 and a test circuit 104 for testing the memory.
- the memory 102 is connected to possible other components of the IC via a connection 112 which is responsible for the communication necessary for the operation of the IC as a whole.
- the memory 102 and the test circuit 104 are connected to one another via a connection 114.
- the test circuit 104 comprises a connection 116.
- This communication may be implemented in various ways, for example on the basis of scan-chains, TAP (test access port) or otherwise.
- the invention relates to the test circuit 104.
- Fig. 2 schematically shows the relevant part of a first embodiment of an IC in accordance with the invention.
- the elements of the IC which are not relevant to the invention have been omitted.
- the above-mentioned terms, i.e. first and second value correspond, respectively, to logical 0 and logical 1.
- a read/ write memory 202 is embodied so as to store 4-bit wide data words.
- the memory 202 comprises a number of memory locations (typically several hundred to many millions) which are all accessible by means of respective unique addresses.
- a BIST test circuit is integrated on the IC. This test circuit comprises a test controller 204 and test logic 206.
- the test controller 204 is capable of generating addresses (a), data (d) and a write-enable (WE) signal for writing test data words on series of memory locations. These test data words correspond to 1010 (data background) and 0101 (inverted data background). Said test controller 204 is also capable of generating addresses and a read-enable (RE) signal for reading response data words on series of memory locations. These response data words become available at an output of the memory 202. In Fig. 2, this is indicated by q(0)-q(3), which represent the 4 independent bits of a response data word. Said output is connected to the test logic 206 via a first bus 224 for passing on response data words.
- the data lines of a second bus 222 of the test logic 206 are connected to corresponding data lines of the first bus 224.
- An inverter 232 is provided for every second data line.
- the test logic 206 is embodied so as to check whether the contents of the response data word is correct. In this embodiment, this is achieved by means of an OR gate 242, an AND gate 244 and a XOR gate 246. To pass on a result of this check, the test logic 206 is connected to the test controller 204.
- the inverters may be incorporated in the OR gate 242 and the AND gate 244 by alternately using PMOS transistors and NMOS transistors. Other optimizations are also possible. In general, it can be said that Fig.
- test logic 206 gives a functional description of the test logic 206 in this embodiment. Possibly, the individual components of the test logic 206 are no longer recognizable in the eventual realization on the IC. These components themselves are not relevant to the invention. The only essential feature is that the patterns of the data background and the inverse of the data background are already incorporated in the test logic 206 in accordance with the invention, so that they do not have to be presented separately to the test logic 206.
- test controller 204 presents an address, the data background and a WE signal to the memory 202, the timing requirements imposed by said memory being met, and hence writes a test data word in the memory; (2) the test controller 204 presents an address and an RE signal to the memory 202, the timing requirements imposed by said memory being met, and hence reads a response data word from the memory; (3) the test logic 206 checks bit- wise whether the contents of the response data word is correct. Subsequently, said steps are repeated for the inverse of the data background.
- step (3) is relevant to the invention.
- the step characteristic of the invention i.e. in which it is checked bit-wise whether the contents of the response data word is correct, can be explained as follows. If the data lines of the bus 222 only convey a 0, this is detected ( e. a deviant output signal is generated) by the OR gate 242. If the data lines of the bus 222 only convey a 1, this is detected (i.e. a deviant output signal is generated) by the AND gate 244.
- the same result can alternatively be achieved by replacing one or both gates by NOR and/or NAND gates.
- This situation is detected by the XOR gate 246, so that in the case of an error, the output of the XOR gate 246 conveys a 1.
- the test controller can store the corresponding address to make it available for diagnosis after the completion of the test.
- the test is interrupted as soon as a deviant response data word is detected, and only an error signal is made available.
- Fig. 3 schematically shows the relevant part of a second embodiment of an IC in accordance with the invention.
- a property of the test circuit shown in Fig. 2 is that response data words corresponding to the data background or to the inverse of the data background are always approved. In theory, however, it is possible that the response data word corresponds to the data background while its inverse was expected, or conversely.
- the test circuit of the second embodiment comprises an additional connection 310 between the test controller 304 and the test logic 306 for stating which one of these two possible data words is expected. This signal has the value 1 if the response data word is expected to correspond to the data background, and the value 0 if the response data word is expected to correspond to the inverse of the data background.
- both the OR gate 342 and the AND gate 344 have an additional input to which this signal is applied.
- this additional input there are only ones and zeros, respectively, at the inputs of the OR gate 342 and the AND gate 344 if, as expected, the response data word corresponds, respectively, to the data background and the inverse of the data background.
- test controller can be optimized for this purpose.
- special data background 0101 use can be made of the property that this data background and the inverse thereof can be derived from each other by shifting by one bit.
- a shift register 320 utilizes this property of the data background.
- the use of this principle leads to a further simplification of the test circuit and hence to a further reduction of the IC-surface, as test circuits suited for a number of data backgrounds must use relatively complex logic to derive and present these data backgrounds and the inverses thereof.
- the test circuit can be readily adapted so that it is capable of testing more than one memory. In practice this boils down to rendering the memories to be tested selectable for the test circuit and adapting the test circuit so that it can deal with possible differences in the address ranges of the memories.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98902148A EP0896720A2 (en) | 1997-03-04 | 1998-02-23 | Self-test for integrated memories |
KR1019980708848A KR20000065188A (en) | 1997-03-04 | 1998-02-23 | Integrated circuit having read / write memory and test circuit for testing same, and read / write memory test method |
PCT/IB1998/000217 WO1998039777A2 (en) | 1997-03-04 | 1998-02-23 | Self-test for integrated memories |
JP10529265A JP2000509874A (en) | 1997-03-04 | 1998-02-23 | Self-test for integrated memory |
Applications Claiming Priority (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP97200636.5 | 1997-03-04 | ||
EP97200636 | 1997-03-04 | ||
PCT/IB1998/000217 WO1998039777A2 (en) | 1997-03-04 | 1998-02-23 | Self-test for integrated memories |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1998039777A2 true WO1998039777A2 (en) | 1998-09-11 |
WO1998039777A3 WO1998039777A3 (en) | 1998-12-17 |
Family
ID=26146206
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/IB1998/000217 WO1998039777A2 (en) | 1997-03-04 | 1998-02-23 | Self-test for integrated memories |
Country Status (3)
Country | Link |
---|---|
EP (1) | EP0896720A2 (en) |
KR (1) | KR20000065188A (en) |
WO (1) | WO1998039777A2 (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100786414B1 (en) * | 2000-09-11 | 2007-12-17 | 애질런트 테크놀로지스, 인크. | Method and apparatus for administering inversion properties in a memory tester |
Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5568437A (en) * | 1995-06-20 | 1996-10-22 | Vlsi Technology, Inc. | Built-in self test for integrated circuits having read/write memory |
EP0744755A1 (en) * | 1995-05-25 | 1996-11-27 | International Business Machines Corporation | Test method and device for embedded memories on semiconductor substrates |
-
1998
- 1998-02-23 KR KR1019980708848A patent/KR20000065188A/en not_active Application Discontinuation
- 1998-02-23 EP EP98902148A patent/EP0896720A2/en not_active Withdrawn
- 1998-02-23 WO PCT/IB1998/000217 patent/WO1998039777A2/en not_active Application Discontinuation
Patent Citations (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP0744755A1 (en) * | 1995-05-25 | 1996-11-27 | International Business Machines Corporation | Test method and device for embedded memories on semiconductor substrates |
US5568437A (en) * | 1995-06-20 | 1996-10-22 | Vlsi Technology, Inc. | Built-in self test for integrated circuits having read/write memory |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100786414B1 (en) * | 2000-09-11 | 2007-12-17 | 애질런트 테크놀로지스, 인크. | Method and apparatus for administering inversion properties in a memory tester |
Also Published As
Publication number | Publication date |
---|---|
EP0896720A2 (en) | 1999-02-17 |
KR20000065188A (en) | 2000-11-06 |
WO1998039777A3 (en) | 1998-12-17 |
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