WO1998039777A3 - Self-test for integrated memories - Google Patents

Self-test for integrated memories Download PDF

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Publication number
WO1998039777A3
WO1998039777A3 PCT/IB1998/000217 IB9800217W WO9839777A3 WO 1998039777 A3 WO1998039777 A3 WO 1998039777A3 IB 9800217 W IB9800217 W IB 9800217W WO 9839777 A3 WO9839777 A3 WO 9839777A3
Authority
WO
WIPO (PCT)
Prior art keywords
test
data word
background
data
inverse
Prior art date
Application number
PCT/IB1998/000217
Other languages
French (fr)
Other versions
WO1998039777A2 (en
Inventor
Guillaume Elisabeth A Lousberg
Martinus Johannes Verstraelen
Original Assignee
Koninkl Philips Electronics Nv
Philips Norden Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Philips Norden Ab filed Critical Koninkl Philips Electronics Nv
Priority to EP98902148A priority Critical patent/EP0896720A2/en
Priority to KR1019980708848A priority patent/KR20000065188A/en
Priority to PCT/IB1998/000217 priority patent/WO1998039777A2/en
Priority to JP10529265A priority patent/JP2000509874A/en
Publication of WO1998039777A2 publication Critical patent/WO1998039777A2/en
Publication of WO1998039777A3 publication Critical patent/WO1998039777A3/en

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/10Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns 
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C29/00Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/36Data generation devices, e.g. data inverters

Abstract

The invention relates to an integrated circuit comprising a read/write memory and a test circuit for testing said memory. The test circuit includes a test controller for successively writing, on series of memory locations, a test data word and reading out a response data word, said test data word in a first phase corresponding to a data background and in a second phase to an inverse of said data background. The test circuit further includes test logic for bit-wise checking whether the contents of the response data word is correct. The invention is characterized in that the test logic intrinsically comprises patterns of the data background and of the inverse of the data background, and said test logic is embodied so as to simultaneously use both patterns to check the response data word.
PCT/IB1998/000217 1997-03-04 1998-02-23 Self-test for integrated memories WO1998039777A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
EP98902148A EP0896720A2 (en) 1997-03-04 1998-02-23 Self-test for integrated memories
KR1019980708848A KR20000065188A (en) 1997-03-04 1998-02-23 Integrated circuit having read / write memory and test circuit for testing same, and read / write memory test method
PCT/IB1998/000217 WO1998039777A2 (en) 1997-03-04 1998-02-23 Self-test for integrated memories
JP10529265A JP2000509874A (en) 1997-03-04 1998-02-23 Self-test for integrated memory

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
EP97200636.5 1997-03-04
EP97200636 1997-03-04
PCT/IB1998/000217 WO1998039777A2 (en) 1997-03-04 1998-02-23 Self-test for integrated memories

Publications (2)

Publication Number Publication Date
WO1998039777A2 WO1998039777A2 (en) 1998-09-11
WO1998039777A3 true WO1998039777A3 (en) 1998-12-17

Family

ID=26146206

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB1998/000217 WO1998039777A2 (en) 1997-03-04 1998-02-23 Self-test for integrated memories

Country Status (3)

Country Link
EP (1) EP0896720A2 (en)
KR (1) KR20000065188A (en)
WO (1) WO1998039777A2 (en)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6973404B1 (en) * 2000-09-11 2005-12-06 Agilent Technologies, Inc. Method and apparatus for administering inversion property in a memory tester

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5568437A (en) * 1995-06-20 1996-10-22 Vlsi Technology, Inc. Built-in self test for integrated circuits having read/write memory
EP0744755A1 (en) * 1995-05-25 1996-11-27 International Business Machines Corporation Test method and device for embedded memories on semiconductor substrates

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0744755A1 (en) * 1995-05-25 1996-11-27 International Business Machines Corporation Test method and device for embedded memories on semiconductor substrates
US5568437A (en) * 1995-06-20 1996-10-22 Vlsi Technology, Inc. Built-in self test for integrated circuits having read/write memory

Also Published As

Publication number Publication date
EP0896720A2 (en) 1999-02-17
KR20000065188A (en) 2000-11-06
WO1998039777A2 (en) 1998-09-11

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