WO1998039846A3 - Delay-locked loop with binary-coupled capacitor - Google Patents

Delay-locked loop with binary-coupled capacitor Download PDF

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Publication number
WO1998039846A3
WO1998039846A3 PCT/US1998/004346 US9804346W WO9839846A3 WO 1998039846 A3 WO1998039846 A3 WO 1998039846A3 US 9804346 W US9804346 W US 9804346W WO 9839846 A3 WO9839846 A3 WO 9839846A3
Authority
WO
WIPO (PCT)
Prior art keywords
clock signal
delay
variable
capacitance
delay line
Prior art date
Application number
PCT/US1998/004346
Other languages
French (fr)
Other versions
WO1998039846A2 (en
Inventor
Troy A Manning
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to AU65433/98A priority Critical patent/AU6543398A/en
Priority to JP53881698A priority patent/JP3778946B2/en
Priority to KR1019997008090A priority patent/KR100662221B1/en
Publication of WO1998039846A2 publication Critical patent/WO1998039846A2/en
Publication of WO1998039846A3 publication Critical patent/WO1998039846A3/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/13—Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals
    • H03K5/131—Digitally controlled
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION, OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H03L7/081—Details of the phase-locked loop provided with an additional controlled phase shifter
    • H03L7/0812—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used
    • H03L7/0814—Details of the phase-locked loop provided with an additional controlled phase shifter and where no voltage or current controlled oscillator is used the phase shifting device being digitally controlled

Abstract

A delay-locked loop incorporates binary-coupled capacitors in a capacitor bank to produce a variable capacitance along a delay line. The variable capacitance allows a delay of the variable delay line to be varied. In response to an input clock signal, the variable delay line produces a delayed output clock signal that is compared at a race detection circuit to the input clock signal. If the delayed clock signal leads the input clock signal, the race detection circuit increments a counter that controls the binary-coupled capacitors. The incremented counter increases the capacitance by coupling additional capacitance to the variable delay line to delay propagation of the delayed clock signal. If the delayed clock signal lags the original clock signal, the race detection circuit decrements the counter to decrease the capacitance, thereby decreasing the delay of the variable delay line. The race detection circuit includes an arbitration circuit that detects when the delayed clock signal and the variable clock signal are substantially synchronized and disables incrementing or decrementing of the counter in response.
PCT/US1998/004346 1997-03-05 1998-03-05 Delay-locked loop with binary-coupled capacitor WO1998039846A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
AU65433/98A AU6543398A (en) 1997-03-05 1998-03-05 Delay-locked loop with binary-coupled capacitor
JP53881698A JP3778946B2 (en) 1997-03-05 1998-03-05 Delay locked loop with binary coupled capacitors
KR1019997008090A KR100662221B1 (en) 1997-03-05 1998-03-05 Delay-locked loop with binary-coupled capacitor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US08/811,918 1997-03-05
US08/811,918 US5946244A (en) 1997-03-05 1997-03-05 Delay-locked loop with binary-coupled capacitor

Publications (2)

Publication Number Publication Date
WO1998039846A2 WO1998039846A2 (en) 1998-09-11
WO1998039846A3 true WO1998039846A3 (en) 1998-12-03

Family

ID=25207946

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/004346 WO1998039846A2 (en) 1997-03-05 1998-03-05 Delay-locked loop with binary-coupled capacitor

Country Status (5)

Country Link
US (7) US5946244A (en)
JP (1) JP3778946B2 (en)
KR (1) KR100662221B1 (en)
AU (1) AU6543398A (en)
WO (1) WO1998039846A2 (en)

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