WO1998044405A1 - Automatic transitioning between acpi c3 and c2 states - Google Patents

Automatic transitioning between acpi c3 and c2 states Download PDF

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Publication number
WO1998044405A1
WO1998044405A1 PCT/US1998/001907 US9801907W WO9844405A1 WO 1998044405 A1 WO1998044405 A1 WO 1998044405A1 US 9801907 W US9801907 W US 9801907W WO 9844405 A1 WO9844405 A1 WO 9844405A1
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WIPO (PCT)
Prior art keywords
power
state
electronic device
processing unit
power state
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PCT/US1998/001907
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French (fr)
Inventor
David Poisner
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Intel Corporation
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Publication date
Application filed by Intel Corporation filed Critical Intel Corporation
Priority to AU61400/98A priority Critical patent/AU6140098A/en
Priority to DE19882269T priority patent/DE19882269T1/en
Priority to GB9922090A priority patent/GB2338806A/en
Publication of WO1998044405A1 publication Critical patent/WO1998044405A1/en

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    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26Power supply means, e.g. regulation thereof
    • G06F1/32Means for saving power
    • G06F1/3203Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3206Monitoring of events, devices or parameters that trigger a change in power modality
    • G06F1/3215Monitoring of peripheral devices
    • G06F1/3225Monitoring of peripheral devices of memory devices
    • GPHYSICS
    • G06COMPUTING; CALCULATING OR COUNTING
    • G06FELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02Addressing or allocation; Relocation
    • G06F12/08Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0806Multiuser, multiprocessor or multiprocessing cache systems
    • G06F12/0815Cache consistency protocols
    • G06F12/0831Cache consistency protocols using a bus scheme, e.g. with bus monitoring or watching means

Definitions

  • the present invention relates generally to reducing average power consumption by electronic devices. More particularly, the present invention relates to keeping the electronic devices in as low a power state as possible by turning off the electronic devices when various system caches do not need to be snooped.
  • Portable computers enable workers and students to have computing power on demand at a variety of locations and not be limited by the power supply of a desktop machine.
  • portable computing devices are frequently limited by the amount of time that they can run on battery power without reconnection to an AC power supply.
  • engineers are continuously trying to find ways of reducing the power consumption of various components of portable computers, including the central processing unit.
  • Keeping electronic devices such as a central processing unit, a memory controller or a memory in their lowest possible power state provides a number of benefits. For example, it allows battery operated machines to operate for longer periods of time between recharging. A reduction in power consumption also reduces thermal dissipation by the central processing unit. Reduced thermal dissipation allows the central processing unit to run at full speed for longer periods of time, while remaining within its thermal dissipation specifications. Reduced thermal dissipation also reduces the need for fans and other components used to prevent heat build-up in a computer. Finally, keeping the electronic device in a lower power state than could otherwise be achieved and reducing the number of transitions between power states improves system performance by reducing latencies caused by switching between designated power states.
  • ACPI advanced configuration and power interface
  • OSPM operating system directed power management
  • the goal of ACPI is to enhance power management functionality and robustness, as well as facilitating industry wide implementation of common power management features.
  • the ACPI specification is a publicly available document and can be obtained from the Internet at www//http.teleport.com/ ⁇ ACPI.
  • the ACPI defines a number of processor power states which are processor power consumption and thermal management states within a global working state. These processor states include a (i) C0 power state, (ii) Cl power state, (iii) C2 power state, and (iv) C3 power state.
  • the processor executes instructions and is at full power.
  • the processor is in a non-executing power state.
  • the C2 power state uses less power than the Cl state.
  • the processor still allows the bus to snoop the processor cache memory and thereby maintain cache coherency.
  • the C3 power state offers improved power savings over the Cl and C2 power states.
  • the processor cache ignores any snoops.
  • the operating software is responsible for ensuring that the processor caches maintain coherency.
  • the C0, Cl, C2 and C3 power states of the ACPI map into various power states of commercial microprocessors.
  • the C0 power state maps into a normal state in which all clocks are running
  • the C2 power state maps into a STOP GRANT state
  • the C3 power state maps into a STOP CLOCK state.
  • PCI Peripheral Component Interconnect
  • FIG. 1 A flow chart of a conventional implementation of a bus access is given in Figure 1.
  • the central processing unit CPU
  • the CPU disables an arbiter in step 104.
  • the CPU transitions to a C3 power state.
  • the power management logic recognizes a bus master request, the power management logic causes the CPU to transition from a C3 power state back to a high powered C0 power state and generates an interrupt in step 108.
  • Examples of conventional interrupts used in an INTEL® PENTIUM® processor include an Interrupt request (“INTR”) or an active-low system management interrupt (SMI#).
  • INTR Interrupt request
  • SI# active-low system management interrupt
  • the CPU which is now in a full power state re- enables the arbiter allowing the bus master to access the CPU's cache memory in step 112.
  • the CPU also determines whether it can wait for the bus master to complete its transfers in step 116. If the CPU can wait for the bus master to complete its transfers, the CPU waits for completion of the transfers in step 120 and returns to step 104 to disable the arbiter. Disabling the arbiter returns the CPU to the C3 power state in step 106. Otherwise, if the CPU cannot wait for the bus master to complete its transfers, the CPU can be placed in a C2 power state in step 124.
  • the invention relates to a method and apparatus of minimizing power consumption in an electronic system which has a processor with at least three power states including a full power state, a first power conserving state, and a second power conserving state.
  • the method comprises the steps of 1) placing the processor in a first conserving state, wherein the first power conserving state does not allow snooping of a cache memory; 2) detecting a bus master request to use a bus; 3) transitioning the processor directly into a second power conserving state, wherein the second power conserving state allows snooping of the cache; and 4) detecting when snooping of the cache is completed and returning the processor directly to the first power conserving state from the second power conserving state.
  • FIG. 1 is a flow diagram of the prior art method of handling CPU cache requests
  • FIG. 2 illustrates the transitions between processor power states in the ACPI specification as modified by the current invention
  • Figure 3 is a flow diagram of one method of handling CPU cache requests involving transitions from the C3 or deep sleep power state to the C2 power state without powering the CPU to the C0 power state;
  • Figure 4 is one embodiment of a chip implementation for performing the method shown in flow diagram 3;
  • Figure 5 is a second embodiment of a hardware system capable of performing the flow diagram shown in Figure 3.
  • Figure 2 illustrates a modified ACPI processor power state diagram.
  • the diagram includes both traditional transitions between power states and new transitions added by the present invention. All states, the C0 state 204, the Cl state 208, the C2 state 212 and the C3 state 216 are encompassed within a G0 working state 220.
  • a G0 working state is defined by the ACPI specification as a computer state where the system dispatches user mode (application) threads. In the G0 working state, these threads are executed. In this state, devices (peripherals) are dynamically having their power states changed.
  • a processor transitions between various processor power states including the C0 state 204, the Cl state 208, the C2 state 212, and the C3 state 216.
  • the processor is at full power.
  • the Cl state 208 defines a state in which the processor power state has the lowest latency. Aside from putting the processor in a non-executing power state, the Cl state 208 has no other software visible effects.
  • the C2 state is a second non-executing power state which offers improved power savings over the Cl state 208.
  • the C3 power state 216 offers improved savings over both the Cl state 208, and the C2 state 212. While in the C3 state 216, the processor's caches maintain the respective cache states but ignore any snoops. Thus the operating system is responsible for ensuring that the caches maintain coherency.
  • transitions between states occur from the C0 state 204 along path 222 to the Cl state 208 and back to the C0 state along return path 224. Transitions also occur from the C0 state 204 to the C2 state 212 along path 226 and return to the C0 state 204 along path 228. Finally, transitions occur from the C0 state 204 along path 230 to the C3 state 216 and return to the C0 state along path 232. Stopping a clock is one method of generating a transition from the C0 state to the C2 state along path 226. An interrupt will result in a transition of the system from the C2 state 212 along a path 228 to the C0 state 204.
  • a transition from the C0 state 204 along path 230 to the C3 state 216 may be achieved by: 1) asserting a stop clock signal, 2) asserting a sleep signal, and 3) stopping the clocks. An interrupt or request for access will cause the processor to transition from the C3 state 216 along path 232 to the C0 state 204.
  • Applicant's invention adds two more paths along which a processor can transition directly between a C3 state 216 and a C2 state 212.
  • a transition from the C3 state 216 to the C2 state 212 along path 234 can be accomplished by restarting a clock and/or deasserting an optional SLP# signal. It should be noted that it is unnecessary to deassert a stop clock signal (STPCLK#) for this transition. Stopping a clock transitions the processor from a C2 state 212 to a C3 state 216 along path 232. In some processors, an optional sleep signal may also be asserted. In the preferred embodiment of the invention, the STPCLK# on the Intel® PENTIUM® processor does not change while the processor is transitioning directly between the C3 state and the C2 state 212.
  • the C3 power state described in the specification will be equivalent to the lowest power state of a processor and should be considered to be a power state in which a CPU cannot maintain cache coherency. In this lowest power state, bus masters are prevented from accessing memory (because the CPU cannot snoop the cycles).
  • the ACPI C3 power state is equivalent to a stop clock state.
  • the C3 power state is called a sleep or a deep sleep state.
  • the C3 power state is simply defined as a low power state in which cache coherency cannot be maintained, and thus, snooping of the cache memory is not permitted.
  • the ACPI C2 power state is defined generally to be an intermediate power state between full power and the C3 power state.
  • the C2 power state is equivalent to the STOP GRANT state.
  • the C2 power state allows snooping memory accesses and maintaining cache coherency.
  • the C0 power state is defined for purposes of this invention as a full power state in which the CPU carries on its normal functions.
  • Figure 3 illustrates a method by which the bus master and power logic can access the cache of the CPU without raising the CPU to a full power state.
  • the CPU disables the arbiter in step 304 before transitioning into a lowest power or deep sleep C3 power state in step 308.
  • the CPU remains in the C3 power state until a bus master request or interrupt is received in step 309. If an interrupt is received, the processor transitions to a C0 power state in step 310. If instead, a valid bus master request is recognized in step 312, the power management logic (typically a chipset) causes the CPU to transition from the C3 power state to a C2 power state in step 316.
  • the power management logic typically a chipset
  • This transition is usually accomplished by either restarting the CPU clock and/or deasserting the optional SLP# signal to an INTEL® PENTIUM® processor. It should be noted that with an INTEL® PENTIUM® processor, no INTR or SMI# interrupts need to be generated and transmitted to the CPU. Unlike prior systems, the CPU transitions directly from the C3 power state to the C2 power state without first going to the C0 (full power) state.
  • the power management logic chipset enables the memory arbiter in step 320.
  • the memory arbiter may be found in a variety of memory controllers, similar to the one found in the Intel 82430TX. It should be noted that the CPU is not enabling the arbiter because the CPU is in a C2 power state and not executing instructions.
  • the bus master While the CPU is in the C2 power state, the bus master is allowed to access memory. As earlier defined, while the CPU is in a C2 power state (a low power state), the CPU can properly snoop the cycles and maintain cache coherency as done in step 324. After the bus master has completed its access of memory, the power management logic (chipset) detects the end of the bus master request and automatically transitions the CPU back to the C3 or deep sleep state in step 328. Thus, the memory access request issued while the CPU was in its lowest power C3 state did not cause the CPU to transition to the C0 or full power state. By avoiding the transition to the full power C0 state, the CPU saves both power and latency time by avoiding multiple transitions between states.
  • FIG. 4 illustrates one embodiment of the present invention.
  • a CPU 404 including a memory cache 408 is coupled to a memory controller 412 which helps direct flow of information to memory 416.
  • the memory controller 412 is coupled to an ACPI or other power management system 420 via a high speed link 422.
  • the power management logic 420 may include a bus interface, such as a Peripheral Component Interconnect (PCI), which connects a peripheral device 424 via a PCI or other appropriate bus 428.
  • PCI Peripheral Component Interconnect
  • the peripheral 424 may transfer PCI requests to the ACPI power management unit 420 along bus 428.
  • the power management unit 420 respond by transferring grant signals to the peripheral 424 along bus 428.
  • the power management unit 420 also controls a clock generator 432 which clocks other chips in the system, such as the CPU, memory controller and memory.
  • a typical "wake-up" from a C3 power to a C0 power state occurs when a request such as a PCI request is transmitted to the power management unit 420, which responds by switching on the clock generator 432 turning the clocks on.
  • PLL phase lock loop
  • the CPU transitions to a C2 state appropriate for snooping of the cache memory.
  • STPCLK# stop clock
  • an optional sleep signal may also be used.
  • the power management unit 420 enables the clock generator 432 upon receipt of the PCI requests from peripheral 424.
  • the start of the clock generator 432 starts the clocks to the memory controller 412 and the CPU 404.
  • the CPU's stop clock signal (STPCLK#) is not deasserted.
  • STPCLK# stop clock signal
  • a power management unit 420 asserts a grant along PCI bus 428 to the peripheral 424, resulting in a memory cycle which can be snooped by the CPU 404.
  • the power management unit 420 deasserts the PCI grant signal and turns off the clocks to the memory controller 412 and to the CPU 404 by appropriately signaling clock generator 432.
  • Figure 5 shows an alternate system capable of implementing transitions directly from a deep sleep or C3 power state to a C2 or low powered snoop state without taking the CPU to a full power state.
  • the CPU 504 including a cache 508 is connected to a memory controller 512.
  • the memory controller includes a memory arbiter (not shown).
  • the arbiter is coupled to a memory 516.
  • a peripheral 524 such as a PCI peripheral, transmits a request to the memory controller to access memory.
  • the request is routed to the power management unit 528 which in one embodiment may be a variant of the Intel PIIX4 chip.
  • the memory access request indicates to the power management unit 528 that the CPU should exit the C3 or deep sleep state.
  • the power management unit 528 starts a clock generator 532 which starts the clock to the CPU 504.
  • an optional sleep signal may also be triggered to "wake up" the CPU.
  • the stop clock signal is not deasserted.
  • the CPU does not transition to a full power state. Instead, the CPU transitions directly to a C2 power state.
  • a PLL OK signal is transmitted to the memory controller 512 indicating a grant signal may be transmitted from the memory controller to the peripheral 524.
  • the peripheral 524 performs a memory cycle which allows snooping of the cache 508 of CPU 504. When snooping is complete, the memory request from the peripheral 524 goes inactive, the grants are deasserted and the clock to the CPU is turned back off.
  • Both embodiments of the ACPI power management unit, the power management unit 420 of Figure 4 or 528 of Figure 5 allow the CPU to transition from a deep sleep or C3 to an intermediate low power C2 power state without powering all the way back up to the fully powered C0 power state by including logic to start a clock to the CPU when a PCI request is received.

Abstract

Minimizing power consumption of a processor and having at least three power states including a full power state, a first power conserving state, and a second power conserving state. The method involves placing the processor in a first conserving state (308), until a bus master requests snooping of a cache (309). Upon receipt of the request, the processor transitions directly into a second power conserving state (316), wherein the second power conserving state allows snooping of the cache. After snooping of the cache is completed, the processor returns directly to the first power conserving state from the second power conserving state (328).

Description

AUTOMATIC TRANSITIONING BETWEEN ACPI C3 AND C2 STATES
BACKGROUND OF THE INVENTION
1. FIELD OF THE INVENTION
The present invention relates generally to reducing average power consumption by electronic devices. More particularly, the present invention relates to keeping the electronic devices in as low a power state as possible by turning off the electronic devices when various system caches do not need to be snooped.
2. DESCRIPTION OF RELATED ART
In recent years, portable battery operated computing devices have become increasingly popular. Portable computers enable workers and students to have computing power on demand at a variety of locations and not be limited by the power supply of a desktop machine. However, such portable computing devices are frequently limited by the amount of time that they can run on battery power without reconnection to an AC power supply. Thus, engineers are continuously trying to find ways of reducing the power consumption of various components of portable computers, including the central processing unit.
Keeping electronic devices such as a central processing unit, a memory controller or a memory in their lowest possible power state provides a number of benefits. For example, it allows battery operated machines to operate for longer periods of time between recharging. A reduction in power consumption also reduces thermal dissipation by the central processing unit. Reduced thermal dissipation allows the central processing unit to run at full speed for longer periods of time, while remaining within its thermal dissipation specifications. Reduced thermal dissipation also reduces the need for fans and other components used to prevent heat build-up in a computer. Finally, keeping the electronic device in a lower power state than could otherwise be achieved and reducing the number of transitions between power states improves system performance by reducing latencies caused by switching between designated power states. A standard specification used in developing power management systems is the advanced configuration and power interface (ACPI) specification developed jointly by Intel Corporation of Santa Clara, California, Microsoft Corporation of Redmond, Washington and Toshiba Corporation of Tokyo, Japan. The ACPI specification is a key element in an operating system directed power management (OSPM). The goal of ACPI is to enhance power management functionality and robustness, as well as facilitating industry wide implementation of common power management features. The ACPI specification is a publicly available document and can be obtained from the Internet at www//http.teleport.com/~ACPI.
The ACPI defines a number of processor power states which are processor power consumption and thermal management states within a global working state. These processor states include a (i) C0 power state, (ii) Cl power state, (iii) C2 power state, and (iv) C3 power state. In the C0 power state, the processor executes instructions and is at full power. In the Cl and C2 power states, the processor is in a non-executing power state. However, the C2 power state uses less power than the Cl state. In the Cl and C2 power state, the processor still allows the bus to snoop the processor cache memory and thereby maintain cache coherency. The C3 power state offers improved power savings over the Cl and C2 power states. However, while in the C3 power state, the processor cache ignores any snoops. Thus, in the C3 state, the operating software is responsible for ensuring that the processor caches maintain coherency.
The C0, Cl, C2 and C3 power states of the ACPI map into various power states of commercial microprocessors. For example, with an INTEL® PENTIUM® processor, the C0 power state maps into a normal state in which all clocks are running, the C2 power state maps into a STOP GRANT state, and the C3 power state maps into a STOP CLOCK state.
In a traditional system, when a Peripheral Component Interconnect (PCI) peripheral signals that it needs to use the bus, the processor transitions from a C3 power state back to a C0 power state. As the system transitions back to the C0 power state, the central processing unit re-enables a bus arbiter.
A flow chart of a conventional implementation of a bus access is given in Figure 1. Before going to the C3 power state, the central processing unit (CPU) disables an arbiter in step 104. In step 106, the CPU transitions to a C3 power state. When power management logic recognizes a bus master request, the power management logic causes the CPU to transition from a C3 power state back to a high powered C0 power state and generates an interrupt in step 108. Examples of conventional interrupts used in an INTEL® PENTIUM® processor include an Interrupt request ("INTR") or an active-low system management interrupt (SMI#). In the INTR or SMI# handler, the CPU which is now in a full power state re- enables the arbiter allowing the bus master to access the CPU's cache memory in step 112. The CPU also determines whether it can wait for the bus master to complete its transfers in step 116. If the CPU can wait for the bus master to complete its transfers, the CPU waits for completion of the transfers in step 120 and returns to step 104 to disable the arbiter. Disabling the arbiter returns the CPU to the C3 power state in step 106. Otherwise, if the CPU cannot wait for the bus master to complete its transfers, the CPU can be placed in a C2 power state in step 124.
The problem with the current method for handling bus arbiter requests is the unnecessary transition to the high-powered C0 power state. Transition to this power state is necessary in conventional systems to enable the CPU to disable and enable the arbiter in steps 112 and 124. Transitioning to the C0 power state consumes significantly more power than either the C3 or C2 power states. Thus, an improved method for handling bus master requests is needed.
SUMMARY OF THE INVENTION
The invention relates to a method and apparatus of minimizing power consumption in an electronic system which has a processor with at least three power states including a full power state, a first power conserving state, and a second power conserving state. The method comprises the steps of 1) placing the processor in a first conserving state, wherein the first power conserving state does not allow snooping of a cache memory; 2) detecting a bus master request to use a bus; 3) transitioning the processor directly into a second power conserving state, wherein the second power conserving state allows snooping of the cache; and 4) detecting when snooping of the cache is completed and returning the processor directly to the first power conserving state from the second power conserving state.
BRIEF DESCRIPTION OF THE DRAWINGS
The advantages of the present invention will become more readily apparent to those ordinarily skilled in the art after reviewing the following detailed description and accompanying drawings, wherein:
Figure 1 is a flow diagram of the prior art method of handling CPU cache requests;
Figure 2 illustrates the transitions between processor power states in the ACPI specification as modified by the current invention;
Figure 3 is a flow diagram of one method of handling CPU cache requests involving transitions from the C3 or deep sleep power state to the C2 power state without powering the CPU to the C0 power state;
Figure 4 is one embodiment of a chip implementation for performing the method shown in flow diagram 3;
Figure 5 is a second embodiment of a hardware system capable of performing the flow diagram shown in Figure 3.
DETAILED DESCRIPTION OF THE INVENTION
A method and apparatus for conserving power in an electronic device is described. Figure 2 illustrates a modified ACPI processor power state diagram. The diagram includes both traditional transitions between power states and new transitions added by the present invention. All states, the C0 state 204, the Cl state 208, the C2 state 212 and the C3 state 216 are encompassed within a G0 working state 220. A G0 working state is defined by the ACPI specification as a computer state where the system dispatches user mode (application) threads. In the G0 working state, these threads are executed. In this state, devices (peripherals) are dynamically having their power states changed. Within this G0 state, a processor transitions between various processor power states including the C0 state 204, the Cl state 208, the C2 state 212, and the C3 state 216. In the C0 state, the processor is at full power. The Cl state 208 defines a state in which the processor power state has the lowest latency. Aside from putting the processor in a non-executing power state, the Cl state 208 has no other software visible effects. The C2 state is a second non-executing power state which offers improved power savings over the Cl state 208.
The C3 power state 216 offers improved savings over both the Cl state 208, and the C2 state 212. While in the C3 state 216, the processor's caches maintain the respective cache states but ignore any snoops. Thus the operating system is responsible for ensuring that the caches maintain coherency.
In the standard ACPI specification, the transitions between states occur from the C0 state 204 along path 222 to the Cl state 208 and back to the C0 state along return path 224. Transitions also occur from the C0 state 204 to the C2 state 212 along path 226 and return to the C0 state 204 along path 228. Finally, transitions occur from the C0 state 204 along path 230 to the C3 state 216 and return to the C0 state along path 232. Stopping a clock is one method of generating a transition from the C0 state to the C2 state along path 226. An interrupt will result in a transition of the system from the C2 state 212 along a path 228 to the C0 state 204. In some processors, a transition from the C0 state 204 along path 230 to the C3 state 216 may be achieved by: 1) asserting a stop clock signal, 2) asserting a sleep signal, and 3) stopping the clocks. An interrupt or request for access will cause the processor to transition from the C3 state 216 along path 232 to the C0 state 204.
Applicant's invention adds two more paths along which a processor can transition directly between a C3 state 216 and a C2 state 212. By way of example, with an Intel® PENTIUM® family of processors, a transition from the C3 state 216 to the C2 state 212 along path 234 can be accomplished by restarting a clock and/or deasserting an optional SLP# signal. It should be noted that it is unnecessary to deassert a stop clock signal (STPCLK#) for this transition. Stopping a clock transitions the processor from a C2 state 212 to a C3 state 216 along path 232. In some processors, an optional sleep signal may also be asserted. In the preferred embodiment of the invention, the STPCLK# on the Intel® PENTIUM® processor does not change while the processor is transitioning directly between the C3 state and the C2 state 212.
It should be recognized that although the description of this system will be described according to the ACPI specifications power states of C0, Cl, C2 and C3 for convenience, the invention is not limited by the ACPI specification. In general, for embodiments not following the ACPI specification, the C3 power state described in the specification will be equivalent to the lowest power state of a processor and should be considered to be a power state in which a CPU cannot maintain cache coherency. In this lowest power state, bus masters are prevented from accessing memory (because the CPU cannot snoop the cycles). In a system with an INTEL® PENTIUM® processor, the ACPI C3 power state is equivalent to a stop clock state. In some CPUs, the C3 power state is called a sleep or a deep sleep state. For purposes of this invention, the C3 power state is simply defined as a low power state in which cache coherency cannot be maintained, and thus, snooping of the cache memory is not permitted.
For purposes of this invention, the ACPI C2 power state is defined generally to be an intermediate power state between full power and the C3 power state. With an INTEL® PENTIUM® processor, the C2 power state is equivalent to the STOP GRANT state. In general the C2 power state allows snooping memory accesses and maintaining cache coherency. The C0 power state is defined for purposes of this invention as a full power state in which the CPU carries on its normal functions.
Figure 3 illustrates a method by which the bus master and power logic can access the cache of the CPU without raising the CPU to a full power state. In the flow chart of Figure 3, the CPU disables the arbiter in step 304 before transitioning into a lowest power or deep sleep C3 power state in step 308. The CPU remains in the C3 power state until a bus master request or interrupt is received in step 309. If an interrupt is received, the processor transitions to a C0 power state in step 310. If instead, a valid bus master request is recognized in step 312, the power management logic (typically a chipset) causes the CPU to transition from the C3 power state to a C2 power state in step 316. This transition is usually accomplished by either restarting the CPU clock and/or deasserting the optional SLP# signal to an INTEL® PENTIUM® processor. It should be noted that with an INTEL® PENTIUM® processor, no INTR or SMI# interrupts need to be generated and transmitted to the CPU. Unlike prior systems, the CPU transitions directly from the C3 power state to the C2 power state without first going to the C0 (full power) state.
In order to allow bus master accesses, the power management logic chipset enables the memory arbiter in step 320. The memory arbiter may be found in a variety of memory controllers, similar to the one found in the Intel 82430TX. It should be noted that the CPU is not enabling the arbiter because the CPU is in a C2 power state and not executing instructions.
While the CPU is in the C2 power state, the bus master is allowed to access memory. As earlier defined, while the CPU is in a C2 power state (a low power state), the CPU can properly snoop the cycles and maintain cache coherency as done in step 324. After the bus master has completed its access of memory, the power management logic (chipset) detects the end of the bus master request and automatically transitions the CPU back to the C3 or deep sleep state in step 328. Thus, the memory access request issued while the CPU was in its lowest power C3 state did not cause the CPU to transition to the C0 or full power state. By avoiding the transition to the full power C0 state, the CPU saves both power and latency time by avoiding multiple transitions between states.
The above described method of handling bus requests while the CPU is in a very low power or deep sleep state may be accomplished by a variety of different apparatus. Figure 4 illustrates one embodiment of the present invention. A CPU 404 including a memory cache 408 is coupled to a memory controller 412 which helps direct flow of information to memory 416. The memory controller 412 is coupled to an ACPI or other power management system 420 via a high speed link 422. The power management logic 420 may include a bus interface, such as a Peripheral Component Interconnect (PCI), which connects a peripheral device 424 via a PCI or other appropriate bus 428. The peripheral 424 may transfer PCI requests to the ACPI power management unit 420 along bus 428. The power management unit 420 respond by transferring grant signals to the peripheral 424 along bus 428. The power management unit 420 also controls a clock generator 432 which clocks other chips in the system, such as the CPU, memory controller and memory.
A typical "wake-up" from a C3 power to a C0 power state occurs when a request such as a PCI request is transmitted to the power management unit 420, which responds by switching on the clock generator 432 turning the clocks on. Once appropriate delay times have been met, typically phase lock loop ("PLL") spin-up times (locking times), the CPU transitions to a C2 state appropriate for snooping of the cache memory. With an INTEL® PENTIUM® processor, the transition to a full power state (C0) is accomplished by deasserting the stop clock (STPCLK#) signal such that the CPU starts executing instructions. In some processors, an optional sleep signal may also be used.
In the proposed embodiment, the power management unit 420 enables the clock generator 432 upon receipt of the PCI requests from peripheral 424. The start of the clock generator 432 starts the clocks to the memory controller 412 and the CPU 404. However, the CPU's stop clock signal (STPCLK#) is not deasserted. After all of the PLL's have stabilized, a power management unit 420 asserts a grant along PCI bus 428 to the peripheral 424, resulting in a memory cycle which can be snooped by the CPU 404. When the PCI request along PCI bus 428 goes inactive, the power management unit 420 deasserts the PCI grant signal and turns off the clocks to the memory controller 412 and to the CPU 404 by appropriately signaling clock generator 432.
Figure 5 shows an alternate system capable of implementing transitions directly from a deep sleep or C3 power state to a C2 or low powered snoop state without taking the CPU to a full power state. In the implementation shown, the CPU 504 including a cache 508 is connected to a memory controller 512. The memory controller includes a memory arbiter (not shown). The arbiter is coupled to a memory 516. A peripheral 524, such as a PCI peripheral, transmits a request to the memory controller to access memory. The request is routed to the power management unit 528 which in one embodiment may be a variant of the Intel PIIX4 chip. The memory access request indicates to the power management unit 528 that the CPU should exit the C3 or deep sleep state. In response, the power management unit 528 starts a clock generator 532 which starts the clock to the CPU 504. In some CPUs an optional sleep signal may also be triggered to "wake up" the CPU. If CPU 504 is an INTEL® PENTIUM® processor chip, the stop clock signal is not deasserted. Thus, the CPU does not transition to a full power state. Instead, the CPU transitions directly to a C2 power state. When the power management unit 528 determines that the PLL clock has stabilized, a PLL OK signal is transmitted to the memory controller 512 indicating a grant signal may be transmitted from the memory controller to the peripheral 524. The peripheral 524 performs a memory cycle which allows snooping of the cache 508 of CPU 504. When snooping is complete, the memory request from the peripheral 524 goes inactive, the grants are deasserted and the clock to the CPU is turned back off.
Both embodiments of the ACPI power management unit, the power management unit 420 of Figure 4 or 528 of Figure 5 allow the CPU to transition from a deep sleep or C3 to an intermediate low power C2 power state without powering all the way back up to the fully powered C0 power state by including logic to start a clock to the CPU when a PCI request is received.
The present invention described herein may be designed in many different methods and using many different configurations. While the present invention has been described in terms of various embodiments, other embodiments may come to mind to those skilled in the art with departing from the spirit and scope of the present invention. The invention should therefore be measured in terms of the claims which follow.

Claims

What is claimed is:
1. A method of reducing power consumption in an electronic device having a first power conserving state and a second power conserving state, the method comprising the steps of: placing the electronic device in a first power conserving state, said first power conserving state precludes snooping of a memory cache; detecting a request to use a bus; transitioning the electronic device directly from said first power conserving state into said second power conserving state, said second power conserving state allowing snooping of said memory cache; and detecting when snooping of said memory cache is completed and returning said electronic device to said first power conserving state.
2. The method of claim 1 wherein said first power conserving state is a C3 power state and said second power conserving state is a C2 state of an Advanced Configuration and Power Interface specification.
3. The method of claim 1 wherein the transitioning of the electronic device from said first power conserving state to said second power conserving state includes the step of starting a clock which provides a timing signal to the electronic device.
4. The method of claim 3 further comprising the step of: waiting for a phase lock loop spin-up delay before transitioning the electronic device to said second power conserving state; and enabling an arbiter with an enabling circuit wherein the enabling circuit is separate from said central processing unit.
5. The method of claim 1 further comprising the steps of: disabling an arbiter when said snooping of said cache is completed.
6. The method of claim 5 wherein said electronic device is a processor and said disabling step is executed by a second circuit, said second circuit is different from said processor.
7. A power efficient method of determining cache contents of an electronic device having at least three power states including the steps of: recognizing a bus master request and restarting an electronic device clock thereby increasing the electronic device power consumption from a third power state to a second power state; snooping a cache in said electronic device while said electronic device is in said second power state; and returning said electronic device to said third power state immediately upon completion of said snooping of said cache.
8. The method of claim 7 further comprising the step of transmitting a disable signal from a power management logic to a bus arbiter disabling the bus arbiter.
9. The method of claim 8 further comprising the step of: transmitting an enable signal from a power management unit independent of said central processing unit, said enable signal enabling said bus arbiter.
10. A system for minimizing the power consumption of an electronic device, said system comprising: a cache memory in said electronic device, said electronic device having a low power state, an intermediate power state and a high power state; a bus master which transmits a bus access request; and a power management logic independent of said electronic device, said power management logic receives the bus master request and raises said electronic device from the low power state directly to the intermediate power state, said power management logic enabling a bus arbiter until the transfer of information from said bus master request has been completed.
11. The system of claim 10 further comprising: an external clock which is switched on by said power management logic, the switching of said external clock raises said electronic device from the low power state to the intermediate power state.
12. The system of claim 10 wherein said power management unit deasserts a SLP# signal to move said electronic device from said high power state to the intermediate power state.
13. The system of claim 10 wherein said electronic device is a memory controller.
14. The system of claim 10 wherein said electronic device is a central processing unit.
15. The system of claim 14 wherein said power management unit includes a second central processing unit coupled to said power management unit, said second central processing unit clocked by said external clock and transitioning between a plurality of power states based on signals from said power logic unit.
16. The system of claim 14 wherein said low power state is a stop clock state of said central processing unit and said intermediate power state is a stop grant state of said central processing unit.
17. The system of claim 11 wherein said low power state is a C3 state and said intermediate state is a C2 state in a electronic device following the advanced configuration power interface specification.
18. A system for reducing the power consumption of a processing unit said system comprising: means for storing information in said processing unit, said processing unit capable of operating in a plurality of power states including a low power state, an intermediate power state, and a full power state; means for controlling the power state of said processing unit; means for generating a bus access request, said means for generating a bus access request coupled to said means for controlling the power state of said processing unit, said means for controlling the power state of said processing unit transitions said processing unit from said low power state directly to said intermediate power state upon receipt of said bus access request and transitions said processing unit directly to said low power state upon completion of a bus access corresponding to said bus access request.
19. The system of claim 18 wherein said transition from said low power state to said intermediate power state is executed by restarting a clock.
20. The system of claim 18 wherein said restarting of said clock involves coupling an external clock to said processing unit.
21. A computer system comprising: a power supply which provides power; a processor coupled to said power supply and powered by said power supply, said processor including at least three power states, a deep sleep state, an intermediate power state and a full power state, and a power management logic coupled to said processor, said power management logic causing said processor to transition directly to an intermediate power state from the deep sleep state when a request to snoop the central processing unit is received.
22. The system of claim 21 wherein said power supply is a battery.
PCT/US1998/001907 1997-03-31 1998-02-02 Automatic transitioning between acpi c3 and c2 states WO1998044405A1 (en)

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