WO1998048525A2 - An arrangement in a subscriber line interface circuit - Google Patents

An arrangement in a subscriber line interface circuit Download PDF

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Publication number
WO1998048525A2
WO1998048525A2 PCT/SE1998/000722 SE9800722W WO9848525A2 WO 1998048525 A2 WO1998048525 A2 WO 1998048525A2 SE 9800722 W SE9800722 W SE 9800722W WO 9848525 A2 WO9848525 A2 WO 9848525A2
Authority
WO
WIPO (PCT)
Prior art keywords
voltage
capacitor
sawtooth wave
wire
line
Prior art date
Application number
PCT/SE1998/000722
Other languages
French (fr)
Other versions
WO1998048525A3 (en
Inventor
Anders Emericks
Henrik Hellberg
Mattias Israelsson
Carl-Henrik Malmgren
Original Assignee
Telefonaktiebolaget Lm Ericsson
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Telefonaktiebolaget Lm Ericsson filed Critical Telefonaktiebolaget Lm Ericsson
Priority to KR10-1999-7009674A priority Critical patent/KR100520026B1/en
Priority to EP98917930A priority patent/EP0978169B1/en
Priority to JP54560498A priority patent/JP2001521714A/en
Priority to AU70960/98A priority patent/AU7096098A/en
Priority to DE69830580T priority patent/DE69830580T2/en
Priority to CA002288907A priority patent/CA2288907A1/en
Publication of WO1998048525A2 publication Critical patent/WO1998048525A2/en
Publication of WO1998048525A3 publication Critical patent/WO1998048525A3/en

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Classifications

    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R19/00—Arrangements for measuring currents or voltages or for indicating presence or sign thereof
    • G01R19/25—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques
    • G01R19/252—Arrangements for measuring currents or voltages or for indicating presence or sign thereof using digital measurement techniques using analogue/digital converters of the type with conversion of voltage or current into frequency and measuring of this frequency
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/46—Monitoring; Testing
    • G—PHYSICS
    • G01—MEASURING; TESTING
    • G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
    • G01R15/00—Details of measuring arrangements of the types provided for in groups G01R17/00 - G01R29/00, G01R33/00 - G01R33/26 or G01R35/00
    • G01R15/14—Adaptations providing voltage or current isolation, e.g. for high-voltage or high-current networks
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/02—Generators characterised by the type of circuit or by the means used for producing pulses
    • H03K3/021—Generators characterised by the type of circuit or by the means used for producing pulses by the use, as active elements, of more than one type of element or means, e.g. BIMOS, composite devices such as IGBT
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04B—TRANSMISSION
    • H04B3/00—Line transmission systems
    • H04B3/02—Details
    • H04B3/46—Monitoring; Testing
    • H04B3/48—Testing attenuation
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/24—Arrangements for testing

Definitions

  • the invention relates generally to subscriber line interface circuits and, more specifically, to an arrangement for determining the line voltage in a subscriber line interface circuit.
  • One way of estimating the length of the line is to measure the line voltage, i.e. the voltage that appears across the line and the telephone set when a connection is established.
  • the object of the invention is to bring about an arrangement in a subscriber line interface circuit for generating a signal for determining the line voltage without occupying the microprocessor unnecessarily. This is attained by means of the arrangement in accordance with the invention in that a sawtooth wave having an amplitude corresponding to the difference between a first and a second voltage, e.g. the voltages of the A- wire and the B-wire, respectively, is generated and, in its rum, converted to a pulse train related to the line voltage.
  • the pulse train is related to the line voltage by its pulse repetiton frequency and/or by its mark-space ratio.
  • these different relationships offer different advantages.
  • by generating a continuous pulse train and measuring its pulse repetition frequency and/or its mark-space ratio it will be possible to freely choose the measurement period.
  • a greater flexibility is obtained in accordance with the invention.
  • Fig. 1 schematically illustrates a first embodiment of an arrangement according to the invention
  • FIGs. 1A and IB illustrate signals appearing in the embodiment according to Fig. 1
  • FIG. 2 schematically illustrates a second embodiment of an arrangement according to the invention, based on the arrangement illustrated in Fig. 1,
  • Figs. 2A, 2B, 2C and 2D illustrate signals appearing in the embodiment illustrated in Fig. 2,
  • Fig. 3 schematically illustrates a third embodiment of an arrangement according to the invention.
  • Figs. 3 A and 3B illustrate signals appearing in the embodiment according to Fig. 3.
  • Fig. 1 illustrates a first embodiment of an arrangement according to the invention for generating a signal for determining the line voltage in a subscriber line interface circuit connected to a telephone line having a high potential wire and a low potential wire.
  • the high potential wire or A-wire (not shown) is connected to a terminal 1, while the low potential wire or B-wire is connected to a terminal 2.
  • the terminal 1 is connected to the (+)-input terminal of a comparator 3, while the terminal 2 is connected to the (-)-input te ⁇ ninal of a comparator 4.
  • the (-)-input terminal of the comparator 3 and the (+)-input terminal of the comparator 4 are interconnected and the interconnection point is connected to a node 5.
  • a capacitor 6 is interconnected between the node 5 and ground GND.
  • the switching element of a voltage-controlled switch 7 is connected to the node 5 and controlled to switch between its upper and lower position by means of a signal from the output terminal 0 of a bistable circuit 8 whose output terminal Q constitutes the output te ⁇ ninal 9 of the arrangement shown in Fig. 1.
  • the output te ⁇ ninal 9 may be connected to a microprocessor (not shown), common to a plurality of subscriber line interface circuits.
  • the inverted set input te ⁇ ninal S of the bistable circuit 8 is connected to the output terminal of the comparator 3, while the inverted reset input terminal R of the bistable circuit 8 is connected to the output terminal of the comparator 4.
  • the switching element of the switch 7 connects a first cu ⁇ ent generator 10 to the node 5 for charging the capacitor 6 as indicated by an a ⁇ ow, while in its lower position, the switching element of the switch 7 connects a second cu ⁇ ent generator 11 to the node 5 for discharging the capacitor 6 as indicated by an a ⁇ ow.
  • the cu ⁇ ent generators 10 and 11 are interconnected between ground GND and the upper and lower terminals, respectively, of the switch 7.
  • the cu ⁇ ent generators 10 and 1 1 may generate cu ⁇ ents of identical or different values.
  • the voltage across the capacitor 6, i.e. in the node 5 is of a value between the voltage VI on the A- wire connected to the terminal 1 and the voltage V2 on the B-wire connected to the terminal 2.
  • the output signal from the comparator 3 as well as from the comparator 4 will be a logic " 1". These signals will not affect the bistable circuit 8.
  • the bistable circuit 8 is supposed to have a logic " 1" on its output terminal Q and a logic "0" on its inverting output O .
  • the switching element of the switch 7 will then be in its lower position (not shown) in which the cu ⁇ ent from the cu ⁇ ent generator 11 will discharge the capacitor 7 at a constant rate.
  • the capacitor 6 will be charged at a constant rate until its voltage exceeds the voltage on the A-wire connected to the te ⁇ ninal 1. Then the comparator 3 will switch its output signal, setting the bistable circuit 8 which again via the switch 7 connects the cu ⁇ ent generator 11 to the node 5.
  • the amplitude of the sawtooth wave shown in Fig. 1A will be equal to the line voltage, i.e. the voltage V1-V2 between the input terminals 1 and 2.
  • the capacitance of the capacitor 6 as well as the values of the constant cu ⁇ ents supplied by the cu ⁇ ent generators 10 and 1 1, are known. Since the capacitor 6 is charged and discharged, respectively, by these constant cu ⁇ ents between voltages depending on the line voltage, the line voltage can easily be determined from the pulse repetition frequency of the pulse train in Fig. IB by means of the microprocessor connected to the ourput terminal 9. The pulse repetition frequency of the pulse train on the terminal 9, as illustrated in Fig. IB, will be inversely proportional to the line voltage.
  • a monostable circuit (not shown) may be connected to the output terminal 9 to convert the pulses of the pulse train to pulses of equal width.
  • the pulse repetition frequency will be inversely proportional to the line voltage.
  • the mean value of the output voltage will be inversely proportional to the line voltage.
  • the mean value is easily extracted by lowpass filtering.
  • Fig. 2 resembles to some extent the embodiment as shown in Fig. 1 as will be apparent from the below description.
  • a capacitor 12 co ⁇ esponding to the capacitor 6 in Fig. 1 is charged and discharged between a first reference voltage VREF 1 applied to an input terminal 13, and a second reference voltage VREF2 applied to a input terminal 14.
  • the terminal 13 is connected to the (+)-input terminal of a comparator 15, while the terminal 14 is connected to the (-)-input terminal of a comparator 16 co ⁇ esponding to the comparators 3 and 4, respectively, in Fig. 1.
  • the (-)-input te ⁇ ninal of the comparator 5 and the (+)-input terminal of the comparator 16 are interconnected and the interconnection point is connected to a node 17.
  • the capacitor 12 is interconnected between the node 17 and ground GND.
  • the node 17 is also connected to the switching element of a voltage-controlled switch 18 which as in the embodiment in Fig. 1, is controlled between its upper and lower position from the output terminal 0 of a bistable circuit 19. In this embodiment, the output terminal Q of the bistable circuital 9 is not used.
  • the input terminals S and R of the bistable circuit 19 are connected to the output terminals of the comparators 15 and 16, respectively.
  • the switching element of the switch 18 In its upper position, the switching element of the switch 18 connects a first current generator 20 to the node 17 for charging the capacitor 12 as indicated by an arrow, while in its lower position, the switching element of the switch 18 connects a second cu ⁇ ent generator 21 to the node 17 for discharging the capacitor 12 as indicated by an a ⁇ ow.
  • the capacitor 12 will be charged and discharged between the voltages VREFl and VREF2, respectively, as illustrated in Fig. 2A where the upper line co ⁇ esponds to the VREFl and the lower line co ⁇ esponds to the voltage VREF2 as indicated.
  • the high potential wire, i.e. the A-wire, of the telephone line is supposed to be connected to a terminal 22, while the low potential wire, i.e. the B-wire, is supposed to be connected to a terminal 23.
  • the terminal 22 is connected to the (+)-input te ⁇ ninal of a comparator 24, while the terminal 23 is connected to the (-)-input terminal of a comparator 25.
  • the (-)-input terminal of the comparator 24 and the (+)-input terminal of the comparator 25 are interconnected and the interconnection point is connected to the node 17.
  • the output terminal 26 of the comparator 24 and the output terminal 27 of the comparator 25 are connected to the respective input terminals of an NAND-circuit 28 whose output terminal constitutes the output terminal 29 of the embodiment in accordance with Fig. 2.
  • V22 the voltage on the A-wire connected to the terminal 22
  • V23 the voltage on the B-wire connected to the terminal 23
  • the output voltage V26 of the comparator 24 will be low when the voltage across the capacitor 12 exceeds the A-wire voltage V22, and high when the capacitor 12 voltage is below the A-wire voltage V22.
  • the output voltage V27 of the comparator 25 as illustrated in Fig. 2C will be high as long as the voltage across the capacitor 12 is above the B-wire voltage V23, and low as long as the voltage across the capacitor 12 is below the B-wire voltage V23.
  • This output signal denoted V29, will appear on the output te ⁇ ninal 29 of the a ⁇ angement in Fig. 2.
  • the pulse train appearing on the output terminal 29 will have a fixed pulse repetition frequency. This is due to the fact that the capacitor 12 is charged and discharged between two constant voltages VREFl and VREF2 by means of constant cu ⁇ ents.
  • the mark-space ratio of the pulse train will be proportional to the ratio between the line voltage and the difference between the reference voltages VREFl and VREF2 applied to the terminals 13 and 14, respectively.
  • the advantage of the embodiment according to Fig. 2 is that the mean value of the output pulse train voltage will be proportional to the line voltage if VREFl and VREF2 are fixed. This mean value is easily extracted by means of lowpass filtering. In applications including an analog-to-digital converter, this embodiment may be preferable.
  • Fig. 3 illustrates a third embodiment of the invention.
  • a capacitor 30 is charged and discharged between reference voltages VREF3 and VREF4.
  • the reference voltage VREF3 is applied to an input terminal 31, while the reference voltage VREF4 is applied to an input te ⁇ ninal 32.
  • the terminal 3 1 is connected to the (+)-input te ⁇ ninal of a comparator 33, while the te ⁇ ninal 32 is connected to the (-)-input terminal of a comparator 34.
  • the (-)-input terminal of the comparator 33 and the (+)-input terminal of the comparator 34 are interconnected and the interconnection point is connected to a node 35.
  • the capacitor 30 is interconnected between the node 35 and ground GND.
  • the node 35 is also connected to the switching element of a voltage-controlled switch 36 which as in the embodiment in Fig. 1, is controlled between its upper and lower position from the output te ⁇ ninal 0 of a bistable circuit 37 whose output terminal Q constitutes the output te ⁇ ninal 38 of the a ⁇ angement shown in Fig. 3.
  • the input terminals S and R of the bistable circuit 37 are connected to the output terminals of the comparators 33 and 34, respectively.
  • the switching element of the switch 36 In its upper position, the switching element of the switch 36 connects a first cu ⁇ ent generator 39 to the node 36 for charging the capacitor 30 as indicated by an a ⁇ ow, while in its lower position, the switching element of the switch 36 connects a second cu ⁇ ent generator 40 to the node 30 for discharging the capacitor 30 as indicated by an a ⁇ ow.
  • the high potential wire, i.e. the A-wire, of the telephone line is supposed to be connected to a terminal 41, while the low potential wire, i.e. the B-wire, is supposed to be connected to a te ⁇ ninal 42.
  • the terminals 41 and 42 i.e. the A-wire and the B-wire, are connected to control input terminals 43 and 44 of the cu ⁇ ent generators 39 and 40 to control these cu ⁇ ent generators to generate cu ⁇ ents in response to the line voltage, i.e. the voltage between the terminals 41 and 42 or the A-wire and the B-wire.
  • the capacitor 30 will be charged and discharged between the constant voltages VREF3 and VREF4, respectively, as illustrated in Fig. 3 A, by means of cu ⁇ ents that are proportional to the line voltage.
  • the resulting pulse train appearing on the output terminal 38, as illustrated in Fig. 3B, will have a pulse repetition frequency which is proportional to the line voltage.
  • a monostable circuit may be connected to the output terminal 38 to convert the pulses of the pulse train to pulses of equal width.
  • the output signal will contain information about the line voltage both in its pulse repetition frequency and its mean value.

Abstract

In a subscriber line interface circuit connected to a telephone line having a high potential wire and a low potential wire, an arrangement for generating a signal for determining the line voltage comprises means (7, 10, 11) for alternately charging a capacitor (6), by means of a first DC current, to a first voltage, and discharging the capacitor (6), by means of a second DC current, to a second voltage. Hereby, a sawtooth wave having an amplitude corresponding to the difference between the first and second voltages is produced. This sawtooth wave is converted to a pulse train related to the line voltage, from which the line voltage can be determined.

Description

AN ARRANGEMENT IN A SUBSCRIBER LINE INTERFACE CIRCUIT
TECHNICAL FIELD
The invention relates generally to subscriber line interface circuits and, more specifically, to an arrangement for determining the line voltage in a subscriber line interface circuit.
BACKGROUND OF THE INVENTION
To be able to adjust hybrid interface parameters and gain in a telephone circuit by means of a microprocessor on a line interface board in order to obtain good echo cancellation for telephone lines of different lengths as well as for certain test purposes, it is necessary to know the length of the respective telephone line.
One way of estimating the length of the line is to measure the line voltage, i.e. the voltage that appears across the line and the telephone set when a connection is established.
It is known to generate a pulse having a length corresponding to the line voltage. To get information about the line voltage, the length of this pulse is then measured by the microprocessor on the line interface board.
When a pulse length is to be measured, it is difficult to get at good resolution since the measurement period will be determined by the pulse length. The instruction cycle of the microprocessor has to be short relative to the shortest pulse length of interest and, moreover, the microprocessor cannot do anything else during that time.
SUMMARY OF THE INVENTION
The object of the invention is to bring about an arrangement in a subscriber line interface circuit for generating a signal for determining the line voltage without occupying the microprocessor unnecessarily. This is attained by means of the arrangement in accordance with the invention in that a sawtooth wave having an amplitude corresponding to the difference between a first and a second voltage, e.g. the voltages of the A- wire and the B-wire, respectively, is generated and, in its rum, converted to a pulse train related to the line voltage.
In accordance with the invention, the pulse train is related to the line voltage by its pulse repetiton frequency and/or by its mark-space ratio. Depending upon the actual application, these different relationships offer different advantages. Generally, by generating a continuous pulse train and measuring its pulse repetition frequency and/or its mark-space ratio, it will be possible to freely choose the measurement period. Thus, a greater flexibility is obtained in accordance with the invention.
BRIEF DESCRIPTION OF THE DRAWING The invention will be described more in detail below with reference to the appended drawing, on which
Fig. 1 schematically illustrates a first embodiment of an arrangement according to the invention,
Figs. 1A and IB illustrate signals appearing in the embodiment according to Fig. 1, Fig. 2 schematically illustrates a second embodiment of an arrangement according to the invention, based on the arrangement illustrated in Fig. 1,
Figs. 2A, 2B, 2C and 2D illustrate signals appearing in the embodiment illustrated in Fig. 2,
Fig. 3 schematically illustrates a third embodiment of an arrangement according to the invention, and
Figs. 3 A and 3B illustrate signals appearing in the embodiment according to Fig. 3.
PREFERRED EMBODIMENTS
Fig. 1 illustrates a first embodiment of an arrangement according to the invention for generating a signal for determining the line voltage in a subscriber line interface circuit connected to a telephone line having a high potential wire and a low potential wire.
In the arrangement in Fig. 1, the high potential wire or A-wire (not shown) is connected to a terminal 1, while the low potential wire or B-wire is connected to a terminal 2.
The terminal 1 is connected to the (+)-input terminal of a comparator 3, while the terminal 2 is connected to the (-)-input teπninal of a comparator 4. The (-)-input terminal of the comparator 3 and the (+)-input terminal of the comparator 4 are interconnected and the interconnection point is connected to a node 5. A capacitor 6 is interconnected between the node 5 and ground GND.
The switching element of a voltage-controlled switch 7 is connected to the node 5 and controlled to switch between its upper and lower position by means of a signal from the output terminal 0 of a bistable circuit 8 whose output terminal Q constitutes the output teπninal 9 of the arrangement shown in Fig. 1. The output teπninal 9 may be connected to a microprocessor (not shown), common to a plurality of subscriber line interface circuits.
The inverted set input teπninal S of the bistable circuit 8 is connected to the output terminal of the comparator 3, while the inverted reset input terminal R of the bistable circuit 8 is connected to the output terminal of the comparator 4.
In its upper position, as illustrated in Fig. 1, the switching element of the switch 7 connects a first cuπent generator 10 to the node 5 for charging the capacitor 6 as indicated by an aπow, while in its lower position, the switching element of the switch 7 connects a second cuπent generator 11 to the node 5 for discharging the capacitor 6 as indicated by an aπow. The cuπent generators 10 and 11 are interconnected between ground GND and the upper and lower terminals, respectively, of the switch 7. The cuπent generators 10 and 1 1 may generate cuπents of identical or different values.
The operation of the embodiment illustrated in Fig. 1 will now be described.
Suppose that the voltage across the capacitor 6, i.e. in the node 5, is of a value between the voltage VI on the A- wire connected to the terminal 1 and the voltage V2 on the B-wire connected to the terminal 2.
Under this condition, the output signal from the comparator 3 as well as from the comparator 4 will be a logic " 1". These signals will not affect the bistable circuit 8. The bistable circuit 8 is supposed to have a logic " 1" on its output terminal Q and a logic "0" on its inverting output O . The switching element of the switch 7 will then be in its lower position (not shown) in which the cuπent from the cuπent generator 11 will discharge the capacitor 7 at a constant rate.
When the voltage across the capacitor 6, i.e. the voltage in the node 5, goes below the voltage on the B-wire connected to the terminal 2, the output signal from the comparator 4 will switch to a logic "0" which will reset the bistable circuit 8. Then, the output 0 will go low, while the output O goes high. This causes the switching element of the switch 7 to switch to its upper position, connecting the cuπent generator 10 to the node 5.
Now, the capacitor 6 will be charged at a constant rate until its voltage exceeds the voltage on the A-wire connected to the teπninal 1. Then the comparator 3 will switch its output signal, setting the bistable circuit 8 which again via the switch 7 connects the cuπent generator 11 to the node 5.
This operating cycle is repeated as long as the connection is kept active. Consequently, the voltage in the node 5 will be a sawtooth wave as illustrated in Fig. 1A, while the output signal on the output terminal 9 will be a square-wave pulse train as illustrated in Fig. IB.
The amplitude of the sawtooth wave shown in Fig. 1A will be equal to the line voltage, i.e. the voltage V1-V2 between the input terminals 1 and 2.
The capacitance of the capacitor 6 as well as the values of the constant cuπents supplied by the cuπent generators 10 and 1 1, are known. Since the capacitor 6 is charged and discharged, respectively, by these constant cuπents between voltages depending on the line voltage, the line voltage can easily be determined from the pulse repetition frequency of the pulse train in Fig. IB by means of the microprocessor connected to the ourput terminal 9. The pulse repetition frequency of the pulse train on the terminal 9, as illustrated in Fig. IB, will be inversely proportional to the line voltage.
A monostable circuit (not shown) may be connected to the output terminal 9 to convert the pulses of the pulse train to pulses of equal width.
The advantage of such an embodiment is that it will be possible to extract line length information in two different ways:
On the one hand, as before, the pulse repetition frequency will be inversely proportional to the line voltage.
On the other hand, the mean value of the output voltage will be inversely proportional to the line voltage. The mean value is easily extracted by lowpass filtering.
Thus, such an embodiment gives an output signal that can be read directly by the microprocessor as a frequency or by an analog-to-digital converter. The operation of a second embodiment of the aπangement according to the invention will now be described with reference to Fig. 2.
The embodiment according to Fig. 2 resembles to some extent the embodiment as shown in Fig. 1 as will be apparent from the below description.
In the embodiment according to Fig. 2, a capacitor 12 coπesponding to the capacitor 6 in Fig. 1, is charged and discharged between a first reference voltage VREF 1 applied to an input terminal 13, and a second reference voltage VREF2 applied to a input terminal 14. The terminal 13 is connected to the (+)-input terminal of a comparator 15, while the terminal 14 is connected to the (-)-input terminal of a comparator 16 coπesponding to the comparators 3 and 4, respectively, in Fig. 1.
The (-)-input teπninal of the comparator 5 and the (+)-input terminal of the comparator 16 are interconnected and the interconnection point is connected to a node 17. The capacitor 12 is interconnected between the node 17 and ground GND.
The node 17 is also connected to the switching element of a voltage-controlled switch 18 which as in the embodiment in Fig. 1, is controlled between its upper and lower position from the output terminal 0 of a bistable circuit 19. In this embodiment, the output terminal Q of the bistable circuital 9 is not used.
In the same manner as in the embodiment in Fig. 1, the input terminals S and R of the bistable circuit 19 are connected to the output terminals of the comparators 15 and 16, respectively.
In its upper position, the switching element of the switch 18 connects a first current generator 20 to the node 17 for charging the capacitor 12 as indicated by an arrow, while in its lower position, the switching element of the switch 18 connects a second cuπent generator 21 to the node 17 for discharging the capacitor 12 as indicated by an aπow.
Thus, the capacitor 12 will be charged and discharged between the voltages VREFl and VREF2, respectively, as illustrated in Fig. 2A where the upper line coπesponds to the VREFl and the lower line coπesponds to the voltage VREF2 as indicated.
In the embodiment according to Fig. 2, the high potential wire, i.e. the A-wire, of the telephone line is supposed to be connected to a terminal 22, while the low potential wire, i.e. the B-wire, is supposed to be connected to a terminal 23.
The terminal 22 is connected to the (+)-input teπninal of a comparator 24, while the terminal 23 is connected to the (-)-input terminal of a comparator 25. The (-)-input terminal of the comparator 24 and the (+)-input terminal of the comparator 25 are interconnected and the interconnection point is connected to the node 17.
The output terminal 26 of the comparator 24 and the output terminal 27 of the comparator 25 are connected to the respective input terminals of an NAND-circuit 28 whose output terminal constitutes the output terminal 29 of the embodiment in accordance with Fig. 2.
In Fig. 2A, the voltage on the A-wire connected to the terminal 22 is denoted V22, while the voltage on the B-wire connected to the terminal 23, is denoted V23.
As apparent from Fig. 2B illustrating the output signal from the comparator 24, the output voltage V26 of the comparator 24 will be low when the voltage across the capacitor 12 exceeds the A-wire voltage V22, and high when the capacitor 12 voltage is below the A-wire voltage V22. The output voltage V27 of the comparator 25 as illustrated in Fig. 2C will be high as long as the voltage across the capacitor 12 is above the B-wire voltage V23, and low as long as the voltage across the capacitor 12 is below the B-wire voltage V23.
Supplying the signals V26 and V27 to the input terminals of the NAND circuit 28 will result in an output signal from the NAND circuit 28 as illustrated in Fig. 2D.
This output signal, denoted V29, will appear on the output teπninal 29 of the aπangement in Fig. 2.
As apparent, the pulse train appearing on the output terminal 29 will have a fixed pulse repetition frequency. This is due to the fact that the capacitor 12 is charged and discharged between two constant voltages VREFl and VREF2 by means of constant cuπents. The mark-space ratio of the pulse train will be proportional to the ratio between the line voltage and the difference between the reference voltages VREFl and VREF2 applied to the terminals 13 and 14, respectively.
The advantage of the embodiment according to Fig. 2 is that the mean value of the output pulse train voltage will be proportional to the line voltage if VREFl and VREF2 are fixed. This mean value is easily extracted by means of lowpass filtering. In applications including an analog-to-digital converter, this embodiment may be preferable.
Thus, also in this second embodiment, a pulse train related to the line voltage will be generated.
Fig. 3 illustrates a third embodiment of the invention.
In the embodiment according to Fig. 3, a capacitor 30 is charged and discharged between reference voltages VREF3 and VREF4. The reference voltage VREF3 is applied to an input terminal 31, while the reference voltage VREF4 is applied to an input teπninal 32. The terminal 3 1 is connected to the (+)-input teπninal of a comparator 33, while the teπninal 32 is connected to the (-)-input terminal of a comparator 34.
The (-)-input terminal of the comparator 33 and the (+)-input terminal of the comparator 34 are interconnected and the interconnection point is connected to a node 35. The capacitor 30 is interconnected between the node 35 and ground GND.
The node 35 is also connected to the switching element of a voltage-controlled switch 36 which as in the embodiment in Fig. 1, is controlled between its upper and lower position from the output teπninal 0 of a bistable circuit 37 whose output terminal Q constitutes the output teπninal 38 of the aπangement shown in Fig. 3.
In the same manner as in the embodiment in Fig. 1, the input terminals S and R of the bistable circuit 37 are connected to the output terminals of the comparators 33 and 34, respectively.
In its upper position, the switching element of the switch 36 connects a first cuπent generator 39 to the node 36 for charging the capacitor 30 as indicated by an aπow, while in its lower position, the switching element of the switch 36 connects a second cuπent generator 40 to the node 30 for discharging the capacitor 30 as indicated by an aπow.
In the embodiment according to Fig. 3, the high potential wire, i.e. the A-wire, of the telephone line is supposed to be connected to a terminal 41, while the low potential wire, i.e. the B-wire, is supposed to be connected to a teπninal 42.
The terminals 41 and 42, i.e. the A-wire and the B-wire, are connected to control input terminals 43 and 44 of the cuπent generators 39 and 40 to control these cuπent generators to generate cuπents in response to the line voltage, i.e. the voltage between the terminals 41 and 42 or the A-wire and the B-wire. Thus, the capacitor 30 will be charged and discharged between the constant voltages VREF3 and VREF4, respectively, as illustrated in Fig. 3 A, by means of cuπents that are proportional to the line voltage.
The resulting pulse train appearing on the output terminal 38, as illustrated in Fig. 3B, will have a pulse repetition frequency which is proportional to the line voltage.
As above, a monostable circuit may be connected to the output terminal 38 to convert the pulses of the pulse train to pulses of equal width. Thus, the output signal will contain information about the line voltage both in its pulse repetition frequency and its mean value.

Claims

1. In a subscriber line interface circuit connected to a telephone line having a high potential wire and a low potential wire, an aπangement for generating a signal for determining the line voltage, characterized by
- means (7, 10, 11; 18, 20, 21; 36, 39, 40 ) for alternately charging a capacitor (6; 12; 30), by means of a first DC cuπent, to a first voltage, and discharging the capacitor (6; 12; 30), by means of a second DC cuπent, to a second voltage to produce a sawtooth wave having an amplitude coπesponding to the difference between the fust and second voltages, and
- means (3, 4, 8; 15, 16, 19, 24, 25, 28; 33, 34, 37) for converting the sawtooth wave to a pulse train related to the line voltage.
2. The aπangement according to claim 1, characterized in - that the first voltage coπesponds to the potential (VI) of the high potential wire,
- that the second voltage coπesponds to the potential (V2) of the low potential wire, and
- that said means (3, 4, 8) for converting the sawtooth wave is adapted to convert the sawtooth wave to a pulse train having a pulse repetition frequency which is inversely proportional to the line voltage.
3. The aπangement according to claim 1, characterized in
- that said means (36, 39, 40) for alternately charging a capacitor (30) are adpated to generate the first and second DC cuπents in response to the voltage difference between the high potential wire and the low potential wire, and
- that said means (33, 34, 37) for converting the sawtooth wave is adapted to convert the sawtooth wave to a pulse train having a pulse repetition frequency which is proportional to the line voltage.
4. The aπangement as claimed in claim 2 or 3, characterized in that it comprises means for converting the pulses of the pulse train to pulses of equal width.
5. The aπangement according to claim 1, characterized in
- that the first voltage coπesponds to a higher potential (VREFl) than the potential (V22) of the high potential wire, - that the second voltage coπesponds to a lower potential (VREF2) than the potential (V23) of the low potential wire, and
- that said means (15, 16, 19, 24, 25, 28) for converting the sawtooth wave is adapted to convert the sawtooth wave to a pulse train having a fixed pulse repetition frequency, and a mark-space ratio which is proportional to the ratio between the line voltage and the difference between the first and second voltages.
6. In a subscriber line interface circuit connected to a telephone line having a high potential wire and a low potential wire, a method of generating a signal for determining the line voltage, characterized by - alternately charging a capacitor (6; 12; 30) to a first voltage by means of a first DC current, and discharging the capacitor to a second voltage by means of a second DC current to produce a sawtooth wave having an amplitude coπesponding to the difference between the first and second voltages, and
- converting the sawtooth wave to a pulse train related to the line voltage.
PCT/SE1998/000722 1997-04-23 1998-04-21 An arrangement in a subscriber line interface circuit WO1998048525A2 (en)

Priority Applications (6)

Application Number Priority Date Filing Date Title
KR10-1999-7009674A KR100520026B1 (en) 1997-04-23 1998-04-21 An arrangement in a subscriber line interface circuit
EP98917930A EP0978169B1 (en) 1997-04-23 1998-04-21 An arrangement in a subscriber line interface circuit
JP54560498A JP2001521714A (en) 1997-04-23 1998-04-21 Equipment in the subscriber line interface circuit
AU70960/98A AU7096098A (en) 1997-04-23 1998-04-21 An arrangement in a subscriber line interface circuit
DE69830580T DE69830580T2 (en) 1997-04-23 1998-04-21 AN ARRANGEMENT IN A SUBSCRIBER INTERFACE CIRCUIT
CA002288907A CA2288907A1 (en) 1997-04-23 1998-04-21 An arrangement in a subscriber line interface circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
SE9701524-2 1997-04-23
SE9701524A SE511963C2 (en) 1997-04-23 1997-04-23 Device and method for determining line voltage in a subscriber line circuit

Publications (2)

Publication Number Publication Date
WO1998048525A2 true WO1998048525A2 (en) 1998-10-29
WO1998048525A3 WO1998048525A3 (en) 1999-01-28

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Application Number Title Priority Date Filing Date
PCT/SE1998/000722 WO1998048525A2 (en) 1997-04-23 1998-04-21 An arrangement in a subscriber line interface circuit

Country Status (11)

Country Link
US (1) US6195429B1 (en)
EP (1) EP0978169B1 (en)
JP (1) JP2001521714A (en)
KR (1) KR100520026B1 (en)
CN (1) CN1127815C (en)
AU (1) AU7096098A (en)
CA (1) CA2288907A1 (en)
DE (1) DE69830580T2 (en)
SE (1) SE511963C2 (en)
TW (1) TW347630B (en)
WO (1) WO1998048525A2 (en)

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US8409587B2 (en) 2002-11-01 2013-04-02 Glaxosmithkline Biologicals S.A. Immunogenic composition

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EP2168597A1 (en) 2001-07-26 2010-03-31 Novartis Vaccines and Diagnostics S.r.l. Vaccines comprising aluminium adjuvants and histidine
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EP2266605A1 (en) 2001-07-26 2010-12-29 Novartis Vaccines and Diagnostics S.r.l. Vaccines comprising aluminium adjuvants and histidine
US8409587B2 (en) 2002-11-01 2013-04-02 Glaxosmithkline Biologicals S.A. Immunogenic composition

Also Published As

Publication number Publication date
EP0978169A2 (en) 2000-02-09
JP2001521714A (en) 2001-11-06
DE69830580T2 (en) 2006-05-18
KR20010020127A (en) 2001-03-15
AU7096098A (en) 1998-11-13
SE9701524D0 (en) 1997-04-23
DE69830580D1 (en) 2005-07-21
CN1127815C (en) 2003-11-12
EP0978169B1 (en) 2005-06-15
SE511963C2 (en) 1999-12-20
CN1252909A (en) 2000-05-10
WO1998048525A3 (en) 1999-01-28
TW347630B (en) 1998-12-11
SE9701524L (en) 1998-10-24
KR100520026B1 (en) 2005-10-10
US6195429B1 (en) 2001-02-27
CA2288907A1 (en) 1998-10-29

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