WO1998053492A1 - Mofset in a trench and method of manufacture thereof - Google Patents

Mofset in a trench and method of manufacture thereof Download PDF

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Publication number
WO1998053492A1
WO1998053492A1 PCT/US1998/006138 US9806138W WO9853492A1 WO 1998053492 A1 WO1998053492 A1 WO 1998053492A1 US 9806138 W US9806138 W US 9806138W WO 9853492 A1 WO9853492 A1 WO 9853492A1
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WIPO (PCT)
Prior art keywords
substrate
pillars
trench
forming
regions
Prior art date
Application number
PCT/US1998/006138
Other languages
French (fr)
Inventor
Charles E. May
Robert Dawson
Original Assignee
Advanced Micro Devices, Inc.
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Filing date
Publication date
Application filed by Advanced Micro Devices, Inc. filed Critical Advanced Micro Devices, Inc.
Publication of WO1998053492A1 publication Critical patent/WO1998053492A1/en

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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/417—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions carrying the current to be rectified, amplified or switched
    • H01L29/41725—Source or drain electrodes for field effect devices
    • H01L29/41775—Source or drain electrodes for field effect devices characterised by the proximity or the relative position of the source or drain electrode and the gate electrode, e.g. the source or drain electrode separated from the gate electrode by side-walls or spreading around or above the gate electrode
    • H01L29/41783—Raised source or drain electrodes self aligned with the gate
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66575—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate
    • H01L29/6659—Lateral single gate silicon transistors where the source and drain or source and drain extensions are self-aligned to the sides of the gate with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66621—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation using etching to form a recess at the gate location
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H01L29/66628—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation recessing the gate by forming single crystalline semiconductor material at the source or drain location
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66537—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a self aligned punch through stopper or threshold implant under the gate region

Definitions

  • the present invention is directed generally to semiconductor devices and to a method of manufacture thereof and, more particularly, to fabrication of semiconductor devices having vertically formed active regions.
  • MOS metal- oxide-semiconductor
  • the principal elements of a typical MOS semiconductor device are illustrated in Figure 1.
  • the device generally includes a semiconductor substrate 101 on which a gate electrode 103 is disposed.
  • the gate electrode 103 acts as a conductor.
  • An input signal is typically applied to the gate electrode 103 via a gate terminal (not shown) .
  • Heavily doped source/drain regions 105 are formed within the semiconductor substrate 101 and are connected to source/drain terminals (not shown) .
  • the typical MOS transistor is symmetrical, which means that the source and drain are interchangeable. Whether a region acts as a source or drain depends on the respective applied voltages and the type of device being made (e.g., PMOS, NMOS, etc.).
  • the term source/drain region refers generally to an active region used for the formation of a source or drain.
  • a channel region 107 is formed in the semiconductor substrate 101 beneath the gate electrode 103 and separates the source/drain regions 105.
  • the channel is typically lightly doped with a dopant of a type opposite to that of the source/drain regions 105.
  • the gate electrode 103 is generally separated from the semiconductor substrate 101 by an insulating layer 109, typically an oxide layer such as Si0 2 .
  • the insulating layer 109 is provided to prevent current from flowing between the gate electrode 103 and the source/drain regions 105 or channel region 107.
  • an output voltage is typically developed between the source and drain terminals.
  • a transverse electric field is set up in the channel region 107.
  • By varying the transverse electric field it is possible to modulate the conductance of the channel region 107 between the source region and the drain region. In this manner, an electric field controls the current flow through the channel region
  • MOSFET MOS field-effect-transistor
  • Semiconductor devices like the one described above, are used in large numbers to construct most modern electronic devices. As a larger number of such devices are integrated into a single wafer, improved performance and capabilities of electronic devices can be achieved.
  • the semiconductor devices In order to increase the number of semiconductor devices which may be formed on a given surface area of a substrate, the semiconductor devices must be scaled down (i.e., made smaller). This is typically accomplished by reducing the lateral dimensions of the device structure. Continued efforts to reduce the dimensions of the semiconductor devices encounter problems related to device performance. Thus, there generally exist a tension between desires to further scale down the semiconductor devices and the need to maintain high performance and reliability.
  • a semiconductor device is formed by forming a trench within a substrate.
  • An oxide layer is formed within the trench and portions of the oxide layer are removed to expose one or more portions of the substrate within the trench.
  • a plurality of doped polysilicon pillars are formed within the trench.
  • the doped polysilicon pillars include one or more active region pillars formed on the one or more exposed portions of the substrate.
  • a semiconductor device in accordance with another embodiment of the invention, includes a substrate having a trench formed therein and at least one vertical source/drain region formed within the trench.
  • the vertical source/drain region includes a doped polysilicon pillar as well as a doped region of the substrate.
  • Figure 1 illustrates elements of a typical MOS transistor
  • Figures 2A through 2G illustrate a fabrication process in accordance with an embodiment of the invention
  • FIGS. 3A through 3D illustrate a fabrication process in accordance with another embodiment of the invention
  • FIGS. 4A through 4B illustrate a fabrication process in accordance with still another embodiment of the invention.
  • FIGS. 5A through 5C illustrate a fabrication process in accordance with yet another embodiment of the invention.
  • the present invention is applicable to a number of semiconductor devices.
  • the present invention is believed to be particularly suited to fabrication of MOS transistors having vertically formed active regions. While the present invention is not limited to such devices, an appreciation of various aspects of the invention will be gained through a discussion of various fabrication processes and device characteristics in connection with the examples provided below.
  • FIGs 2A through 2G illustrate a fabrication process in accordance with one particular embodiment of the invention.
  • the fabrication process uses a substrate 201, such as a silicon substrate, on which an isolation oxide 203 has been formed.
  • the isolation oxide 203 is typically on the order of 100 to 300 angstroms (A) .
  • a trench 205 is defined within the substrate 201 as illustrated in Figure 2B.
  • the trench 205 may be formed, for example, using conventional lithographic and etching techniques to a depth on the order of 1500 to 2000 A.
  • An oxide layer 207 is formed within the trench 205. Portions of the oxide layer 207 within the trench 205 are removed to expose portions of the substrate 209. The resultant structure is illustrated in Figure 2C.
  • the oxide layer may be formed and removed using, for example, well-known deposition and etching techniques.
  • the oxide thickness may range for example, from 30 to 60 A.
  • the oxide layer 207 will be used to form a gate oxide to insulate a gate electrode from the substrate.
  • a relatively thick polysilicon layer 211 is formed over the structure depicted in Figure 2C. This may be done by deposition, for example.
  • the thickness of the polysilicon layer may range, for example, between 1500 to 2000 A.
  • portions of the polysilicon layer 211 may be removed, for example, by etching, to form polysilicon pillars 213 over the portions of the substrate exposed during the removal of the oxide layer 207 and a polysilicon a pillar 215 on the oxide layer 207.
  • the pillars 213 in contact with the substrate 201 may be used to form vertical source/drain regions in the device, while the pillar 215 which rests on the oxide layer 207 may be used to form a gate electrode. While the invention is readily suitable to the formation of source/drain regions, the invention is not so limited. Other types of active regions can be formed using the invention.
  • the polysilicon source/drain pillars 213 as well as the gate electrode pillar 215 are doped to provide desired conductivity.
  • P-type or N-type dopants may be used depending upon the device structure being fabricated.
  • the doping may, for example, be performed using standard implantation techniques at dopant concentration and energy levels suitably selected in consideration of the desired conductivity. Dopant concentrations of about 1E15 to 1E16 and energy levels of 1 to 50 KeV would be suitable for many applications.
  • the polysilicon layer 211 may be doped prior to formation of the pillars.
  • the polysilicon source/drain pillars 213 may alone form the source and drain regions of the semiconductor device.
  • regions of the substrate 201 between the polysilicon pillars 213 and the gate electrode pillar 215 may be doped to form doped regions of the substrate which together with the polysilicon pillars 213 form source and drain regions.
  • a relatively thick oxide layer 221 may be formed over the substrate using, for example, well-known deposition techniques.
  • Contact holes 223 may then be cut to expose surfaces of the source/drain pillars 213 and gate electrode pillar 215, for example, using well known etching techniques.
  • the resultant structure is depicted in Figure 2G. Subsequent processing may continue with the formation of contact layers, etc.
  • transistors can be formed having increased lateral density.
  • the vertical height of the active devices may be increased and the lateral area decreased, while maintaining a volume substantially the same as a conventionally formed active device, if desired.
  • the vertical depth of the pillars can be greater than the lateral width of the pillars. This allows for the active devices to be closer together and increases the density of the chip.
  • the planarity of produced devices may be increased, thus enhancing, for example, the ability to do fine-resolution lithography.
  • the above-described process can be used to fabricate a number of different types of devices.
  • the process may be used to form silicon-on-insulator (SOI) devices.
  • SOI silicon-on-insulator
  • the process is particularly suited for SOI devices since it does not depend on back side contacts.
  • a layer of silicon is formed over an insulator using, for example, well-known techniques.
  • the silicon layer is subject to the processing discussed above with respect to the silicon substrate to form vertical active regions in the silicon layer.
  • LDD lightly-doped drain
  • FIGS. 3A through 3D illustrates fabrication steps for forming an LDD device in accordance with one particular embodiment of the invention.
  • Figure 3A illustrates polysilicon pillars 303 and 305 formed within a trench 302 of a substrate 304.
  • the structure illustrated in Figure 3A may be constructed using a process similar to that illustrated in Figures 2A through 2E.
  • the polysilicon pillars may be doped to a desired concentration level. Doping of the pillars may be done in a similar manner as discussed above.
  • portions of the substrate lying between the source/drain pillars 303 and the gate electrode pillar 305 are exposed, for example, by etching the oxide layer.
  • the exposed areas of the substrate are doped, for example, by implantation, to form lightly doped regions 307.
  • the resultant structure is depicted in Figure 3C.
  • Dopant implantation may, for example, be performed using standard implantation techniques with energy levels and dopant concentrations suitably selected based on the desired profile of the LDD regions 307.
  • Spacers 309 may be formed on sidewalls of the gate electrode 305 and sidewalls of the source/drain regions 303, as illustrated in Figure 3D.
  • the spacers 309 may, for example, be formed using conventional deposition and etching techniques. With the spacers in place, exposed portions of the substrate between source/drain regions 303 and the gate electrode 305 are doped with a heavier dopant concentration to form heavier doped regions 311.
  • the resultant structure is illustrated in Figure 3D.
  • the combination of the source/drain pillar 303, the LDD region 307 and the heavy doped region 311 together forms an active source/drain region of the device being formed.
  • the subsequent heavy dose implant may be omitted.
  • the LDD region and the pillars may be used to form the entire active structure.
  • Source/drain active regions 407 within the substrate 401.
  • a relatively thick source/drain pillar region together with a doped region of the substrate may be used to form a vertical active source/drain region.
  • the vertical thickness or height of the elevated active region pillar may be on the order of 1500 to 2000 A.
  • a trench 503 may first be formed in a substrate 501.
  • a relatively thick oxide layer 505 may then be formed over the substrate and etched to form contact holes 507 as illustrated in Figure 5B.
  • the contact holes 507 may then be filled with a polysilicon material and the resultant structure polished to form a trench having source/drain pillars 509 and a gate electrode pillar 511 disposed therein, as illustrated in Figure 5C.
  • source/drain pillars may be formed by selectively etching the substrate and leaving pillars formed of the intact substrate material.
  • the present invention is applicable to the fabrication of a number of different devices having a vertically formed active region. Accordingly, the present invention should not be considered limited to the particular examples described above, but rather should be understood to cover all aspects of the invention as fairly set out in the attached claims. Various modifications, equivalent processes, as well as numerous structures to which the present invention may be applicable will be readily apparent to those of skill in the art to which the present invention is directed upon review of the present specification. The claims are intended to cover such modifications and devices.

Abstract

A semiconductor device and method of manufacture thereof is provided. According to one embodiment, a semiconductor device is formed by forming a trench within a substrate. An oxide layer is formed within the trench and portions of the oxide layer are removed to expose one or more portions of the substrate within the trench. A plurality of doped polysilicon pillars are formed within the trench. The doped polysilicon pillars include one or more active region pillars formed on the one or more exposed portions of the substrate.

Description

MOFSET IN A TRENCH AND METHOD OF MANUFACTURE THEREOF
Field of the Invention
The present invention is directed generally to semiconductor devices and to a method of manufacture thereof and, more particularly, to fabrication of semiconductor devices having vertically formed active regions.
Background of the Invention
Over the last few decades, the electronics industry has undergone a revolution by the use of semiconductor technology to fabricate small, highly integrated electronic devices. The most common semiconductor technology presently used is silicon-based. A large variety of semiconductor devices have been manufactured having various applications in numerous disciplines. One such silicon-based semiconductor device is a metal- oxide-semiconductor (MOS) transistor. The MOS transistor is used as one of the basic building blocks of most modern electronic circuits.
The principal elements of a typical MOS semiconductor device are illustrated in Figure 1. The device generally includes a semiconductor substrate 101 on which a gate electrode 103 is disposed. The gate electrode 103 acts as a conductor. An input signal is typically applied to the gate electrode 103 via a gate terminal (not shown) . Heavily doped source/drain regions 105 are formed within the semiconductor substrate 101 and are connected to source/drain terminals (not shown) . As illustrated in Figure 1, the typical MOS transistor is symmetrical, which means that the source and drain are interchangeable. Whether a region acts as a source or drain depends on the respective applied voltages and the type of device being made (e.g., PMOS, NMOS, etc.). Thus, as used herein, the term source/drain region refers generally to an active region used for the formation of a source or drain.
A channel region 107 is formed in the semiconductor substrate 101 beneath the gate electrode 103 and separates the source/drain regions 105. The channel is typically lightly doped with a dopant of a type opposite to that of the source/drain regions 105. The gate electrode 103 is generally separated from the semiconductor substrate 101 by an insulating layer 109, typically an oxide layer such as Si02. The insulating layer 109 is provided to prevent current from flowing between the gate electrode 103 and the source/drain regions 105 or channel region 107.
In operation, an output voltage is typically developed between the source and drain terminals. When an input voltage is applied to the gate electrode 103, a transverse electric field is set up in the channel region 107. By varying the transverse electric field, it is possible to modulate the conductance of the channel region 107 between the source region and the drain region. In this manner, an electric field controls the current flow through the channel region
107. This type of device is commonly referred to as a MOS field-effect-transistor (MOSFET) .
Semiconductor devices, like the one described above, are used in large numbers to construct most modern electronic devices. As a larger number of such devices are integrated into a single wafer, improved performance and capabilities of electronic devices can be achieved. In order to increase the number of semiconductor devices which may be formed on a given surface area of a substrate, the semiconductor devices must be scaled down (i.e., made smaller). This is typically accomplished by reducing the lateral dimensions of the device structure. Continued efforts to reduce the dimensions of the semiconductor devices encounter problems related to device performance. Thus, there generally exist a tension between desires to further scale down the semiconductor devices and the need to maintain high performance and reliability.
Summary of the Invention
Generally, the present invention relates to a semiconductor device and fabrication process in which devices are formed having vertical active regions. In accordance with one embodiment of the invention, a semiconductor device is formed by forming a trench within a substrate. An oxide layer is formed within the trench and portions of the oxide layer are removed to expose one or more portions of the substrate within the trench. A plurality of doped polysilicon pillars are formed within the trench. The doped polysilicon pillars include one or more active region pillars formed on the one or more exposed portions of the substrate.
In accordance with another embodiment of the invention, a semiconductor device is provided. The semiconductor device includes a substrate having a trench formed therein and at least one vertical source/drain region formed within the trench. The vertical source/drain region includes a doped polysilicon pillar as well as a doped region of the substrate.
The above summary of the present invention is not intended to describe each illustrated embodiment or every implementation of the present invention. The figures and the detailed description which follow more particularly exemplify these embodiments.
Brief Description of the Drawings
The invention may be more completely understood in consideration of the following detailed description of various embodiments of the invention in connection with the accompanying drawings, in which:
Figure 1 illustrates elements of a typical MOS transistor; Figures 2A through 2G illustrate a fabrication process in accordance with an embodiment of the invention;
Figures 3A through 3D illustrate a fabrication process in accordance with another embodiment of the invention;
Figures 4A through 4B illustrate a fabrication process in accordance with still another embodiment of the invention; and
Figures 5A through 5C illustrate a fabrication process in accordance with yet another embodiment of the invention.
While the invention is amenable to various modifications and alternative forms, specifics thereof have been shown by way of example in the drawings and will be described in detail. It should be understood, however, that the intention is not to limit the invention to the particular embodiments described. On the contrary, the intention is to cover all modifications, equivalents, and alternatives falling within the spirit and scope of the invention as defined by the appended claims. Detailed Description of the Various Embodiments
The present invention is applicable to a number of semiconductor devices. The present invention is believed to be particularly suited to fabrication of MOS transistors having vertically formed active regions. While the present invention is not limited to such devices, an appreciation of various aspects of the invention will be gained through a discussion of various fabrication processes and device characteristics in connection with the examples provided below.
Figures 2A through 2G illustrate a fabrication process in accordance with one particular embodiment of the invention. As illustrated in Figure 2A, the fabrication process uses a substrate 201, such as a silicon substrate, on which an isolation oxide 203 has been formed. The isolation oxide 203 is typically on the order of 100 to 300 angstroms (A) . A trench 205 is defined within the substrate 201 as illustrated in Figure 2B. The trench 205 may be formed, for example, using conventional lithographic and etching techniques to a depth on the order of 1500 to 2000 A.
An oxide layer 207 is formed within the trench 205. Portions of the oxide layer 207 within the trench 205 are removed to expose portions of the substrate 209. The resultant structure is illustrated in Figure 2C. The oxide layer may be formed and removed using, for example, well-known deposition and etching techniques. The oxide thickness may range for example, from 30 to 60 A. As will be appreciated from the description below, the oxide layer 207 will be used to form a gate oxide to insulate a gate electrode from the substrate.
A relatively thick polysilicon layer 211 is formed over the structure depicted in Figure 2C. This may be done by deposition, for example. The thickness of the polysilicon layer may range, for example, between 1500 to 2000 A.
As illustrated in Figure 2E, portions of the polysilicon layer 211 may be removed, for example, by etching, to form polysilicon pillars 213 over the portions of the substrate exposed during the removal of the oxide layer 207 and a polysilicon a pillar 215 on the oxide layer 207. As will be discussed more fully below, the pillars 213 in contact with the substrate 201 may be used to form vertical source/drain regions in the device, while the pillar 215 which rests on the oxide layer 207 may be used to form a gate electrode. While the invention is readily suitable to the formation of source/drain regions, the invention is not so limited. Other types of active regions can be formed using the invention.
As illustrated in Figure 2F, the polysilicon source/drain pillars 213 as well as the gate electrode pillar 215 are doped to provide desired conductivity. For example, P-type or N-type dopants may be used depending upon the device structure being fabricated. The doping may, for example, be performed using standard implantation techniques at dopant concentration and energy levels suitably selected in consideration of the desired conductivity. Dopant concentrations of about 1E15 to 1E16 and energy levels of 1 to 50 KeV would be suitable for many applications. It is noted that, in an alternative embodiment, the polysilicon layer 211 may be doped prior to formation of the pillars. The polysilicon source/drain pillars 213 may alone form the source and drain regions of the semiconductor device. In other embodiments, as will be discussed more fully below, regions of the substrate 201 between the polysilicon pillars 213 and the gate electrode pillar 215 may be doped to form doped regions of the substrate which together with the polysilicon pillars 213 form source and drain regions.
After formation of the pillars, a relatively thick oxide layer 221 may be formed over the substrate using, for example, well-known deposition techniques. Contact holes 223 may then be cut to expose surfaces of the source/drain pillars 213 and gate electrode pillar 215, for example, using well known etching techniques. The resultant structure is depicted in Figure 2G. Subsequent processing may continue with the formation of contact layers, etc.
Using the above process, transistors can be formed having increased lateral density. In particular, by forming vertical active devices within a trench, the vertical height of the active devices may be increased and the lateral area decreased, while maintaining a volume substantially the same as a conventionally formed active device, if desired. As will be appreciated, the vertical depth of the pillars can be greater than the lateral width of the pillars. This allows for the active devices to be closer together and increases the density of the chip. By using the above process to form vertical source/drain regions, it is possible to control the amount of charge capability in the source/drain regions to be substantially the same as conventional source/drain regions, while minimizing the overall area (lateral) density for the device being produced. Moreover, by placing vertical active regions within a trench, the planarity of produced devices may be increased, thus enhancing, for example, the ability to do fine-resolution lithography.
It will be appreciated that the above-described process can be used to fabricate a number of different types of devices. For example, in addition to the more conventional type of devices, the process may be used to form silicon-on-insulator (SOI) devices. Indeed, the process is particularly suited for SOI devices since it does not depend on back side contacts. In one exemplary SOI embodiment, a layer of silicon is formed over an insulator using, for example, well-known techniques.
The silicon layer is subject to the processing discussed above with respect to the silicon substrate to form vertical active regions in the silicon layer.
While the above-process is not so limited, the following description illustrates use of the process in conjunction with the formation of source/drain regions in the substrate. In certain instances, it is desirable to form a source/drain region which has an uneven conductivity profile (i.e., heavily and lightly doped regions) such as a lightly-doped drain (LDD) device.
Figures 3A through 3D illustrates fabrication steps for forming an LDD device in accordance with one particular embodiment of the invention.
Figure 3A illustrates polysilicon pillars 303 and 305 formed within a trench 302 of a substrate 304. The structure illustrated in Figure 3A may be constructed using a process similar to that illustrated in Figures 2A through 2E. As illustrated in Figure 3B, the polysilicon pillars may be doped to a desired concentration level. Doping of the pillars may be done in a similar manner as discussed above.
After the pillars 303 and 305 have been doped, portions of the substrate lying between the source/drain pillars 303 and the gate electrode pillar 305 are exposed, for example, by etching the oxide layer. The exposed areas of the substrate are doped, for example, by implantation, to form lightly doped regions 307. The resultant structure is depicted in Figure 3C. Dopant implantation may, for example, be performed using standard implantation techniques with energy levels and dopant concentrations suitably selected based on the desired profile of the LDD regions 307.
Spacers 309 may be formed on sidewalls of the gate electrode 305 and sidewalls of the source/drain regions 303, as illustrated in Figure 3D. The spacers 309 may, for example, be formed using conventional deposition and etching techniques. With the spacers in place, exposed portions of the substrate between source/drain regions 303 and the gate electrode 305 are doped with a heavier dopant concentration to form heavier doped regions 311. The resultant structure is illustrated in Figure 3D. The combination of the source/drain pillar 303, the LDD region 307 and the heavy doped region 311 together forms an active source/drain region of the device being formed. In an alternative embodiment, the subsequent heavy dose implant may be omitted. In this embodiment, the LDD region and the pillars may be used to form the entire active structure.
In another embodiment of the invention, illustrated in Figures 4A and 4B, after doping the pillar structures as illustrated in Figure 4A, portions of the substrate between source/drain pillars 403 and a gate electrode pillar 405 are exposed and heavily doped to form source/drain active regions 407 within the substrate 401. As will be appreciated, from the preceding examples, a relatively thick source/drain pillar region together with a doped region of the substrate may be used to form a vertical active source/drain region. The vertical thickness or height of the elevated active region pillar may be on the order of 1500 to 2000 A.
It will be appreciated that a number of different variations and processing techniques may be used to form the vertical pillar structure illustrated in the above examples. For example, as illustrated in Figures 5A through 5C, a trench 503 may first be formed in a substrate 501. A relatively thick oxide layer 505 may then be formed over the substrate and etched to form contact holes 507 as illustrated in Figure 5B. The contact holes 507 may then be filled with a polysilicon material and the resultant structure polished to form a trench having source/drain pillars 509 and a gate electrode pillar 511 disposed therein, as illustrated in Figure 5C. In still another alternative, source/drain pillars may be formed by selectively etching the substrate and leaving pillars formed of the intact substrate material.
As noted above, the present invention is applicable to the fabrication of a number of different devices having a vertically formed active region. Accordingly, the present invention should not be considered limited to the particular examples described above, but rather should be understood to cover all aspects of the invention as fairly set out in the attached claims. Various modifications, equivalent processes, as well as numerous structures to which the present invention may be applicable will be readily apparent to those of skill in the art to which the present invention is directed upon review of the present specification. The claims are intended to cover such modifications and devices.

Claims

WE CLAIM :
1. A process for forming a semiconductor device, comprising: forming a trench within a substrate; forming an oxide layer within the trench; removing a portion of the oxide layer to expose one or more portions of the substrate within the trench; and forming a plurality of doped polysilicon pillars within the trench, the plurality of doped polysilicon pillars including one or more active region pillars formed on the one or more exposed portions of the substrate .
2. The process of claim 1, wherein the plurality of pillars includes a gate electrode pillar formed on the oxide layer.
3. The process of claim 2, wherein forming the plurality of doped polysilicon pillars includes: forming a polysilicon layer in the trench; selectively removing portions of the polysilicon layer to form a plurality of undoped polysilicon pillars; and doping the plurality of undoped polysilicon pillars .
4. The process of claim 3, further including planarizing the plurality of doped polysilicon pillars with an upper surface of the substrate.
5. The process of claim 2, wherein forming a plurality of doped polysilicon pillars includes: forming a doped polysilicon layer in the trench; and selectively removing portions of the doped polysilicon layer.
6. The process of claim 5, further including planarizing the plurality of doped polysilicon pillars with an upper surface of the substrate.
7. The process of claim 2, further including doping regions of the substrate between the gate electrode pillar and the one or more active region pillars to form active regions in the substrate.
8. The process of claim 7, further including removing portions of the oxide layer over the regions of the substrate between the gate electrode pillar and the one or more active region pillars prior forming the active regions in the substrate.
9. The process of claim 7, wherein the active region pillars and active substrate regions together form source/drain regions.
10. The process of claim 8, wherein doping the regions of the substrate includes lightly doping the active substrate regions to form lightly-doped regions in the active substrate regions.
11. The process of claim 10, wherein doping the regions of the substrate includes heavily doping the active substrate regions to form heavily-doped regions in the active substrate regions.
12. The process of claim 11, further including forming spacers on the sidewalls of the gate electrode pillar and the one or more active region pillars prior to heavily doping the active substrate regions.
13. The process of claim 2, wherein the plurality of polysilicon pillars are formed to a thickness about the same as a depth of the trench.
14. The process of claim 1, wherein the plurality of polysilicon pillars are formed to a vertical thickness about the same as a depth of the trench.
15. The process of claim 14, wherein the vertical thickness of the polysilicon pillars and the depth of the trench are about 1500 to 2000 A.
16. The process of claim 1, wherein the oxide layer comprises a relatively thin oxide layer.
17. The process of claim 1, wherein the oxide layer comprises a relatively thick oxide layer.
18. The process of claim 17, further including removing a portion of the oxide layer to form a thin oxide over a portion of the substrate.
19. The process of claim 18, wherein forming the plurality of doped polysilicon pillars includes filling the removed portions of the oxide layer with a polysilicon.
20. The process of claim 19, wherein the polysilicon is a doped polysilicon.
21. The process of claim 19, further including doping the polysilicon.
22. The process of claim 19, further including polishing the relatively thick oxide layer and the polysilicon pillars to the surface of the substrate.
23. The process of claim 1, further including: forming a relatively thick oxide layer over the doped polysilicon pillars; and removing portions of the relatively thick oxide layer to expose the doped polysilicon pillars.
24. A semiconductor device, comprising: a substrate having a trench formed therein; and at least one vertical source/drain region formed within the trench, the at least one vertical source/drain region including a doped polysilicon pillar having a vertical depth greater than a width of the pillar.
25. The semiconductor device of claim 24, wherein the vertical source/drain region includes a doped region of the substrate adjacent the pillar.
26. The semiconductor device of claim 24, further including a gate oxide disposed in the trench and a gate electrode pillar formed on the gate oxide.
27. The semiconductor device of claim 26, wherein the gate electrode pillar and the doped polysilicon pillar each have a vertical depth of about a thickness of the trench.
28. The semiconductor device of claim 25, wherein the vertical depth ranges from about 1500 to 2000 A.
29. A process for forming a semiconductor device, comprising: forming a silicon layer on an insulator; forming a trench within the silicon layer; forming an oxide layer within the trench; removing a portion of the oxide layer to expose one or more portions of the silicon layer within the trench; and forming a plurality of doped polysilicon pillars within the trench, the plurality of doped polysilicon pillars including one or more active region pillars formed on the one or more exposed portions of the silicon layer.
30. A semiconductor device, comprising: an insulator; a silicon layer formed on the insulator, the silicon layer having a trench formed therein; and at least one vertical source/drain region formed within the trench, the at least one vertical source/drain region including a doped polysilicon pillar having a vertical depth greater than a width of the pillar.
PCT/US1998/006138 1997-05-20 1998-03-27 Mofset in a trench and method of manufacture thereof WO1998053492A1 (en)

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