WO1998053556A2 - Direct sequence spread spectrum method, computer-based product, apparatus and system tolerant to frequency reference offset - Google Patents
Direct sequence spread spectrum method, computer-based product, apparatus and system tolerant to frequency reference offset Download PDFInfo
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- WO1998053556A2 WO1998053556A2 PCT/US1998/010164 US9810164W WO9853556A2 WO 1998053556 A2 WO1998053556 A2 WO 1998053556A2 US 9810164 W US9810164 W US 9810164W WO 9853556 A2 WO9853556 A2 WO 9853556A2
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04B—TRANSMISSION
- H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
- H04B1/69—Spread spectrum techniques
- H04B1/707—Spread spectrum techniques using direct sequence modulation
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- the present invention is directed to communications-related systems, networks apparatuses and methods as well as computer-based digital signal processing mechanisms and methods used therein. More particularly, the invention is directed to the field of direct sequence spread spectrum (DSSS) communication that employ a DSSS transmitter and a DSSS receiver, or transceiver configured to convey a data signal in a transmitted DSSS signal by spreading the data signal on transmission and correlating on reception so as to "despread" the DSSS signal and recover the data signal.
- DSSS direct sequence spread spectrum
- RF radio-frequency
- FM frequency modulation
- AM amplitude modulation
- interference signals e.g. jammers
- disturbances in the communications path between the transmitter and receiver can interfere with reception. For example, fading due to multipath or atmospheric obstruction can attenuate the signal significantly. Also, shadowing becomes significant if the signal must pass through solid matter such as buildings, walls, floors or trees and vegetation.
- Spread spectrum radio communication addresses the shortcomings of narrowband communications by mixing (i.e. applying) a wideband spreading signal to the data signal so as the "spread" the data signal.
- the transmitter also modulates a RF carrier with data, as with the narrowband systems, but then adds one more modulation step by modulating the signal with a wideband, noise-like signal (e.g. a PN code). Consequently, the data signal is spread in frequency over a much larger bandwidth, typically several million Hertz (MHZ) .
- Common spread spectrum techniques include frequency hopping and DSSS. Frequency hopping systems move (i.e., "hop") the data modulated carrier to frequencies following a pseudo-random pattern defined by the PN code.
- DSSS mix a PN code with the data modulated carrier to create a DSSS signal which simultaneously occupies roughly the bandwidth of the pseudo noise signal.
- Narrowband interference signals transmitted at same frequency as a portion ofthe spread signal "jam" the spread signal by an amount proportional to the ratio of jammer bandwidth to pseudo-noise bandwidth.
- the interference signal will at least be attenuated by a "processing gain" ofthe spread spectrum signal, where processing gain is defined as a ratio of data signal bandwidth to spread signal bandwidth.
- processing gain is defined as a ratio of data signal bandwidth to spread signal bandwidth.
- DSSS systems have been used in the past to achieve low probability of intercept (LPI) for secure communication and thus are valuable in military applications or other scenarios requiring covert communications.
- LPI low probability of intercept
- DSSS is also used in places where multipath or fading is prevalent, such as satellite communication.
- GPS Global Positioning System
- conventional DSSS systems are expensive (considering the transmitter and receiver) because relatively high performance frequency references and digital signal processing equipment is used. Accordingly, DSSS techniques are most commonly used in military and high-end consumer market, where component cost is less of a factor than with low-end consumer product.
- Conventional direct sequence spread spectrum transceivers are directed towards high-end systems (e.g.
- Past DSSS systems have avoided using lower cost components because conventional wisdom dictates that selectively high fidelity frequency references are required at the transmitter and receiver, as well as powerful digital signal processing equipment so to compensate for even minor frequency deviations between transmitter and receiver systems. Contrary to conventional DSSS design practice, the present inventors have identified that these conventional DSSS devices are not applicable for low-end, inexpensive, commercial use applicable for high-volume sale, nor are they well suited for small packages, that may be used in a variety of non-standard field uses, such as, for example, home security and fire systems, data telemetry, access control, remote meter reading as well as other applications.
- PN codes that require substantial digital signal processing to be despread in a receiver. While there are many advantages to using a long code (such as with code division multiple access, CDMA, telephony which permits many users to transmit on a common channel at the same time) the present inventors have recognized that a shorter code, such as a 63 bit PN code, may enable the use of components applicable for lower cost applications.
- FIG. 1 is a block diagram of a conventional receive system that of either a conventional receiver (either narrowband or DSSS receiver)
- the receive system includes a RF front end section 120, a first local oscillator (109, 112, 111, and 110, as will be discussed) section, an analog -to-digital conversion section 121, baseband mixing section (115, as will be discussed) and a baseband processing section 122, as shown
- the details of the conventional receiver are desc ⁇ bed below, following a general overview description
- the RF section 120 performs the function of converting electromagnetic wave energy (including the transmitted signal) and outputtmg an analog signal
- the analog signal is maintained within a predetermined signal level range, as controlled by an automatic gain control circuit (AGC) as shown
- AGC automatic gain control circuit
- the output from the RF front end is provided to a first local oscillator section having a mixer 109, which translates the analog signal to a lower frequency by using a precise, and generally expensive, voltage controlled oscillator 110
- the downconverted signal is then passed to the intermediate frequency processing section 121, that adds appropriate gam p ⁇ or to a digitahzation process while filtering out-of-band images necessary for the digitization process, as will be discussed herein
- the output ofthe intermediate frequency section is passed to the analog to digital converter ADC shown as mixer 115 (as will be discussed), which converts the analog signal into a digital representation for subsequent processing in the baseband section 122
- the analog AGC's function is to keep the signal level applied to the ADC 115 within an operational range ofthe ADC
- the signal is passed to the baseband section 122, where digital signal processing operations are performed on the signal and the signal is detected and demodulated, resultmg in outputtmg the data signal originally transmitted from the transmitter (either in a spread or non-spread form)
- the burden of performing the "inverse spreading" (despreading) operation on the signal usually falls on the digital signal processor 116 section 1 ofthe baseband processing section 122
- the despreading code is mixed in the RF front end 120, first LO or intermediate frequency (IF) sections ofthe receiver, but such analog architectures require significantly precise components or specialized compensation mechanisms
- conventional direct sequence spread spectrum receivers require high performance digital signal processors or complicated analog sections m order to perform the despreading and correlation functions, as well as signal acquisition and demodulation processes
- a precise frequency reference at the DSSS transmitter is assumed to be present so little to no frequency ambiguity is presented into the signal received by the receiver
- Conventional digital receiver design wisdom is such that the loss in performance associated with using low cost, low power desirable and possible components does not justify their use in light ofthe fact that slightly more expensive components provide greater precision and processing power and therefore avoid performance problems associated with low-cost, inaccurate components
- Figure 1 depicts RF downconversion and signal conditioning components used to prepare a received analog signal for sampling
- Antenna 101 receives the RF signal sent from a transmitter and passes the signal through RF diversity switch 102 and on to a bandpass filter (BPF) 103
- BPF bandpass filter
- a controllable select mechanism 104 may select antenna 105 to receive the RF signal
- the antennas may be physically separated and/or of different polarizations so as to enable spatial or polarization diversity reception
- the BPF 103 rejects undesired frequencies prior to signal amplification by an amplifier 106
- the RF signal is then filtered by BPF 107 and amplified by another amplifier 108 prior to downconversion in a mixer 109
- VCO voltage controlled oscillator
- the downconverted signal is positioned at an intermediate frequency (IF) determined by the downconversion tone applied to the mixer 109, and additional gain is provided by an amplifier 113
- a BPF 114 serves as an anti-aliasing filter pnor to a second downconversion operation that, as recognized by the present mventors, may be performed with the sampling ADC 115
- the signal is positioned near baseband (l e near 0 Hz)
- the digital signal processor (DSP) 116 performs va ⁇ ous operations including despreading the signal if it is a spread spectrum signal and then sends the baseband signal to a demodulation block 117 so as to extract the data originally added to the transmitted signal by the transmitter Frequency control of the DSP 116 is provided by an oscillator 118 and using the DSP 116 passes the frequency control to all relevant sections 110, 115 and 117 to compensate for mismatch m received signal frequency, and/or chip phase, though frequency mismatch is usually minimized by using accurate frequency references at the transmitter and receiver While Figure 1 depicts a smgle RF downconversion step, other downconversion steps may be added to properly center the received signal at the desired ADC IF frequency
- Figures 2 and 3 show respective frequency plots of a signal of interest, before and after, respectively, being passed through a harmonic sampling operation, a technique that may be used to reduce signal processing complexity in digital receivers
- harmonic sampling is performed using a "real", not complex or quadrature, harmonic sampling approach, as will be discussed
- Harmonic Sampling Harmonic sampling also known as undersampling, bandpass sampling or Super-Nyquist sampling
- IF intermediate frequency
- Figures 2 and 3 illustrate an example strig ⁇ o where the sampling rate for the ADC is between 0 Hz (labeled as 204) and the maximum analog input frequency 214 (These specific frequencies are used to simplify the later discussion with respect to these present invention and should not be construed as a specific implementation of a prior art device)
- the signal of interest 210 exists at an IF frequency 212 of 10 8 MHZ
- the sample rate ofthe converter 206 is an integer multiple such as 4 times the chipping rate (l e , a rate at which chip ofthe PN sequence are produced)
- the sample rate of the converter 206 is an integer multiple such as 4 times the chipping rate (l e , a rate at which chip ofthe PN sequence are produced)
- Fs sample rate
- any signal that exists between 0 Hertz (Hz) 204 and Fs/2 205 (l e , the Nyquist bandwidth) is digitized and represented untranslated following digitization
- the sampling device operates as a discrete component whose sample event is set by a clock edge
- the signal is tracked until the sample edge occurs, and is then immediately held
- this track and hold system operates on an infinitesimally small time window (a clock edge)
- This time domain operation is an impulse function and can be expressed as a series of fundamental frequencies (tones) in the frequency domain separated by the frequency ofthe sampling clock
- tones fundamental frequencies
- Each of these tones is equal in magnitude and extend to infinity
- these tones act as harmonics in an ideal mixer and the input signal is mixed against these harmonics, creating repetitive images in the digitized spectrum
- the resulting images 318, 319, 320, 321, 322, and 323 are separated every Fs/2 m frequency
- Ideal IF center frequencies (F c ) will therefore exist at multiples ofthe sample rate ⁇ V ⁇ ofthe sample rate
- the following equation may be used to select ideal IF frequencies for a given Fs
- IF Fs(N ⁇ l A), where N is an integer harmonic sampling multiplicand
- N 2 and "+ l /4 H ⁇ s selected Whenever the "-'//'option is selected, the downconverted image is "high side injected” and will be spectrally flipped (high frequencies at 0, and 0 at Fs/2)
- the actual IF frequency can exist at anv harmonic of the sample rate
- practical limitations should be observed because the input frequency range 202 is limited primarily due to the limitations in the track and hold operator to adequately follow the signal without introducing distortion Any slew limiting or overshoot will introduce noise mto the system, which is true for limiting single-bit digitizers as well as multi-bit digitizers
- aperture jitter cont ⁇ butes to phase noise in the digitized signal, where aperture jitter is defined as a time difference present in a decision threshold for realizable sampling components Assuming the sample clock has zero phase noise (which seldom is true), the sampling component will observe the clock
- the sample rate 406 is shown to be 4 times the chipping rate, and the anti-alias lowpass filter 408 attenuates undesired frequencies
- the downsampled, digitized spectrum exists at 0 Hz, 519 (i e , baseband), and present in the Nyquist bandwidth 516 are two copies ofthe same spectrum flipped about 0 Hz All ofthe signal information is available now in the previous bandwidth of interest, but, 3 dB off orthogonal transmitter loss is present resultmg in degraded performance Repetitive images ofthe signal exist throughout the frequency spectrum and are depicted as items 518, and 520 through 522 Techniques for Processing Digital Signals Having High Sample Rates
- a challenge with modern digital receivers is identifying how to convert radio frequency energy into digitized samples which occur at extremely high sampling rates (in most applications well over 1 MHZ) and providing enough digital signal processing power to process in real time the samples provided from the analog to digital converter
- a technique that has been used to lower the sample rate of digital signals is to low pass filter the digital signal samples, followed by decimating in time the respective samples
- Decimation in time is a process in which a set of adjacent samples are combined into a lesser number of samples so as to produce a lower sample rate This lesser number of samples is then more easily handled by digital signal processors Accordingly, decimation reduces signal processing demands in digital receivers by lowering sample rate
- decimation and sample rate reduction techniques see Frerking, M, "Digital Signal Processing and Communication Systems", Van Nostrand Rernhold, 1994, the contents of which is incorporated herem by reference, in particular pp 65-66, 193-199 Nonetheless, while decimation is an approach for reducing sample rate, conventional wisdom suggests that performance in digital receivers requires high
- Receive systems typically contain cascaded filters to band-limit the received signal prior to detection
- the final filter prior to detection sets the predetection bandwidth ofthe system
- this predetection bandwidth is as narrow as possible so as to maximize receiver sensitivity
- Typical direct sequence systems set this final predetection bandwidth to be equal to the desired signal of interest, thus maximizing the receive sensitivity
- Distnbutions 630 and 625 are for a keyed, or "ON" signal of -110 dBm as detected in a 115 kHz and 20 kHz predetection bandwidth respectively
- SNR signal to noise ratio
- the present inventors have identified that a performance penalty is to be paid in the form of decreased SNR if low-cost, inaccurate frequency references are used for transmitting and receivmg a signal
- Figure 6 further demonstrates that the wider predetection bandwidth of 115 KHz incurs a sensitivity loss relative to a narrower predetection bandwidth As the predetection bandwidth is allowed to grow wider, the noise distnbution function approaches the signal distnbution function actually overlapping it and inducing e ⁇ ors on detection which corresponds to a reduction m sensitivity
- Direct sequence transmission systems require that the receiver and the transmitter have aligned pseudorandom codes in order to properly despread the received signal.
- the receiver has the burden of aligning the receiver pseudorandom code with a transmitter pseudorandom code in order to properly despread the signal.
- Direct sequence receivers must correlate the received signal in order to recover data.
- the correlation process can be described as either a serial or parallel process.
- Prior art has typically performed low cost correlation in a serial process wherein multiple bit intervals (or multiple code repetition intervals) of received data are used against successive relative chip phases ofthe receiver PN code to correlate data.
- High cost, high end systems typically achieve correlation much faster using a technique called parallel correlation.
- System which use parallel correlation use one or a few code periods of data to correlate against many phases ofthe PN code in parallel to produce a correlation function over one or a few code periods of data.
- the present inventors have recognized that with either the slow serial search or the parallel search, the RF front end must remain active in order to continuously receive the signal, and thus, cannot be turned off during the computation ofthe correlation function, so as to conserve battery power.
- a fine sync process For direct sequence receivers, a fine sync process , sometimes called a fine search process, further reduces correlation error following the coarse synchronization process (course sync, or coarse search process) .
- the coarse sync process terminates when a correlation result surpasses a predetermined threshold (i.e., a trip condition) indicating that the received signal is aligned to within +/- Vi of a code chip interval of the PN code.
- a predetermined threshold i.e., a trip condition
- the signal and the PN code should be perfectly aligned to provide optimum performance. So as to more closely align the signal with the PN sequence, a fine sync process is initiated after the coarse sync process so as to further reduce the relative chip interval between the received signal and the receiver PN code.
- Figure 7 illustrates results observed in an ideal receiver when attempting to align the PN code to the received signal through successive 1/4 chip fractional chips steps as part of a fine sync process.
- the circles in Figure 7 represent respective powers (i.e., co ⁇ elation results) received from the fine sync correlation process for relative 1/4 chip fractional offsets of a signal, absent noise, and the PN code.
- a perfect correlation yields the maximum process gain at zero chip phase error, as shown by the center circle.
- the maximum process gain is 18 dB.
- chip enors that are greater than 1 chip width result in the loss of all system process gain, such that the received signal cannot be detected or demodulated.
- Fine search processes are used to initially acquire the spread spectrum signal and at predetermined time intervals through the data message in order to maintain correlation alignment.
- the term "reposition” or “repo” is a term used in spread spectrum systems, such as in transceiver systems designed by Axonn, to reposition the PN code and received signal while receiving a data message portion ofthe received signal. Drift Offset Between Transmit and Receive Frequency References
- Typical direct sequence spread spectrum systems require very stable local frequency references for transmit and receive operations in order to maintain near coherent (i.e., in phase) operation. Ideally. transmitters and receivers will operate using a common frequency reference in order to maintain co ⁇ elation throughout the data message.
- An example of such a direct sequence system is the Global Positioning Satellite (GPS) system, which requires very accurate frequency references, typically Cesium based or other atomic standards.
- GPS Global Positioning Satellite
- frequency offset between the transmitter and the receiver may be measured to determine the magnitude and direction of the frequency uncertainty
- Frequency and /or phase detectors may be used to determine the magnitude and direction ofthe frequency uncertainty
- RF downconversion portion of the receiver and not in the baseband processing section of the receiver, preserves the signal processing efficiency, thereby enabling the use of lower cost, lower performance digital signal processing components as compared with state-of-the-art signal processing components
- a first LO is usually generated by a phase and/or frequency locked synthesizer
- a phase and/or frequency locked synthesizer A block diagram of an integrated circuit-based LO synthesizer, such as a National Semiconductor
- LMX1501A is given in Figure 8
- Conventional phase lock frequency synthesizers are descnbed in Manassewitsch, V , "Frequency Synthesizers Theory and Design", John Wiley & Sons, 1987, pp 43-48, the contents of which is incorporated herein by reference
- the synthesizer of Figure 8 includes a stable reference frequency source 800 (such as a quartz crystal oscillator), a reference divider 805, a phase and/or frequency detector 810, a loop filter 820, a voltage controlled oscillator 830 and feedback dividers 840 and 850.
- An output 860 ofthe synthesizer is a signal at the desired frequency.
- the desired frequency is set by programming the moduli ofthe dividers 805, 840 and 850.
- Digital signal processing systems typically employ decimation as a way to lower a number of samples that need to be processed at various processing steps.
- the effect of decimation is to combine a number of samples into a lesser number of samples, or merely select a subset of samples within a block of adjacent samples for subsequent processing.
- Decimation is typically preceded by a filter whose characteristics often impact signal strength adversely, particularly because the decimation operation has a characteristic transfer function that preferentially passes signals occurring in a middle portion ofthe characteristic transfer function, but attenuating signal offset from the middle portion.
- the present inventors have identified methods for eliminating or limiting the effects of decimation loss while minimally impacting processing requirements.
- one object ofthe present invention is to overcome the above identified limitations and excesses in conventional direct sequence spread spectrum systems that prohibit the use of low-cost, low-end frequency references and digital signal processing components for performing the substantive direct sequence spread spectrum transceiver operations. It is another object ofthe present invention to provide a method and apparatus for receiving a direct sequence spread spectrum signal sent from a transmitter having a relatively inaccurate frequency reference.
- Yet another object ofthe present invention to provide a method and apparatus for quickly acquiring a transmitted direct sequence spread spectrum signal.
- An aspect of this object is to provide a fast serial search method that offers the simplicity attributes of a conventional slow serial search method and efficiency attributes of a parallel co ⁇ elator, while also conserving battery power by disabling an RF front- end of a transceiver after receiving a portion ofthe signal and while attempting to acqire the direct sequence spread spectrum signal.
- Still a further obj ect ofthe present invention is to provide a receiver and/or transceiver architecture that includes a scalable sensitivity attribute that allows the sensitivity of the receiver/transceiver to be incrementally improved, at the expense of increasing computational loading.
- AGC automatic gain control
- DC direct current
- Another object of the present invention to provide a method for receiving OOK signals using a receiver and/or transceiver that employs a hard limited analog to digital converter.
- Still another object ofthe present invention is to provide a direct sequence spread spectrum system/ network that establishes a communications protocol for saving battery power at various remote receiver/transceiver elements in the network.
- a method, apparatus, computer-based product and system that uses a receiver (or transceiver) to receive, digitize and process a direct sequence spread spectrum signal using efficient, low-cost digital signal processing components
- a radio front end, and/or analog to digital conversion (ADC) apparatus are mcluded to receive the direct spectrum signal and convert the received signal into a digitized signal
- Downconversion and decimation are performed on the digitized signal at an intermediate frequency prior to despreadmg and correlating the digitized signal with a pseudorandom noise (PN) code used at a transmitter to spread a data signal contained in the direct sequence spread spectrum signal
- PN pseudorandom noise
- despreading and co ⁇ elating the signal with PN signal extracts the data signal portion ofthe direct sequence spread spectrum signal for subsequent processing
- a timmg and state control mechanism is included and provides time reference co ⁇ ection information to the signal processing components of the receiver and/or transceiver, without expressly
- the receiver and transceiver employ power management mechanisms that, at least in selected embodiments, may be powered by small battenes that apply power only to those components necessary to maintain an operational state ofthe receiver and/or transceiver, based on a present operational state ofthe receiver and transceiver Using the power management features, the receiver and/or transceiver may communicate with other direct sequence spread spectrum transmitters and receivers as part of a communications network for multi-year penods of time
- FIG. 1 is a block diagram of a conventional Digital Signal Processor (DSP)-based receiver
- Figure 2 is a graph illustrating a signal spectrum before conventional harmonic sampling of an Intermediate Frequency (IF) signal when the IF signal is converted to "near baseband",
- IF Intermediate Frequency
- Figure 3 is graph illustrating a resulting frequency spectrum of conventional harmonic sampling ofthe Intermediate Frequency (IF) signal of Figure 2 when the IF signal is converted to "near baseband”
- Figure 4 is a graph illustrating the signal spectrum before conventional harmonic sampling of an
- Figure 5 is graph illustrating a resulting frequency spectrum of conventional harmonic sampling ofthe IF signal of Figure 4 when the IF signal is brought directly to baseband
- Figure 6 is a graph that shows signal level distributions for 115 kHz and 20 kHz of noise bandwidth
- Figure 7 is a graph of a conventional co ⁇ elation function with associated power loss due to fractional chip e ⁇ or of spreading code alignment
- Figure 8 is a block diagram of a conventional local oscillator frequency synthesizer
- Figure 9 is a block diagram of a smgle channel transceiver ofthe first embodiment ofthe present invention.
- Figure 10 is plan view of the single channel transceiver, and associated battery pack of the first embodiment
- Figure 11 is a block diagram of a digital signal processing portion ofthe single channel receiver portion ofthe transceiver of Figure 9
- Figure 12 is a circuit diagram of a digital downconversion and decimation stage ofthe transceiver ofthe first embodiment, as realized by a table lookup process,
- Figure 13 is a circuit diagram that shows an alternative digital downconversion and decimation stage, realized by Boolean logic
- Figure 14 is a graph that demonstrates (1) how decimation can reduce system performance, and (2) how this reduction in system performance can be avoided accordmg to the signal processing architecture ofthe first embodiment
- Figures 15A-B are graphs that illustrate a signal acquisition process ofthe first embodiment
- Figure 16 is a flow chart of a fast tune domam se ⁇ al search process ofthe first embodiment
- Figure 17 is a graph that shows how the ideal correlation process of Figure 7 is adversely affected by noise
- Figure 18 is a graph that compares respective results of different inventive fine search methods
- Figure 19 is a flow chart of a Center of Mass fine search method
- Figure 20 is a flow chart of a Center of Mass 9 method
- Figure 21 is a flow chart of a Center of Mass 5+ method
- Figure 22 is a flow chart of a Center of Mass 9' method
- Figure 23 is a flow chart of a top-level search process performed by the transceiver of the first embodiment ofthe present invention
- Figure 24 is a graph that shows how antenna diversity can improve the received signal to noise ratio
- Figure 25 is a block diagram of a low-cost implementation of a frequency diversity transmitter portion ofthe transceiver of Figure 9;
- Figures 26A-B are graphs showing the respective transmitted signals with frequency diversity disabled and enabled
- Figures 27A-D are timing diagrams showing how a transceiver ofthe first embodiment implements antenna and frequency diversity
- Figure 28 is a graph showing how averaging a signal in the first embodiment reduces an effects of noise
- Figure 29 is a graph showing how averaging reduces a false alarm rate in the first embodiment
- Figures 30A-F are respective approaches for incrementally increasing data rate using partial sums ofthe co ⁇ elation function
- Figure 31 is block diagram of an alternative demodulator of the first embodiment showing a differential binary phase shift keying (DBPSK) demodulator, with scaleable bit rate;
- Figure 32 is a block diagram of an alterative embodiment of a receiver portion shown in Figure
- Figure 33 is a illustration of an approach for implementing a frequency detection portion ofthe receiver shown in Figure 32;
- Figure 34 is a block diagram of an implementation ofthe digital-to-analog converter of Figure 32;
- Figure 35 is a block diagram ofthe digital downconversion, decimation, and removal of Analog-to-
- ADC Digital converter
- Figure 36 is a block diagram of channel formation portion ofthe multichannel receiver shown in Figure 35, which reduces processing requirements for symmetric channel filters;
- Figure 37 is a block diagram of a center channel forming portion, having reduced processing requirement attributes, for a center channel filter ofthe multichannel receiver of Figure 35,
- Figure 38 is a graph demonstrating how a reduction in decimation loss may be achieved m the multi-channel receiver ofthe second embodiment ofthe present invention
- Figure 39 is a graph showmg how non-uniformly spaced frequency channels in the multi-channel receiver ofthe second embodiment limits system performance loss
- Figure 40 is a block diagram of a fast frequency domain code correlator portion of the second embodiment
- Figure 41 is a block diagram of a conventional co ⁇ elator
- Figure 42 is a block diagram of a conventional circular co ⁇ elator
- Figure 43 is a block diagram of a conventional circular co ⁇ elator implemented with a convolution process
- Figure 44 is a block diagram of a conventional circular convolution correlator, operating in the frequency domain
- Figure 45 is a illustrative flow diagram of an implementation of an inventive frequency domain code correlator ofthe second embodiment
- Figure 46 is a graph of signal conditions that can cause false t ⁇ ps (I e , false co ⁇ elation detection indications),
- Figure 47 is a graph that shows how the power of a received noise signal will be distnaded among frequency channels in a multi-channel receiver
- Figure 48 is a graph that shows how the power of a received Carrier Wave (CW) jammer signal will be distributed among frequency channels in a multi-channel receiver
- Figure 49 is a graph that shows how the power of a received non-co ⁇ elated spread spectrum signal will be distnaded among frequency channels m a multi-channel receiver
- Figure 50 is a graph that shows how the power of a received correlated spread spectrum signal will be distributed among frequency channels m a multi-channel receiver
- Figure 51 is a flow chart of false trip avoidance method implementable in the multi-channel receiver
- Figure 52 is a graph illustrating results of a co ⁇ elation function of a single code penod of data in the multi-channel receiver embodiment
- Figure 53 is a graph similar to Figure 52, but mcludmg an averaging mechanism to reduce the effect of noise,
- Figure 54 is another graph showing how averagmg reduces a false alarm rate m the multi-channel receiver
- Figures 55-61 are flow charts of an Automatic Gain Control (AGC) method implementable in the multi-channel receiver ofthe second embodiment
- Figure 62 is a graph showing signal power loss in a multi-channel receiver of the second embodiment due to past frequency drift ofthe transmitter;
- Figure 63 is a graph showing received signal loss due to fast transmitter frequency drift;
- Figure 64 is a flowchart of a process implementable in the multi-channel receiver to compensate for fast frequency drift in a signal transmitted by a transmitter;
- Figure 65 is a graph showing a method for limiting noise contribution and corresponding to the process illustrated in Figure 64;
- Figures 66A-C are graphs of signal loss due to frequency error and how this loss may be reduced by implementing a code phase repositioning and predictive code phase repositioning process throughout the message;
- Figure 67 is a block diagram of a system with multiple transmitters, and multiple receivers that are connected to a processor via a common bus in a network, according to a third embodiment of the present invention.
- FIG. 68 is a block diagram showing a battery operated remote transceiver (BORT) application ofthe network of Figure 67;
- BORT remote transceiver
- Figures 69A-B are graphs shows network timing, co ⁇ esponding to Figures 67 and 68;
- Figures 70A-C jointly present a flow diagram of a process flow implemented in a BORT device of Figure 68;
- Figures 71 A-B jointly present a flow diagram of a process flow of a system transceiver of Figure 68;
- Figures 72A-C jointly present a timing diagrams showing the steady state communication exchanges between a system transceiver and a BORT device;
- Figures 73A-B jointly present a flow diagram showing the steady state operation of a BORT device;
- Figure 74 is a timing diagram showing the initialization sequence of a BORT device in a BORT- based system, or network;
- Figure 75 is a flow diagram showing a BORT initialization process
- Figures 76A-C are timing diagrams showing the re-synchronization sequence of a BORT device in a BORT-based system, or network
- Figure 77 is a flow diagram of a BORT re-synchronization process. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
- a first embodiment of the present invention in the form of a credit card sized single channel transceiver (which includes a receiver and a transmitter, hence the term "transceiver"), that is included as part of a direct sequence spread spectrum network of transmitters, and receivers, which include transceivers.
- the present transceiver is of a sufficiently small size that it may be operated under battery control, and require low end, low performance digital signal processors in order to perform the digital receiver, transceiver and other control functions.
- Figure 9 is a block diagram ofthe single channel transceiver that includes two antennas 901 and 903 that feed a radio frequency (RF) front end 905.
- a direct sequence spread spectrum signal formed at a transmitter preferably with a 63 bit pseudorandom noise (PN) code at a transmitter, is coupled into the antennas 901 and 903 and to the RF front end 905.
- An output ofthe RF front end 905, provides, at an intermediate frequency (IF), the received signal to a single bit analog to digital converter (ADC) 907.
- the ADC 907 converts the analog signal into a series of digital samples, as a particular sample rate as will be discussed, which are then be processed in baseband processing section 908.
- the digital signal processing section 908 includes a low performance 16-bit digital signal processor, which operates at less than 20 MHZ clock.
- One example of such a digital signal processor is Model 893x1, available in the United States from Zilog.
- the digital samples from the ADC 907 are passed to a quadrature (i.e., inphase, I and quadrature, Q) downconversion mechanism 909 that further reduces the center frequency of the received signal to baseband, and decimates the digital signals.
- a quadrature (i.e., inphase, I and quadrature, Q) downconversion mechanism 909 that further reduces the center frequency of the received signal to baseband, and decimates the digital signals.
- the output ofthe quadrature downconversion mechanism 909 is provided to a direct sequence despreading/co ⁇ elator mechanism 911.
- the despreading correlation mechanism 911 aligns the PN code, which is the same code as that used to spread a data signal at the transmitter but generated locally at the transceiver, to the incoming signal so as to correlate the received signal with the locally generated PN code. As a consequence (as will be explained), the despreading/correlating mechanism 911 further decimates the co ⁇ elated signal so as to further reduce the data rate and realize the 18 dB of processing gain (i.e., the gain associated with the PN spread spectrum signal) so that the signal may then later be passed to additional mechanisms for identifying when the signal is correlated, how well the signal was correlated, and ultimately for extracting the data from the co ⁇ elated signal.
- the PN code which is the same code as that used to spread a data signal at the transmitter but generated locally at the transceiver
- the output of the direct sequence despread/co ⁇ elator 911 passes to a switch 913, preferably implemented as a state-driven digital process, under control of a timing and state control mechanism 921, as shown.
- the timing and state control mechanism 921 first throws the switch 913 so as to connect to a coarse search and trip mechanism 919 which performs initial signal acquisition, and acquisition detection respectively. Once the coarse search and trip mechanism 919 determines that the signal has been acquired, the timing and state control mechanism 921 throws the switch 913 into a middle position, as illustrated, so as to pass the output ofthe direct sequence despread/correlator 911 to a fine search mechanism 917.
- the fine search mechanism adjusts the receive PN sequence to align within a small predetermined chip interval with respect to the transmitted PN sequence.
- the fine search mechanism 917 positions the received PN sequence to less than 1/4 of a chip interval.
- the timing and state control circuit 921 moves the switch 913 to the upper position, as illustrated, so as to pass the output of the direct sequence despread/co ⁇ elator 911 to the demodulation circuit 915 which extracts the data from the transmitted signal and passes the data to a data sink as shown.
- the output of the demodulation mechanism 915 is also passed to the timing and state control mechanism 921 as a reposition signal to perform a reposition operation like that discussed in U.S. Patent 5,457,713, incorporated herein by reference.
- the time reference co ⁇ ection mechanism 923 provides a time reference co ⁇ ection signal to the
- ADC 907 quadrature downconversion mechanism 909, and direct sequence despread/correlator mechanism 911, in order to compensate for time drift e ⁇ ors induced by differences in transmitter and receiver time references (a time reference being a particular implementation of a frequency reference, and thus the two terms being used in a co ⁇ esponding sense herein), due to inherent inaccuracies in low-cost, low performance time references such as receiver time reference 927 as shown.
- the time reference co ⁇ ection mechanism does not adjust the receiver time reference 927, as is done in convention receivers. Rather the time reference correction signal compensates for the inaccuracies induced by the time reference 927 in the various elements that employ an input from the receiver time reference 927.
- the timing and state control mechanism 921 also includes an antenna select control signal which selects between antennas 901 and 903 when antenna diversity (such as for spatial or polarization diversity purposes) is employed.
- the select signal includes a frequency control select signal, illustrated by a dashed line, applied to the RF front end 905, so as to control frequency diversity reception when frequency diversity is employed in the transceiver of Figure 9, as will be discussed.
- the transceiver of Figure 9 includes a power control mechanism 925 that is controlled by the states determined in the timing and state control mechanism 921 , so as to provide a power management function for the transceiver. More particularly, when the transceiver is operated in selected states, where not all of the components, such as the RF front end 905, are required for successful operation, the power control mechanism 925, places the selected components in a reduced power consumption mode of operation. Although not shown for clarity purposes in Figure 9, the power control mechanism 925 is operatively coupled to a battery pack 1003 ( Figure 10) and to each of the active components in the transceiver illustrated in Figure 9.
- the power control mechanism can remove power from the RF front- end 905, transmitter 929 and the entire, or subsections of, the digital signal processing section 908.
- the transmitter 929 that is connected to a transmit antenna 931 , which may be a separate element, but preferably is the same as antenna 901 or 903 with an accompanying diplexer (not shown).
- the transmitter 929 is provided with an external data source as shown, and derives time and frequency information from the receiver time reference 927 such that transmissions by the transmitter 929 will also be subject to the timing uncertainties caused by low cost receiver time reference 927.
- the transmit feature associated with the transmitter 929, and the waveform produced therein are discussed in U.S. Patent
- Figure 10 is a plan view ofthe credit card outline transceiver 1000 as was discussed in Figure 9.
- the two dimensional footprint ofthe credit card outline transceiver 1000 includes a length in an X direction of about 3 A", and a width in a Y direction of about 2J" as shown. A thickness (not shown) is roughly A".
- the battery pack 1003 connects to the credit card outline transceiver 1000 via a connector 1002 as shown.
- the battery pack 1003 includes two external 3.6V lithium thionyl chloride (LiSOCL) cells (such as a LS- 14500 cell available from Faft Co ⁇ oration), which provide sufficient power to operate the transceiver, as discussed herein, for multiple years.
- LiSOCL lithium thionyl chloride
- the data source and data sink on the credit card transceiver shown in Figure 9, is provided via bidirectional interface 1004 as shown in Figure 10.
- the connector includes a serial interface such as a
- RS232C pseudo RS232C (0-5 V RS232C) or other interfaces such as RS-485.
- other interfaces may also be suitable, such as universal serial bus USB, Fire Wire (IEEE 1394), and other data interfaces available in data communication equipment.
- Selecting Sequence Length Based on Prime Factors The process gain that a radio exhibits is driven by the length of the spreading sequence.
- the present invention uses the class of codes refe ⁇ ed to as maximal length (ML) sequences, due to their co ⁇ elation properties, and preferably a 63-bit ML sequence.
- ML sequences are always of length 2 k -l, where k is any positive integer.
- the process gain associated with a particular spreading sequence is 201og(n), where n is the length ofthe spreading sequence. Longer spreading sequences allow for more process gain; but require more computational loading to achieve correlation .
- the present invention does not attempt to achieve the greatest possible processing gain (because too much processing power is required) but provides a reasonable amount of processing gain that can be realized with limited computational resources.
- code phase refers to an alignment ofthe code chips used to spread the signal relative to the code chips ofthe PN code generated locally at the transceiver
- code phase refers to an alignment ofthe code chips used to spread the signal relative to the code chips ofthe PN code generated locally at the transceiver
- the present invention uses decimation m the time domam and Founer transforms in the frequency domain to achieve this result
- the present invention utilizes partial decimation (1 e , multiple decimation stages distnubbed throughout the transceiver) and partial transformation techniques to reduce computational loading These techniques are enabled by selection of length ofthe spreading sequence that can be factored into pnme numbers In the preferred embodiment, a code length of 63 is selected and can be factored into prime numbers 3, 3, and 7 Table 3 depicts ML sequences of length 2 k -l for k up to 13, as well as the number of prune factors for each length and a processing gain associated with each code length
- Another computational efficiency feature offered by a code sequence that is factorable by multiple pnme numbers is that increase flexibility is achieved in selectmg intermediate decimation factors This in turn enables flexibility m the number and position of decimation, filtering, and downconversion processes employed in the transceiver Single Channel Receiver Partial Decimation Method
- the single channel embodiment of this invention employs a distributed (partial) decimation scheme configured to reduce the Nyquist bandwidth ofthe signal to equal the frequency uncertainty caused by inaccurate frequency references in the transmitter and receiver
- the signal is sampled at 4 times the chip rate (l e , the number of chips per second applied in the despreading stage), downconverted and decimated by 4 immediately so as to drop the resultmg sample rate to 1 2 MHZ
- the signal is correlated (despread) and subsequently decimated again to drop the Nyquist bandwidth to ⁇ 57 6 kHz, which m the preferred embodiment is the frequency uncertainty bandwidth (BW)
- the digital signal processing flow for the receiver portion ofthe transceiver shown in Figure 9 is depicted in Figure 11 In Figure 11, a signal of interest lies at an IF frequency of 49 2 MHZ and is applied to an input 1102 of a ADC 1104 at a sampling frequency of 4 8 MHZ (1106)
- 1116Q and decimation blocks 11181 and 1118Q Code co ⁇ elation is performed as the signal from PN code generator 1120 is mixed in 11221 and 1122Q to generate correlated I and Q data streams This data is further filtered by low pass filters 11241 and 1124Q and then decimated by elements 11261 and 1126Q
- the resulting I and Q data streams form a set of partial decimation sums, each sum being the co ⁇ elation of 42 processed samples
- the decimation from the sample rate with 252 points to 6 points reduces the effective Nyquist bandwidth for the signal and sets the predetection bandwidth to 115 kHz
- the magnitude ofthe resulting signal power is calculated by respective squaring mechanisms 1128 I and 1128 Q and summation blocks 11301, 1130Q, and 1132
- the result is signal a 1134, which is a magnitude scalar value representative ofthe correlated signal power m a 115 kHz noise bandwidth
- the leftmost portion of Figure 11 performs the quadrature downconversion and partial decimation
- the nght portion of Figure 11 performs the subsequent despreading and decimation required to limit the noise bandwidth and achieve maximum sensitivity, while spanning a frequency uncertainty of 115 kHz Alternating a dec ⁇ mate-by-10 operation followed by a dec ⁇ mate-by-11 operation, three times in succession, realizes the dec ⁇ mate-by-10 5 block 1126 in Figure 11
- the resultmg 6 data points of I and 6 data points of Q are squared, thus destroying their phase relationship pnor to final decimation which is performed as a summing function
- further techniques for limiting noise bandwidth is prevented so that the subsequent summation yields a predetection noise bandwidth of 115 kHz
- the wide predetection noise bandwidth of 115 kHz which is much larger than the approximately 19 2 kHz baseband signal is needed because the exact position ofthe baseband signal cannot be a pno ⁇ predicted with any degree of certainty, owing to the inaccuracy of
- the ADC 1104 is a 1-bit sampled luniter
- a multi-bit ADC may also, albeit at greater expense and possible requirement that an Automatic Gain Function (AGC) function be used to avoid applying the signal at a level that is outside ofthe multi-bit ACC's dynamic range
- AGC Automatic Gain Function
- the overall noise contnbution due to IF slew limiting and aperture jitter is evaluated to ensure that remaming dynamic range supports signal processing requirements
- the dynamic range must be able to receive both noise and at least 18 dB (and preferably 36 dB) of signal Because the low-cost embodiment ofthe instant invention is a 1 -bit limited system, the dynamic range ofthe system is hmited to the process gam of 18 dB But since the system can also produce earner insertion for jamming signals, the theoretic process gain against a frequency coincident jamming signal is 36 dB
- the resulting spectrum following digitization is centered at +'/ 4 Fs so as to maximize distance to the nearest image (as was discussed in reference to Figure 3) Additional images exist at -% Fs as well as - VA FS Because the signal is sampled real, the image is ideally centered m the Nyquist bandwidth prior to final downconversion as shown previously m Figure 3
- the final conversion to baseband must be performed in quadrature to ensure that negative images do not overlap
- the digitized signal is downconverted to baseband using a half-mixer, as discussed m reference to the background art
- the present invention completes the signal downconversion operation by moving the quadrature signal centered at Fs/4 (1 e , 1 2 MHZ) to baseband (I e , 0 Hz), as performed with components 1110, 1112 and 1114
- Figure 11 illustrates the sampled limiter (l e , ADC) 1104 as a mixer because the sampled miter
- IF 1004 is operating as a harmonic sampler and thus also downconverts the IF centered at 49 2 MHZ Several IF frequencies are preferred based on the availability of inexpensive surface acoustic wave (SAW) filters
- Inexpensive bandpass SAW filters enable the harmonic sampling technique due to their sharp roll-off and excellent ultimate rejection characteristics 10 8 MHZ is very near the standard SAW frequency of 10 7
- MHZ used widely as a communication IF 34 8 MHZ is ideal due to SAW filters that are present in many color televisions 49 2 MHZ, the prefe ⁇ ed embodiment, is also ideal due to the volume of portable telephones using this frequency 70 MHZ SAW filters are also available, but the harmonic multiplicand
- the 10th harmonic multiplicand ofthe sample rate 1106 of 4 8 MHZ creates a mixing tone at 48 MHZ, the difference yielding the digitized downconverted image 1108 centered at 1 2
- the half-mixer (1144) performs a complex translation ofthe real signal centered at 1 2 MHZ and completes the downconversion to the baseband signal at 0 Hz
- the downconversion tone 1110 is realized digitally as a series of values of 1 2 MHZ as sampled at 4 8 MHZ, which in turn defines a 4 1 relationship between Fs and the IF center frequency (Fc)
- This 4 1 relationship enables a particularly efficient downconversion operation because a coefficient set for the I (In phase) data downconversion mixer may be represented as follows
- the half-mixer multipliers 11141 and 1114Q become simple XOR gates for single-bit data
- the resulting complex signal 11131 and 1113Q at the input to the lowpass filters 11161 and 1116Q have a Nyquist bandwidth of 2 4 MHZ
- the time resolution provides ' ⁇ -chip steps for fine search by skippmg or reusing a data point
- the fine search algorithm uses this technique to co ⁇ elate the incoming signal against a fixed PN at %-ch ⁇ p resolution
- Coarse search does not require '/4-ch ⁇ p time resolution Rather, a reduction of data and co ⁇ espondmg computational loading is realized by decimating the complex signal to the chip rate
- Figure 11 performs this function in the lowpass filters 11161 and 1116Q and decrmators 11181 and 1118Q
- Decimation-in-time processes may be viewed as providmg mixmg and sampling operations
- Filters 11161 and 1116Q are used to reject unwanted images that exist in the digitized spectrum separated by the Nyquist bandwidth, m this case 2 4 MHZ
- Decimate-by-four 11181 and 1118Q mechanisms follow the filters 11161 and 1116Q so as to lower the effective sample rate to 1 2 MHZ, shown as signals 1 1 191 and 1119Q
- the decimation process immediately following the half-mixer may be realized as a simple adder that adds every other sample, ignoring the products containing zero coefficients
- the combined downconversion decimation block is therefore optimized for minimized computation and signal processing load, reducing multipliers to single XOR gates and the decimators to simple adders
- the entire downconversion decimation process is performed without any mathematical processmg operations being performed on samples originating from a one-bit ADC converter
- Specific signal processmg functions are avoided by using two 16-element lookup tables and indirect addressmg based on a serialized 4-bit nibble
- the 16-element lookup tables may be implemented in semiconductor memory or other mechanism for holding database entnes (such as boolean operators, as will be discussed)
- database entnes such as boolean operators, as will be discussed
- Data structures for the database entnes are shown m Tables 1 and 2, where respective fields of the respective data structures include decimated and downconverted data samples corresponding to particular sets of pre-decimated samples
- Figure 12 depicts a digitizing system that would use this technique replacing the half mixer and decimate operators of Figure 11
- a signal of interest 1202 lies at an IF frequency of 49 2 MHZ and is sampled by the 1 bit ADC 1204 at a sampling frequency of 4 8 MHZ (1206)
- the resulting signal 1208 is at a near baseband frequency of 1 2 MHZ with a sampling rate of 4 8 MHZ Because the sampling rate is four times the code repetition rate, four samples represent a single code chip
- These four samples are converted into parallel by the senal-to-parallel converter 1210 and then passed to a database implemented as the lookup tables 1212 I and 1212 Q implemented as semiconductor memory
- the four parallel samples are used as the address input (address or database indica) of these lookup tables 12121 and 1212Q
- the four address bits are weighted accordmg to the I coefficients (1, 0, -1, 0) and the co ⁇ espondmg Q coefficients (0, 1, 0, -1) to produce the
- the I data only uses alternating data points exclusive ofthe Q data (unused points are shaded gray in Table 1), and therefore, Table 1 collapses into two 4-element tables as shown m Table 2 Conversely, m systems where additional memory is available, the shift register 1210 can be expanded and the table appropnately increased in scale to perform a wide vanety of decimation ratios and downconversion tones For example, if the Fs to Fc ratio were 8 1 , eight samples ofthe data would be sufficient for multiplication
- the shift register 1210 would be lengthened to 8, and the lookup table would have 256 values
- the data width of the output would be scaleable, and the quantization e ⁇ or would be predictable and programmed into the lookup table
- This quantization e ⁇ or is not a problem in the case of 4 1 ratios because the coefficients are integer Fractional coefficients. however, create a need to represent non-integer decimation results
- the output of the lookup table can represent the fractional results to whatever resolution is required by the system implementation at the cost of widening the datapath (e g , a bus)
- Table 2 The example in Figure 12 uses a 16-element table that holds the sum ofthe two valid samples in a two-bit result. Processors that have an abundance of memory and excellent memory access operations but do not have fast multiply-accumulators will benefit from this technique. This enables the class of general pu ⁇ ose microcontrollers to perform "DSP" functions without the need of fast multiply-accumulator operations.
- Table 2 In another alternative, reference is made to data in Table 2, where the resulting I data and Q data are simplified into logical combinations ofthe input samples.
- the lookup table itself can be replaced with a few logic gates (serving as the database, which is a hardwired, preprogrammed alternative to the semiconductor database of Figure 12) implemented in the decimation stage. The Boolean logic expression for these is given by:
- a signal of interest 1302 lies at an IF frequency of 49.2 MHZ and is sampled by the 1 bit ADC 1304 at a sampling frequency of 4.8 MHZ (1306).
- a center ofthe resulting signal 1308 is above a baseband frequency by about 1.2 MHZ and represented with a stream of samples at a sampling rate of 4.8 MHZ. Because the sampling rate is four times the code repetition rate (i.e., a rate at which the PN code repeats itself), four samples correspond to a single code chip interval. These four samples are converted into a parallel representation by the serial-to-parallel converter 1310 and then passed to Boolean logic blocks 13121 and 1312Q.
- the combinatorial block 13121 performs the same function as the lookup table and produces a decimated, downconverted signal.
- a divide-by-four device 1316 serves to clock latches 13141 and 1314Q so to produce the decimated, downconverted output data samples as 13181 and 1318Q.
- Another alternative approach for implementing the quadrature downconversion and decimation function uses a signal processing engine such as a DSP or other processor to perform this function as the data is read from the sampling device.
- a signal processing engine such as a DSP or other processor to perform this function as the data is read from the sampling device.
- the processor combines the 4:1 downconversion ratio efficiencies discussed previously with the data collection and decimation to perform the downconversion, despreading and decimation process without the need for storing any data coefficients . This is particularly useful for processors with limited RAM memory such as very inexpensive processors or a hardware state-machine implementation (as implemented in a programmable logic device--
- Coefficient-less decimation, downconversion and despreading as implemented in the present embodiment is based on the processor's ability to sign-accumulate data as read from the sampling device Two parallel interleaved processes are executed to compute the inphase and quadrature data streams
- an in-line execution process is performed that adds/subtracts m the accumulation process to represent multiplication by 1 or -1
- the in-line code itself serves as the database repository for the resulting downconverted, despread, and decimated samples So as to further illustrate to explain this technique, exemplary pseudo-code for the in-line code is listed below
- a single processor can interleave the inphase and quadrature functions if there exists multiple accumulators or registers in the processor to hold intermediate values
- the above instructions would be modified to replace the "A" register with a "B" register Either multiple accumulators, context switched register files or temporary storage of intermediate values performs this function
- the downconversion and decimation algonthm may be encoded into the firmware without using any data store For example, if the processor executed four instructions per sample, the downconversion and decimation function becomes as follows
- the above pseudo-code performs a quadrature downconversion and 4 1 decimation on an input data stream It is repeated as in-line code for however many iterations necessary to correspond with a symbol interval
- the NOP instructions are replaced with instructions for performing concurrent processes, such as moving data or subsequent signal processmg
- despreading could be combined with the method where the spreadmg code inverts the sign of accumulation on a chip by chip basis For chips where the spreadmg code is a "1", the above described process leaves the resultmg sample unchanged For chips where the spreading code is a "0", the above process sign inverts the decimated result pnor to performing the STORE operation, or alternatively the LOAD and SUBTRACT functions could be replaced with a LOAD NEGATIVE and ACCUM instruction where the data is sign inverted on the initial read and accumulated on the second sample instead of subtracted
- the code becomes an m-hne algonthm where the length ofthe algonthm extends to the encompass the received signal spreading code Because multiplication is an associative operation, the downconversion and decimation functions can be performed concurrently even if the downconversion and oversample ratios are different The downconversion ratio is given by the ratio of
- oversample ratio is given by a ratio of Fs to the frequency of chippmg rate, F ch ⁇ p which may be any integer number
- the present embodiment uses an oversample rate of 4 1, but a 5 1 is used m the multichannel embodunent (discussed later) Table 3 depicts how the associative property of multiplication allows for simultaneous downconvert and despread without the need for coefficient store
- the decimation ratio becomes a straight-forward operation in that the accumulated sum may be stored as an intermediate partial decimation result at any integer number of samples This provides for intermediate decimation results for setting a predetection noise bandwidth similarly for the quadrature data For example, assuming the receiver is already PN aligned with the received signal and demodulating the signal, the 252 samples may be decimated by 42, 1 e .
- the sampled signal interval is initially decimated to a sampling rate equal to the chipping rate Durmg coarse search mode, before the signal is aligned with the PN code, the sampled data is mixed with the PN code at increments of 1-ch ⁇ p steps
- the co ⁇ elation result is bandwidth limited down to the predetection bandwidth so as to determine if that particular spreading code position resulted in a high co ⁇ elation result, indicative of code alignment
- decimation filter is included pnor to the decimation step to ensure that alias images do not destroy system performance Also, this filter should attenuate the desired signal to a mmimal extent because the signal may still contain mismatches in PN alignment
- a boxcar averaging filter is used as the decimation filter
- a boxcar averaging filter has a rectangular time domain window characteristic and therefore maximizes co ⁇ elation gain derived near the sample wmdow discontinuities
- the boxcar averaging decimation filters implemented in the preferred embodiment are unitary scaled at the window discontinuities In the frequency domam, this is a sine function, which is characteristic of a transfer function of the decimation filter, having a roll-off that is a function of the decimation frequency Because the transfer function will have a rounded shape, signals that are not centered in the middle ofthe transfer function will be attenuated by an amount corresponding to a frequency offset error imparted on the transmit signal by the inaccurate frequency reference employed by the transmitter while forming and transmitting the signal
- the present embodiment reduces the effects of decimation loss as a way to keep from incurring as much as 3 9 dB loss for transmitters that have a significant frequency offset error that place the transmitted signal at the edge ofthe detection bandwidth, Nyquist band edge
- decimation loss due to a filtenng effect
- Curve 1402 in Figure 14 represents how a frequency uncertainty e ⁇ or imparted on the received signal will reduce a signal power in an initial downconversion and decimation operation
- the frequency ofthe transmitted signal is close to the Nyquist band edge, (l e , at a left hand side or right hand side ofthe "transmitter frequency uncertainty range", as illustrated) the receiver will suffer a 3 9 dB loss in signal power, which, among other things, will inhibit the receiver's ability to align the signal
- a co ⁇ ection is then made to the downconversion tone so as to shift the frequency of the receiver by ⁇ l A the frequency uncertainty
- the effective signal loss ofthe transmitter will then be represented by either curve 1404 or 1406 depending on whether the signal is shifted up or down in frequency
- the processor determines that the transmitter frequency e ⁇ or exceeds at least 50% of the decimation bandwidth, the downconversion tone is altered by ⁇ 50% of the Nyquist bandwidth, which moves the desired signal from the center to 50%
- the resultmg effect is that depicted m Figure 14 of moving the decimation center by ⁇ 50% where it can be seen that the worst case decimation loss is limited to 9 dB This shifting operation recovers 3 dB at band edge relative to usmg the center channel alone
- the added step of altering the digital downconversion tone adds complexity to the receiver because the downconversion coefficients become a complex tone sampled at the ADC rate
- the sign ofthe tone is a function of whether the I component leads or lags the Q component
- the tone should be 50% ofthe decimation bandwidth so as to limit loss to 9 dB
- a tone close to 9 dB will yield similar results and may improve computational efficiencies m performing the downconversion
- the coefficient set may be represented by only a portion ofthe cycle For example, 252 data samples would be collected if the sample rate were 4 tunes the chip rate for a 63 chip sequence The sample rate is approximately 4 8 MHZ, so a downconversion tone equal to Fs/4 would repeat every 4 samples, thus the coefficient set need only be 4 samples long Only l A cycle ofthe downconversion tone need be stored as coefficients smce the I and Q processes access the same coefficient set in offset sequence The order and the sign of coefficient retrieval completes the
- a second approach for correcting the frequency of an incoming signal is to adjust the downconversion frequency in the 1st local oscillator This is accomplished by programming the conventional LO synthesizer of Figure 8 to a new frequency
- the synchronization search process is modifiable m yet another method for reducing frequency uncertamty decimation loss
- the digital or RF/IF frequency co ⁇ ection was made following initial search and trip determination
- there exists a significant loss of signal power at the frequency uncertainty band edge This loss also has an adverse impact for signal detection
- the previous discussion makes the assumption that the signal can first be detected and roughly located so an appropnate correction be made to limit the loss for demodulation
- SNR signal-to-noise ratio
- the detection process is enhancable by inco ⁇ orating the techniques discussed above into the search process.
- One method for improving detection at band edge is to subdivide the frequency uncertainty band into a set of center frequencies which set the worst case loss for decimation loss at tolerable limits.
- Lines 1404 and 1406 represent 2 center frequencies which will perform this task.
- the search process simply makes an adjustment, alternating between these two candidate frequencies.
- frequency selection can be made either in the digital downconversion or in a RF/IF downconversion step.
- the signal leader (or preamble, as will be discussed) or synchronization interval needs to have sufficient duration for all candidate frequencies to be evaluated.
- both lobes may be simultaneously performed, the two lobes being depicted in Figure
- Another method for improving band edge sensitivity is averaging, which as discussed later herein, is a technique for improving sensitivity across the predetection bandwidth, including the frequency uncertainty band edge.
- Optimal sensitivity can be achieved using averaging, band limiting and frequency adjustments as discussed above at the cost of system complexity, transmitted duration and receive algorithmic loading.
- the signal amplitude information is stripped, and thus, except for signals which are at the same relative power as thermal noise, all signals appear in the final co ⁇ elation function at the same relative power level. Because of this, a simplified threshold mechanism searches only the maximum and compares it to an absolute threshold, thus skipping a noise estimation process.
- the correlation (or despreading) task is performed in software at the minimum frequency possible, namely the chipping rate
- Direct sequence receivers align the receiver PN code with the transmitter PN code (as represented in the received signal) in order to realize the process gain
- This search process can be performed senally by evaluating a sampled data set with respect to a given receiver code phase, stepping the code phase by one chip, and repeatmg the process until a power mcrease is noted Smce the information provided by the correlation function is relevant for only a 1 chip width ofthe PN code, the co ⁇ elation process must be repeated so as to cover each possible chip location Because the code length in the present embodiment is 63 chips long, a serial search approach would require as many as 63 steps before alignment is attained So as to assist in code alignment, the transmitter transmits, as a first part ofthe direct sequence spread spectrum signal, a leader which is a repeated copy ofthe PN code
- Figures 15A-B help illustrate this alignment process, where Figure 15A depicts the transmitter power over time For an ASK data modulation (such as on-off-keying for binary channel symbols), the transmitter keys-on at
- Figure 15B depicts the received power developed in the receiver corresponding to the transmitted signal An mcrease in transmitted power is detected at point 1506 Signal correlation is achieved at point 1508, which is the initial trip event Because the search process steps in one chip mcrements (or multiples thereof), the resultmg trip alignment up to point 1508 will be within Vi chip This degree of alignment is insufficient because a Vz chip offset error represents a 6 dB process gam loss Consequently, to improve performance by further limiting alignment loss, a fine search process follows the course search so as to resolve the code misalignment to within a small fraction of a chip, which is accomplished at a time 1510 Once fine search is performed, the receiver waits until a tune 1512 to begin receivmg the ASK data
- the present embodiment uses the fast serial search to achieve initial t ⁇ p
- This approach offers a preferred trade-off of performance versus computational complexitv in the first embodiment
- the fast senal search operates m the receiver in the tune domain by collecting and sto ⁇ ng one code repetition interval (I e , one portion ofthe leader that corresponds m length to a PN code repetition)
- I e one code repetition interval
- the receiver initiates a real-tune clock and then sequentially steps the PN code in one-chip steps agamst the collected and stored data until the portion of received signal has been correlated with all 63 code positions
- the maximum correlation power is determined along with the associated phase position ofthe PN code that generated the maxima
- the t ⁇ p condition would require that the maximum value exceed the average ofthe remaining values by a predetermined threshold
- the tnp condition may optionally use a predetermined threshold because systems with a sampled limiter are
- This fast serial search process has several key advantages for digital receivers as implemented in the present invention Because the receiver only collects one code repetition, the RF front-end may be powered down dunng the subsequent DSP search, savmg battery life Also, the physical collection of data as descnbed in the serial search consumes much ofthe processors computational bandwidth By halting the collection process, the computational bandwidth is recovered in the present invention Even with low- cost DSP processors, the search tune is reduced from 63 code periods to approximately 10 The transmitter leader can therefore be reduced, extending transmitter battery life
- the fast senal search is performed in less than 14 the time required to transmit the leader so as to ensure detection by the receiver Moreover, assuming that a first sampled bit was collected immediately before the key-on ofthe transmitter, I e , time 1502 m Figure 15A
- the receiver's search process will not report a tnp event because the receiver's locally generated PN code will be compared to an incomplete portion ofthe transmitters PN code contained in the leader Under these conditions, if the receiver spends more than 14 the leader transmit time performing the search, the next portion ofthe leader sampled by the receiver would he past a mid-point ofthe leader, and thus the receiver would once again fail to synchronize with the transmitted signal because the receiver would be attempting to correlate based on a portion ofthe transmitters PN sequence, contamed at the end ofthe leader, and a beginning portion ofthe ASK data contamed in the transmitted signal Moreover, the new search would extend into the data section of transmission and the receiver would not be ready to demodul
- Figure 16 is a flowchart explaining the steps performed in the fast serial search process
- the process beings in step 1605 and proceeds to step 1610, where a data record corresponding to a PN code length is captured and stored in memory
- the process proceeds to step 1615, where an initial PN sequence phase is set to zero
- the data sample is co ⁇ elated agamst the current PN sequence and the result is stored in step 1620, subsequently, the PN sequence phase is mcremented by one m step 1625
- a decision block is performed in step 1630 wherem the process determines whether or not the data sample has been correlated agamst all possible PN sequence phase positions If the data sample has not been co ⁇ elatcd agamst all possible PN sequence phase positions, the process returns to step 1620 to correlate the data agamst the next PN phase position If the data sample has been correlated against all possible PN sequence phase positions, the process continues to step 1635 wherein the maximum value of the 63 co ⁇ elation calculations is
- alterative steps include stepping the PN code relative to the data, data relative to the PN code or both, because the relative phase positions is the relevant information sought in the co ⁇ elation process.
- the receiver aligns the two spreading codes as closely as possible, therefore maximizing the signal strength ofthe received spread spectrum signal. So as to more closely align the two spreading codes, the receiver of the present embodiment initiates a fine search process wherein the receiver changes the spreading code by fractional chips and attempts to establish a better code alignment.
- the processor slips or advances a single sample by 1/4 chip intervals. Because the processor executes several instructions per sample interval, a fraction ofthe 1/4 chip step is achieved by hesitating instruction intervals combined with slipping samples. In the prefe ⁇ ed embodiment, the processor controls the sample clock to the ADC, so that the processor executes 4 instructions per sample. Therefore, the processor can affect a slip ofthe locally generated PN code relative to transmit PN code (as represented in the received portion ofthe leader) by 1/16 of a chip by inserting a single NOP instruction into the bit- time processing loop.
- Figure 17 shows a "real world" fine search process, to be contrasted with the ideal co ⁇ elation process discussed in reference to Figure 7.
- the solid triangular line 1705 represents the ideal correlation peak, and the vertical lines 1710 at each fractional chip phase position show the potential signal drift due to instantaneous noise.
- the dashed line 1720 shows an example of a fine search process in the presence of noise.
- Conventional fine search algorithms correlate each relative code position with the data sample, and then choose the code position that generates the highest signal level. In Figure 17, such an algorithm will result in a % chip e ⁇ or, resulting in a mean 2.5 dB signal loss; the e ⁇ or will resulting from the process detecting that correlation occurred at position 1730 rather than 1725.
- the standard deviation ofthe noise becomes a significant factor in identifying the true correlation peak. More particularly, a larger standard deviation noise will cause the lengths of the vertical lines 1710 to increase causing greater numbers of co ⁇ elation e ⁇ ors in the serial fine search process.
- a conventional method to overcome the effects of instantaneous noise is to dwell on each fine search position for more than one code period and average the values.
- a disadvantage to this method, for battery operated applications is that increased amounts of transmitter leader time is required to obtain enough samples to average.
- a goal of the fine search algorithm in the present embodiment is to obtain the best possible spreading code correlation as quickly as possible.
- the receiver ofthe present embodiment dwells on each fractional spreading code position for only one code period, but does not select the strongest signal out ofthe data set.
- the present fine sync process uses both chip offset and correlation strength of the entire data set to determine the ideal code alignment.
- application of a center of mass operation on this entire data set improves fine search accuracy.
- Alternative operations including least squares, curvefitting and convolution may be used, but are less computationally efficient in the present application.
- Figure 18 shows the results of three different search processes evaluated over several hundred fine search passes on real data containing noise. These processes slip the phase position of the receiver despreading code by 1/5 chip steps, and seven discrete positions are used (-3/5, -2/5, -1/5, 0, +1/5, +2/5, and +3/5 ) . Because the initial trip can occur within 14 chip ofthe transmitted spreading code, the respective processes at least include data from -14 chip to +14 chip ofthe trip position. Also, the processes may utilize any fractional value, keeping in mind that smaller fractional positions may yield a better result but will require more data samples as well as require more computational power.
- the "Peak 7" process searches the 7 different chip phase positions and selects the maximum signal value.
- the "Peak 7" line 1810 depicts the results when the maximum signal strength value is selected from the 7 chip positions. Note that even though the initial trip sometimes occurs at the best possible code alignment, the fine search process will, on the average, result in a 1.5 to 2.0 dB loss in received signal.
- CM 7 This process has been previously implemented. Inventive methods described as "CM 7" and “CM 7+” algorithms have an effect of averaging out the noise of 7 bit times without dwelling on each chip position for 7 bit times.
- the "CM 7" process calculates the center of mass ofthe 7 different chip positions and selects the chip value which coincides with the center of mass. This process works well if the initial trip is within 1/5 of a chip of the ideal relative code phase position. However, if the initial trip is greater than 1/5 of a chip from the ideal position, the co ⁇ elation loss becomes severe, as seen at the end points of curve 1820 of Figure 18. This shortcoming is addressed in the CM7+ process, explained below.
- the "CM 7+" process is a conditional two-step process. If the initial trip and subsequent center of mass calculation results in a fine search adjustment of less than 1/5 chip, then the condition is satisfied. If, however, the center of mass calculation shows that the initial trip error was greater than 1/5 chip, then the process moves the trip location by 2/5 chips, collects new data points out to 1 chip from the initial trip position, and re-calculates the center of mass, by re-using 5 ofthe first correlation sums. The fine search error results in less than a .75 dB loss, as seen on curve 1830 of Figure 18.
- Steps in the "CM 7+" algorithm are explained with reference to Figure 19 where the method begins in steps 1905 and then 1910, where an initial PN sequence phase is set to the initial trip phase minus 3/5 of a chip.
- the process proceeds to step 1915, where one code period of data is taken and stored.
- the data sample is correlated against the current PN sequence and stored in step 1920; subsequently, the PN sequence phase is incremented by 1/5 of a chip in step 1925.
- a decision block is performed in step 1930 wherein the process determines whether or not the data sample has been co ⁇ elated against all seven fractional phase positions . If the data sample has not been co ⁇ elated against all fractional code chip phase positions, the process returns to step 1920 to co ⁇ elate the data against the next phase position.
- step 1935 the process continues to step 1935 wherein the center of mass calculation is performed.
- the process proceeds to step 1940, where the center of mass result is compared against the initial trip value. If the center of mass indicates that the fine search position is within 1/5 of a chip ofthe coarse search position, then the algorithm proceeds to step 1945 to begin the demodulation process. If the center of mass indicates that the fine search position is more than 1/5 of a chip away from the coarse search position, then the algorithm proceeds to step 1950, where the algorithm recenters the trip location by 2/5 of a chip, collects new data points, and recomputes the center of mass. As stated earlier, other algorithms such as least squares, curve fitting, and convolution can also be used to implement this fine search technique. Center of Mass 9
- a variant ofthe fine sync process uses the decimation process to acquire a minimum of data points and gives a reasonable trade-off between accuracy and computational loading
- the initial code phase will be withm 14 chip of the ideal code phase position
- the process as descnbed below, uses a sample rate (Fs) at 4x the chippmg rate
- a data sample Once a data sample is acquired, it can be co ⁇ elated agamst different phases ofthe spreadmg code, and, if not decimated, the data sample can be co ⁇ elated agamst all fractional code phase positions, provided that a fractional resolution of the spreadmg code equals the sampling rate of the data
- This approach requires storage of a single data sample with a duration equal to the code repetition
- the initial downconversion and decimation process is performed prior to despreading and the result is a data set containing one element for each chip of the spreading sequence
- This data set is used m coarse search where all possible combinations ofthe phase of the spreadmg code are used to determine if a trip event occurs, and thus the coarse search step resolution is in integer chip steps
- the receiver ofthe present embodiment re-uses the decimation process in the fine search process Multiple data samples are taken at fractional phase offsets so as to calculate the correlation power over the correlation peak
- This center of mass 9 process is explamed with reference to the flowchart of Figure 20
- the process begins in step 2005 and then block 2010 where a first data sample is acquired at a 4 1 multiple ofthe chip rate and then decimated to the chip rate This data sample is co ⁇ elated three times in block 2011 with the spreadmg code at - 1 , 0, and + 1 chip offsets from the initial tnp position
- the spreading code is adjusted by +14 chip from the initial tnp phase position
- a second data sample is acquired and then decimated to the chip rate
- This data sample is co ⁇ elated twice m block 2021 with the spreadmg code at -% and +14 chip offsets from the initial t ⁇ p position
- the spreadmg code is adjusted by +14 chip from the previously sampled phase position
- a third data sample is acquired and
- the center of mass calculation is performed on the co ⁇ elation results from the -1, -VA, -YI, -54, 0, +54, +54, +%, and +1 code phase offsets This calculation is used m step 2051 to establish the code position to receive and demodulate data m block 2052
- steps 2115, 2120, and 2130 may be removed from the process, although m this vanant all possible data pomts must now be calculated
- This alternative process is explained with reference to Figure 22 where the process begms in step 2205 and then 2210 where a data record is acquired at said multiple ofthe chip rate and stored for re-use
- the algonthm proceeds to block 2211 where the data is despread and power measured determined for mne relative code chip offsets of -1, -%, -14, -54, 0, +14, +14, +% and +1 chips where the 0 chip offset equals the initial trip phase
- the center of mass is calculated on the co ⁇ elation results from the -1, - 3 4, -14, -14, 0, +14, +14, +% and +1 code phase offset power measurements
- the process then proceeds to block 2240 where the relative phase ofthe receiver code generator
- On / Off Keyed (OOK) systems a subset of ASK modulation systems, use OOK modulation to format transmitted messages, and rely on an ability ofthe receiver to detect the presence or absence of energy coincident with particular bit (or symbol) times This is the extreme case for amplitude modulation where data is encoded linearly or at discrete amplitude steps relative to a peak value
- Hard-limited receivers are not typically used for ASK systems because hard-limited receivers use a detection mechanism that inherently strips the amplitude information from the signal.
- hard-limited systems are mostly used in phase or frequency modulated systems, where the data information is encoded in the phase of a carrier. Nonetheless, because ofthe hard limiting receiver's wide dynamic range, it is desirable to use it in a low-cost receiver to receive transmission from an OOK transmitter.
- a transmitter feature of the present embodiment implements on-off-keying by imposing a requirement to not only amplitude attenuate the signals during a "0" state, but also suspend the PN code generator used to spread the transmitted signal as shown in Figure 25, 2510, 2552.
- the receiver that uses a hard-limiter will not notice the amplitude key but it will be able to use the code on / code off aspect to make a determination between correlation sum and no co ⁇ elation sum.
- the bit state determination is therefore a function ofthe ability to produce process gain in the receiver.
- the receiver is relatively indifferent to amplitude changes, it may seem reasonable to modulate only by employing code on / code off, but not varying a power. However, it is presently identified that systems operating near power per unit bandwidth restrictions should not use this approach because removal ofthe code will cause the transmitted na ⁇ ow band signal to have a higher peak power roughly equal to the process gain. Otherwise, a combination of amplitude and code keying is desired to create a OOK transmitter which operates at controlled power spectral density.
- the present invention has scaleable embodiments that allow for increased system improvement for increase processing power and, perhaps, battery power. Accordingly, the several approaches discussed herein, in some instances, are specialized algorithms to acquire, synchronize, detect a trip condition and subsequently demodulate data using the least amount of computational resources. Processes that appear to be equivalent in function must be compared based on their computational efficiency, and related power draw for a particular application. To this end some processes disclosed herein may appear to be less elegant than known algorithms, but, as is often the case, these known, conventional algorithms presuppose that a certain amount of processing resources and power is available.
- Figure 23 is a flow chart of a top level receiver signal acquisition process, which is applicable to a battery mode of operation where "time to search" is triggered by a wake-up interval timer.
- the process of Figure 23 is also applicable to continuous search receivers that stay on line continuously where "time to search" merely is a start point in a continuous loop.
- the process begins in step 2305 arid then step 2310 where the receiver samples and stores one code period of data. Subsequently, the process proceeds to step 2315 where the antenna and/or frequency settings are selected for the subsequent search to allow for settling in the VCO, as will be discussed in reference to Figure 27. Alternatively, if averaging is used, these steps may be delayed until the last sample is taken so as to complete the average.
- the decision to perform antenna or frequency selection is an optional step and depends on the specific system requirements and architecture.
- the process continues at step 2325, where a coarse search process is performed. Coarse search may be any of the fast search methods discussed previously, or any known methods.
- step 2330 the process continues to step 2330 through branch 2331 and then branch 2333 is taken, where the steps of 2310 and 2325 are repeated until the proper amount of data has been sampled, stored, and averaged.
- Averaging is implemented on a single antenna and frequency setting; therefore, step 2315 is not repeated in the averaging algorithm.
- decision block 2335 a trip decision is made based on the process depicted in Figure 28 . If a trip is detected, then the receiver performs the fine search and demodulation processes in step 2340, where the fine search operation uses a center of mass algorithm discussed previously or other known methods.
- step 2345 the process decides whether or not to enter into sleep mode, based upon the receiver type. If the receiver is battery powered, the receiver will either go into sleep mode in step 2350, or return to step 2305 to repeat the signal acquisition process. If the receiver is externally powered, the receiver returns to step 2305. If in step 2335 a trip is not achieved, the process proceeds to step 2355 where the receiver verifies that the acquisition process has been performed for all possible antennas and frequencies. If not, the process returns to step 2310 to collect new data and select another antenna (if necessary) or another frequency (if necessary) 2315. From step 2355, the process proceeds to the sleep decision step 2345 only if all possible antennas and frequency values have been searched. Many possibilities exist for a specific path followed in process of Figure 23, depending on system requirements, transmitter leader length and averaging options. Nonetheless, the flexibility afforded by the scaleable approach for acquisition, trip and demodulation based on system requirements is evident.
- the present transceiver includes redundant receive antennas 901, 903 ( Figure 9) so as to offer recourse in overcoming signal fading or shadowing by allowing the antennas 901, 903 to be physically separated and or orthogonally polarized.
- the receiver utilizes the antennas 901 , 903 in acquisition to select the channel with greatest power for demodulation.
- Figure 24 depicts the antenna selection process, assuming the coarse search process has already been performed.
- the fine search process is complete with an optimal phase position calculated at time 2405 and verified at time 2410, all of which being performed using the same antenna.
- the alternate antenna is evaluated for reception, using the same PN phase that was selected at the end ofthe fine search process.
- the alternate port is selected and demodulation begins during interval 2430. The process is also repeated at various points throughout the data collection during bit periods where known symbols are expected.
- transmitters and receivers must overcome the effects of jammers.
- Many systems use time diversity, or data redundancy, to overcome the effects of instantaneous jammers.
- the transceiver ofthe present embodiment uses a frequency diversity scheme in an economical manner that does not force the requirement of a frequency synthesizer in a compatible transmit-only or transceiver device.
- Figure 25 is a block diagram of a DSSS transmitter that may be used to communicate with the receiver ofthe first embodiment or may be in the transmitter portion of a transceiver according to the first embodiment.
- the transmitter includes a frequency reference source 2502, which is low cost crystal having accuracy of 50 ppm (parts per million) e ⁇ or. This example shows one frequency reference for the entire transmitter, clock divider circuit 2504 produces a code clock signal 2506 for a data generator
- the data generator 2508 is implemented by a microprocessor, external source or other data source.
- the PN generator 2510 is also implemented, although it does not have to be, by the same device as data generator 2508.
- a Clock divider circuit 2512 produces a diversity clock signal
- the frequency diversity enable signal 2516 controls switch 2518 (implemented as an AND gate), either producing a logic "0" (2520 with diversity disabled) or passing the diversity clock signal (2522 with diversity enabled).
- the data generator 2508 generates a binary data stream 2524 at baseband and is combined with the PN code 2526 in the XOR gate 2528 so as to produce a waveform spectrum 2530, also at baseband. With frequency diversity enabled, the baseband signal is mixed in a second XOR gate 2532 with diversity enable signal 2522 and low-pass filtered 2534 to produce a signal with spectrum 2538.
- the second XOR gate 2532 and LPF 2534 serve as a buffer, producing a signal with spectrum 2536, which is identical to the signal with spectrum 2530.
- the output of frequency source 2502 is upconverted in upconverstion circuit 2540 to produce an
- RF ca ⁇ ier 2542 with a center frequency of about 915 MHZ (plus the frequency error of 2502 multiplied by the upconversion factor of 2540).
- the signal with spectrum 2536 is combined with the ca ⁇ ier 2542 in mixer 2544.
- This product is band-pass filtered in 2546 to produce a signal with single sine spectrum 2548 with a center frequency of about 915 MHZ.
- This signal is amplified at 2552 and transmitted from antenna 2554.
- the signal with spectrum 2538 is combined with the carrier 2542 in mixer
- This product is band-pass filtered in 2546 to produce a signal with dual sine spectrum 2550 with a center frequency of about 915 MHZ.
- This signal is amplified at 2552 and broadcast on antenna 2554.
- the generated signal will be as depicted in Figure 26B, with dual images 2601 and 2602 centered at about 915 MHZ.
- the signal power of either lobe of this signal is 3dB down from the power output ofthe signal from Figure 26A, because the signal power is now distributed in twice the bandwidth as the signal in Figure 26A.
- the receiver may select from either of two frequency components from which to retrieve the data signal.
- the receiver performs signal searches at all three frequency values, using the algorithm from Figure 27 to cycle through all possible frequency settings. This approach assumes a transmitter that alternates, or coexists with other transmitters, between diversity (Figure 26B) and no diversity ( Figure 26 A).
- the present receiver includes a select mechanism for selecting one of several receive frequencies. This mechanism is provided for two primary modes of operation. In the first mode, the receiver is tasked to use one of the available frequencies to select transmitters using that frequency band. This allows the receiver to be compatible with pools of transmitters separated by frequency to be selected through receive frequency tasking. The time to switch between frequencies is typically not critical in this mode of operation.
- the second mode of operation is intended to capture a transmitter pool (i.e., a group of one or more transmitters) that transmit simultaneously at different frequencies using the previously discussed frequency diversity process.
- a transmitter pool i.e., a group of one or more transmitters
- Such transmitters use this diversity technique where the signal is split and separated in frequency by a fixed amount.
- the receiver must monitor the two (or three) frequencies as part of the acquisition process. Because the frequency selection is integrated into the acquisition process, a timely transition between selection helps minimize transmitter leader time.
- This mode of operation adds diversity in frequency to increase the probability of data throughput in the presence of intentional or unintentional interference and multipath propagation. If a static interference signal and/or a fade exists at one ofthe transmitted frequencies, the other frequency may be used to demodulate the data.
- the receiver of the present embodiment uses this technique to improve throughput, quickly alternating search frequencies while processing a previous captured bit interval. By pipelining the process, the frequency transition time can be absorbed thus minimizing the impact on search time.
- Figures 27A-D depicts this receive acquisition schedule which includes the antenna and frequency diversity processes discussed above.
- Figure 27D depicts a transmitted signal and Figures 27A-C depict the receiver process used to acquire the signal.
- Figure 27A represents different candidate frequencies on which the receiver attempts to acquire the signal;
- Figure 27B represents the antennas on which the receiver attempts to acquire the signal;
- Figure 27C represents different samples obtained by the receiver and used by the receiver to determine if the transmitter is presently transmitting.
- the transmitter presents a leader (i.e., preamble) signal prior to data, where the leader is of sufficient duration to allow the receiver to evaluate all combinations of diversity provided for in the system architecture.
- the receiver samples data at times 2735 for one code period then processes the data using the fast serial search process for a duration 2737, lasting several code periods.
- the leader is of sufficient length that allows for the receiver to perform successive searches which coincide with all diversity combinations used in the system.
- Figure 28 depicts the benefit of averaging over successive co ⁇ elation processes to improve acquisition sensitivity.
- Each coarse search 2812, 2814, 2816, 2818 produces a cross correlation of the received signal and the PN code embedded in the receive coefficients, with 2810 being the average value over the previous N multiple searches.
- This process requires that subsequent samples are phase coherent to each other, meaning that the time relationship of the first sampled data point in each code period is identical.
- This phase coherency is obtained using a timer and/or counted state processes to ensure zero relative code phase alignment. Only the frequency reference drift is left uncompensated, but this drift is low relative to the time interval of search.
- the averaging is performed as a box-car or finite impulse response (FIR) filter structure where the last N symbols are averaged, or the averaging may be performed in an exponential or Infinite Impulse Response (IIR) averaging process where the previous results are decayed and added to a fraction of the current sample.
- IIR Infinite Impulse Response
- an exponential averaging process is used so as to minimize memory requirements because only the cu ⁇ ent sample plus one decaying average need be maintained.
- the weight "N" is 6 where the previous average is multiplied by 5/6 to decay the previous result, the current sample is multiplied by 1/6 and summed to the previous product. The result is stored for future decay and then passed to the trip decision process.
- Figure 29 depicts the reduction in false alarm rate for averaging 6 samples in the present single channel receiver embodiment.
- Curves 2910 and 2920 show the power distribution of noise in a 115 kHz noise bandwidth with and without averaging, respectively.
- Curves 2930 and 2940 show the power distribution of a -110 dBm signal in 115 kHz noise bandwidth with and without averaging, respectively. Improvement is visualized by comparing a minimized overlap of distributions (2920 and 2940, and 2910 and 2930) which is a measure of false alarm rate and degradation in bit error rate. The mean power for the noise and signal plus noise distributions remain unchanged, yet the deviations are reduced creating a greater miss distance between the minimum "On" and the maximum "Off' distributions.
- Averaging is only useful if coordinated with the leader length ofthe transmitter, and in the case of the present signal channel receiver embodiment, each coarse search operation takes less than 12 PN code intervals. Accordingly, averaging over 6 searches produces a maximum benefit after 72 code intervals. Because the leader length is 92 code intervals on the transmitter, this leaves 20 code intervals for fine search, AGC and overhead. In systems where the leader length must be reduced, the averaging time-base may be reduced accordingly. There is an asymptotic diminishing return on investment for averaging. Averaging two noise samples together reduces the noise deviations by 3 dB. To gain another 3 dB, the number of samples must be doubled to 4. Each significant reduction of noise deviations requires a doubling of time.
- the most effective average is, therefore, the first average and subsequent averages, while helpful, provide diminishing returns. Also, the improvement cannot exceed the mean signal to noise ratio (SNR) at the output ofthe bandpass filter preceding the magnitude computation. While averaging can improve trip sensitivity to overcome the greatest portion ofthe 3.9 dB loss at maximum frequency ambiguity due to decimation loss, the system performance and cost is at odds according to a trade off of sensitivity for leader length in the transmitter and power/computation loading in the receiver.
- SNR mean signal to noise ratio
- a "scalable" feature ofthe present invention is an adjustable data rate .
- Data rate may be increased in the receiver while using partial decimation coupled with data modulation transitions in the transmitter that occur at fractional PN code boundaries.
- a standard modulation method for transmitting data in the present inventive system is OOK where a data value "1" is represented by the presence of signal for a repetition ofthe PN code and a data value "0" is represented by the absence of signal for the same interval
- An alternative data modulation method is BPSK data where the signal is present for both “1" and “0” data symbols, yet the earner phase is inverted 180 degrees to delineate the data state
- the correlation sum will either sum positively or negatively depending on the arbitrary earner relationship at acquisition
- the data " 1 " is assigned the state dunng the preamble (leader) so that the PN sequence will be transmitted "in the clear”
- a Costas loop or other techmque for translating the received phase normal to that ofthe phase detector is used to create a maximum data miss distance and therefore maximize SNR
- phase mversion event marks a data state where the absence of inversion marks the alternate bit state
- the data rate can be increased by creatmg artificial symbol boundanes within the PN code
- the present transceiver system uses a 63 chip PN code length to represent a standard symbol, and therefore provides a data symbol (or data bit) rate of approximately 19 2
- the data rate can be effectively doubled by arbitrarily assigning the first 31 5 chips to one data symbol, and the second 31 5 chips to the second
- the transmitter must perform the BPSK or DPSK phase inversion at the 31 5 chip boundary or amplitude key the signal, and the receiver must perform the correlation process by parts (I e , treatmg the first 31 5 chips separate from the subsequent 31 5 chips)
- Boundary conditions are relatively arbitrary and data rates may be mcreased at any fractional code interval provided the rate divides evenly mto the code repeat rate or a multiple ofthe code repeat rate For example, it may be desirable to send three symbols over two code repeat intervals
- the transmitter and receiver need only have a synchronization method, or other prearranged agreement, to know when to expect phase mversion or keying ofthe earner
- Figure 30A depicts the maximum process gain available for a symbol rate equal to the code repeat rate resulting in 17.99 dB of process gain at a 19.2 kbits/sec data rate.
- FIG. 30B depicts the maximum process gain per symbol for a symbol rate equal to twice the code repeat rate. This effectively doubles the data rate to 38.4 kbits/sec with a co ⁇ esponding process gain maximum of 14.98 dB.
- Figure 30C depicts three symbols per code interval yielding a data rate of 57.6 kbits/sec with a maximum process gain of 13.22 dB.
- Figure 30D depicts four symbols per code interval yielding a data rate of 76.8 kbits/sec with a maximum process gain of 11.97 dB.
- Figure 30E depicts five symbols per code interval yielding a data rate of 96.0 kbits/sec with a maximum process gain of 10.97 dB.
- Figure 30E depicts six symbols per code interval yielding a data rate of 115.2 kbits/sec with a maximum process gain of 10.21 dB.
- Data demodulation may proceed after acquiring spreading code synchronization ofthe receiver to the transmitter. If the transmitter derives its spreading code sequence from the same frequency reference as its RF carrier, it is sufficient for the receiver to track the transmitter carrier so as to maintain spreading code synchronization throughout data demodulation. Also, to demodulate a phase modulated signal, it is prefe ⁇ ed to remove the effect ofthe carrier frequency e ⁇ or between transmitter and receiver.
- One way to remove the effect ofthe carrier frequency e ⁇ or between transmitter and receiver is to use conventional DBPSK demodulation augmented with frequency error co ⁇ ection. According to this approach, assume the received signal is despread, downconverted to baseband and decimated to a bandwidth greater than or equal to the frequency e ⁇ or as previously discussed. This is shown as 3100 in
- Figure 31 with 6 output samples C(n') 3105 per code period. Choi, Z. Y, Lee, Y. H, "Compensating Frequency Drift in DPSK Systems via Baseband Signal Processing", IEEE Transactions on Communications Vol. 45 No. 8, August 1997, pp 921-924, the contents of which is inco ⁇ orated herein by reference, discusses this techmque using one sample per code period as unduly limiting the frequency range that can be co ⁇ ected
- a conventional DBPSK demodulator 3110 as taught in Frerkmg, M , "Digital Signal Processing and Communications Systems", Van Nostrand Remhold, 1994, pp 433-435, 448-450, is shown in Figure 31
- the bit rate being scaleable by the parameter L in the DBPSK demodulator 3110 R (kbit/s) L
- a product of the present bit samples C(n') 3105 are multiplied by a complex conjugate of the previous bit samples and decimated to one sample C(n) 3115 in the DBPSK demodulator so as to convert the frequency error to a static phase e ⁇ or ⁇
- the complex sample C ⁇ (n) 3125 whose angle is the static phase error ⁇ , averaged over the previous M bits, is estimated in a decision feedback loop 3120
- the static phase e ⁇ or ⁇ is canceled before making the demodulated data bit decision b ⁇ t(n) 3130 as shown m Figure 31 , and is accomplished by multiplying C(n) by the complex conjugate of
- the synthesizer includes a stable reference frequency source (such as a quartz crystal oscillator) which is the master clock for the DSP 3280, a downconvert despread and decimate function 3210 as previously disclosed, a frequency detector 3220, a loop filter 3230, a voltage controlled oscillator 3250 and feedback divider 3255
- the output 3260 ofthe synthesizer is a signal at the desired frequency
- a digital to analog converter (DAC) 3240 is placed between the loop filter 3230 and the VCO 3250 to provide an analog control signal to the VCO 3250
- Low cost DACs 3240 are available in a dual 8-bit converter package where fine converter steps are set to 1/64 ofthe coarse converter steps
- the loop filter algonthm 3230 first adjusts the coarse converter to the coarse frequency error 3232 and then the fine converter to the fine frequency error 3233 dunng frequency control loop settling After the LO is locked to the receiver frequency reference, the receiver is reconfigured by changing the switch 3205 to position 2 in Figure 32.
- the receive antenna 3201 feeds the conventional analog RF front end 3203 which includes an analog to digital converter (ADC) at its output.
- ADC analog to digital converter
- the downconvert coefficients in block 3210 are the computationally efficient Fs/4 set, as previously discussed, and thus a computational burden is minimal and may be shared by other receiver functions.
- the frequency locked loop drives the coarse and fine frequency e ⁇ ors 3232, 3233 between the transmitter and receiver and hence the decimation loss to zero.
- Figure 33 illustrates part of a frequency detector implementation as was shown as the decimating frequency detector 3220 in Figure 32, and preferably uses the output of the digital down conversion operation, decimated to 12 samples per spreading code period.
- signal frequency is the first derivative of signal phase with respect to time. (The over dot signifies first derivative with respect to time.)
- the continuous time first derivative is approximated by the discrete time first difference 3320 as is known in the DSP art.
- a group delay of the first difference must be independent of frequency and must equal a group delay ofthe decimated I and
- Figure 34 is a block diagram of a very low cost DAC that includes a coarse 3401 charge pump and a fine 3403 charge pump (controlled current source) driving a capacitive voltage divider 3405.
- the "Charge Control" logic 3410 turns on a charge pump for a predetermined time interval required to deposit or remove a particular charge on the capacitors 3405 This produces an output voltage proportional to the frequency e ⁇ or 3415 computed by the loop filter
- the charge estimate logic 3420 keeps track ofthe charge on the capacitors To conserve power m a battery operated device, the power to the synthesizer is cycled on and off Dunng a power-off event, the estimated charge on the capacitors is saved in non-volatile memory During a power-on event, the estimated charge is ret ⁇ eved from non-volatile memory and used, as will be discussed, to replace the charge on the capacitors that was present pnor to the power-off event
- a third way to remove the effect ofthe ca ⁇ ier frequency error between transmitter and receiver is to control the first LO VCO 3250 ( Figure 32) in a Costas earner recovery loop for BPSK demodulation
- a fourth way to remove the effect ofthe earner frequency e ⁇ or between transmitter and receiver uses the Costas earner recovery loop for BPSK demodulation This shown m Figure 32 with the frequency detector 3220 replaced with a Costas phase e ⁇ or detector
- the DAC 3240 is fed a constant frequency setting and the loop filter 3230 outputs 3232, 3233 control the down conversion coefficients
- Some ofthe diagram blocks in Figure 32 may be shared by other receiver functions According to this approach the NCO must generate arbitrary frequencies for the downconvert tone so the computational efficiencies discussed previously may not be as prevalent
- a fifth way to remove the effect ofthe earner frequency e ⁇ or between transmitter and receiver is to measure the frequency error using the frequency detector 3220 shown in Figure 32
- An additional computation downconverts the decimated I and Q signals from downconvert and despread and decimate block 3210 to zero frequency error in a feedforward a ⁇ angement prior to DBPSK demodulation
- a second embodiment ofthe present mvention is directed to a multi channel transceiver, having a receiver and transmitter that provides enhanced system sensitivity and performance relative to the single channel transceiver ofthe first embodiment, although requmng additional digital signal processing power than the smgle channel transceiver ofthe first embodiment
- the multi channel transceiver contains several common components with the single channel transceiver ofthe first embodiment
- the multi-channel transceiver includes the antennas 901, 903, RF front end 905, transmitter 929, associated antenna 931, and low performance receiver time reference 927 of the single channel receiver, as discussed in Figure 9 Differences, however, will be descnbed with respect to the digital signal processmg section 908 ofthe single channel receiver m Figure
- the smgle channel receiver compensates for a frequency ambiguity ofthe transmitted signal by using a 115 kHz predetection bandwidth so as to be assured of capturing the transmitted signal therein
- the wider bandwidth caused a sensitivity loss, as compared with a conventional receiver that does not attempt to compensate for transmitter frequency uncertainty and therefore uses a detection bandwidth that is commensurate in size to a signal bandwidth
- the multi-channel receiver (actually transceiver, but for simplicity referred to as a receiver) includes a baseband processmg stage that is sufficiently wide to account for the transmitter frequency uncertamty range, although the multi-channel receiver offers improved sensitivity by further subdividing the frequency ambiguity bandwidth mto smaller overlapping bandwidths, each of which match the bandwidth ofthe desired signal
- the multi-channel receiver In order to determine which ofthe channels actually contains the signal, the multi-channel receiver mcludes a channel selection mechanism that selects one of a plurality of smaller bandwidths in order to acquire the spread spectrum signal and demodulate the data contained therein
- the multi channel receiver offers slightly better performance than the single channel receiver of the first embodiment because at least one ofthe channels will capture the signal, and that channel will have a bandwidth that more closely approximates a bandwidth ofthe signal
- the multi channel receiver uses a multi-bit ADC 3504 that serves the same function as the single bit converter in the single channel receiver, in that it digitizes the analog signal mto a series of digital samples, however the ADC 3504 represents the digital samples in multi bit words for subsequent processing in the baseband processor Because the ADC 3504 has hmited dynamic range (I e , a range from lowest signal representable by the ADC 3504 to the highest signal representable by the ADC 3504), an automatic gain control AGC mechanism 3502, as depicted on Figure 35, is used to adjust the incoming signal from the RF front end (similar to the RF front end 905 of Figure 9) to fall within the dynamic range ofthe ADC 3504 Keeping the received signal within the dynamic range of the ADC 3504 prevents the signal from being "clipped" (l e , causing the ADC to perform a non-hnear operation on the signal) if the signal is too high, and prevents the signal from bemg "swamped" by quantization noise generated by the
- Figure 35 also shows a quadrature downconvert and decimate operator similar to 909 in Figure 9, although processor 3530 depicts the mechanisms used for creating the downconversion and decimation coefficients used m the multi-channel receiver Tone generator 3532 generates a tone at frequency (Fc) equal to an IF center frequency (Fc) ofthe received signal
- Tone generator 3532 feeds phase shifter
- Each downconversion tone is mixed with the PN code generator 3536, which has been spectrally compressed with a filter 3538 and mixed m mixers 3540 and 3542 so as to create a downconversion and despreading coefficient table that is precalculated and stored in semiconductor memory m the DSP processor
- Mixers 3512 and 3522 perform the downconversion and despread process using the signal from the ADC 3504 and the quadrature downconversion despreading signal from the precalculated look-up table stored in memory
- the resulting signal is a quadrature, baseband, despread signal passed to low pass filters 3514 and 3524 and decimated in downsampling operators 3516 and 3526 to lower the signal sample rate pnor to DC (0 Hz) removal in DC removal mechanisms 3518 and 3528
- the resulting signal is a despread downconverted and decimated representation of the sample signal received at the input of the quadrature downconversion, despread and decimation process
- the signal processmg mechanism depicted in Figure 35 has sufficient processmg power to perform either a slow senal search, or a fast senal search, as long as the data record for one code repetition interval is stored in memory and correlated agamst all possible combinations ofthe PN code generated locally m PN code generator 3536 To this end, the decimation efficiencies previously discussed may also be employed herem
- the sample rate (Fs) ofthe ADC is 6 0 MHZ which differs from the single channel sample rate of 4 8 MHZ
- the prefe ⁇ ed over sample rate ofthe multi-channel receiver is a 5 1 ratio relative to the chipping rate of 1 2 MHZ which sets the sample rate at a slightly higher frequency
- the over sample ratio is immaterial to the operation ofthe device and only sets the requirements for the anti-aliasing filter preceding to the ADC Accordingly, a subsequent descnption for the multi-channel receiver will be based on a 5 1 over sample ratio
- the present mventors have identified that by precalculating the hybrid coefficients, a coefficient lookup table may enable the downconvert, despread and decimate process to be implemented m very modest DSP components that are presently available
- the final process step depicted m Figure 35 is DC removal, and is performed by DC removal mechanisms 3518 and 3528 that remove undesirable effects of a voltage bias introduced at an analog signal side ofthe ADC 3504
- DC removal mechanisms 3518 and 3528 that remove undesirable effects of a voltage bias introduced at an analog signal side ofthe ADC 3504
- the present multi-channel receiver may use a low precision voltage reference at the ADC 3504, compensating in real-time in firmware This further reduces hardware complexity and cost in realizable systems at a very small computational loading cost
- ADC devices typically have an AC coupled input with a voltage reference set by precision resistors and active components D ⁇ ft in the resistors due to agmg and temperature will vary the reference voltage and center point, creating a DC bias in the incoming data stream
- ADC bias on the signal will be mte ⁇ reted as a CW jammer in the system, exactly centered in the IF, and will be translated to the Nyquist extremes (0 and Fs/2) This creates an elevated noise floor and will decrease radio sensitivity if left unco ⁇ ected
- the present multi-channel receiver performs DC removal at a later point in the signal processing, removing the need to perform the math function at the sample rate
- DC removal is performed in operators 3518 I and 3528 Q, not at pomt 3508, and thus performs DC removal on downconverted, decimated and despread samples
- the multi-channel receiver performs a despread-and- decimate function on the raw data, reducing the number of samples by the decimation ratio of decimators
- the signal is decimated by 21 to produce 15 quadrature samples per bit period, yielding a Nyquist-bandwidth frequency uncertamty of 288 kHz, of which only 120 kHz is of interest
- Removing the DC component from the input data following the decimation reduces the loading from 315 math operations to 30 ( 15 I terms and 15 Q terms)
- Decimation often implements an averagmg function, but instead of averaging, the decimation process can instead compute the sum This introduces an e ⁇ or factor that will be proportional to 1/N where N is the decimation ratio.
- decimation (summing) process can be expressed as 15 multiply-accumulate processes against independent data and coefficient sets.
- Each decimation block / can be expressed as:
- the result is a scalar value representing one of 15 downsampled data points per I and Q processor. Because a DC offset value is present in the samples, the term D,(n) contains the sampled data plus a constant, A, added to each data point.
- the new constant K represents the sum of the coefficients for the decimation block.
- a non-zero mean for the decimation block acts as a multiplier for DC offset if a correction is not performed.
- the product AK must be compensated within each decimation block if the computation is to be co ⁇ ect.
- Each I and Q decimation block therefore has an independent K scalar multiplier that magnifies DC.
- a mean measure ofthe DC component is needed so as to complete the decimation co ⁇ ection.
- a number of random sampled data points are averaged for each bit interval to produce an estimate ofthe mean. More particularly, in the present embodiment, 16 random ADC data points per code period are averaged to compute a mean.
- the "code period" mean is then time-averaged over an the most recent 8 code periods to calculate a running approximation of A.
- each decimation coefficient block (K,) is computed at a compile time and provided as a lookup table.
- the time-averaged mean (A) is multiplied with each ofthe I and Q coefficient sums (K,) to create 30 DC removal products (AK,) which are subtracted from their respective I and Q decimation results.
- a final bandwidth in a receiver must match the information bandwidth to achieve maximum sensitivity.
- the present multi-channel receiver embodiment uses overlapped channel filters to achieve an optimal signal-to-noise ratio (SNR).
- SNR signal-to-noise ratio
- the data sampled at the ADC 3504 is despread and partially decimated to a point where the decimated signal bandwidth is at least as great as the frequency uncertainty of the transmitter (greater to reduce decimation loss at band edge, as was discussed).
- the receiver next sends the partially decimated data into a bank of channel filters to complete the decimation process and make the decimation bandwidth equal to the signal bandwidth.
- the channel filters may be implemented using a fast Fourier transform (FFT) or discrete Fourier transform (DFT), finite impulse response (FIR) filter or infinite impulse response (IIR) filter or other similar transform that band-limits the data signal.
- FFT fast Fourier transform
- DFT discrete Fourier transform
- FIR finite impulse response
- IIR infinite impulse response
- a DFT is prefe ⁇ ed over an FFT because an FFT provides uniform channel spacing that is equal to the channel bandwidths. If an FFT is used, the between-channel roll-off adds 3.9 dB of loss to the decimation loss.
- the input data stream may be represented as:
- a +jB where "A" and "B” represent vector components of sampled data.
- the vector holds 1 code period of sampled data partially decimated down to a sampling rate greater than 2 times the frequency uncertainty.
- the channel filter coefficient is atone represented by the complex vector C + jD.
- the positive channel filter becomes the product of these two tones.
- the prefe ⁇ ed embodiment employs this technique to maximize the number of usable overlapped channels . Adding more channels reduces the between-channel losses and more efficiently utilizes processor computational bandwidth. This technique enables the realization of many channels in a very modest digital signal processor.
- Figure 36 depicts a signal processing mechanism that implements the above-described symmetrical channel filter efficiencies, for realizing a single pair of channel filters, symmetric about 0 Hz. Other mechanisms are used for calculating the other symmetrical channel filter pairs.
- signals 3602 and 3604 represent the I and Q decimated data streams of a baseband signal.
- a frequency generator 3606 and delay element 3608 i.e., a phase shifter
- Multiply operators 36M1 through 36M4 generate the product terms 36P1 through 36P4 respectively by multiplying signals 3602 and 3604 with inphase and quadrature frequency offsets produced by frequency generator 3606 and delay element 3608, as shown.
- the product terms 36P1-36P4 are decimated by lowpass filters 36F1 through 36F4 and then decimated by 15 in the downsampling elements 36D 1 through 36D4 so as to produce the signals AC, BD, BC, and AD.
- the signals AC, BD, BC, and AD are then either added or subtracted in elements 36A1 through 36A4 to produce the intermediate values that will be used to determine the signal power in the respective symmetric channel filters.
- These intermediate values are squared in squaring operators 36S1 through 36S4 and then combined in adders 3614 and 3616 to produce both the positive and negative channel filter outputs for a particular frequency offset.
- the center channel filter i.e., 0 Hz offset.
- the center channel filter is the most straight forward to implement because it may be noted that for a 0 Hz frequency offset, as noted in Figure 36, the quadrature component ofthe sinusoidal transform may be constant 0 while the in-phase component may be constant 1. Thus, half of the product terms go to 0 while the other product term is the data itself (multiplied by 1). The 0 Hz channel filter therefore becomes the sum ofthe squares ofthe decimated in-phase and quadrature data.
- Figure 37 illustrates a center frequency channel determination mechanism that receives the I and Q decimated data streams, 3702 and 3704 respectively, and applies the same to lowpass filters 37F1 and
- the pu ⁇ ose for employing the decimation filter is to attenuate image frequencies that exist above the Nyquist frequency. According to the filter roll-off, these image frequencies are rejected by at least 13 dB.
- the decimation loss with regard to transmitter frequency error is the loss across the center ofthe main lobe ofthe sine function.
- Figure 38 is a graph illustrating an amount of decimation loss for the transmitter frequency uncertainty range as a function of percent of Nyquist bandwidth. When a signal of interest 3803 approaches the band edge of the Nyquist bandwidth 3802 or 3804, up to 3.9 dB of decimation loss can be expected, as shown.
- the multi-channel receiver performs decimation to reduce the data rate prior to channel filter implementation.
- the optimal decimation would bring the Nyquist bandwidth down to equal the transmitter frequency uncertainty at a cost of significant decimation loss. Maximizing decimation means that each channel filter performs its function on the minimum of data points. Relaxing the decimation increases the channel filter computational loading, yet provides relief against decimation loss.
- the sampled data is processed to create overlapping filters that span the frequency uncertainty.
- the sensitivity of each channel filter is set by the bandwidth ofthe channel filter and the total decimation loss.
- the ideal channel filter would be performed at the maximum data rate, thus suffering no decimation loss. This is not practical, in systems having limited computational resources, as is the case with the present multi-channel receiver. Accordingly, the realization ofthe present multichannel receiver performs a partial initial decimation, lowering the effective bandwidth and associated data rate prior to channelization.
- a set-on channel filter may be used to further reduce system loss due to filter shape
- Set-on channel filter 3910 is used to eliminate or reduce the effects of between-channel loss, where the set- on channel filter has vanable center frequency that may be moved to be centered overtop of a signal, once the signal is detected Following a tnp event m one ofthe static channels, the processor implements an inte ⁇ olation mechanism that inte ⁇ olates a power m two adjacent channel filters so as to determine a best estimate of actual frequency offset
- the set-on channel filter is subsequently steered to exactly match the desired signal center frequency, thus removing any channel filter roll-off Total system loss is therefore hmited to the decimation loss
- Figure 39 depicts the set-on filter as a dashed line 3910 which recovers the roll-off loss between two fixed channels
- the ambiguity function is the received signal energy as a function of spreading code phase ⁇ and carrier frequency shift v between transmitter and receiver.
- the receiver is adjusted by the code phase and carrier frequency shift that results in greatest received signal energy so as to acquire synchronization with the transmitted signal.
- a size ofthe phase step in the search method is one code chip and a size of the frequency shift step is the frequency ofthe code repetition.
- Step 1 A real input fast Fourier transform (FFT) 4010 is performed on an input record 4005 of one period ofthe reference code.
- the 63 output (frequency) points centered on 0 Hz are saved in memory and the remaining output points are zeroed, which results in a reference code 4014 being filtered by an ideal low pass transfer function 4012. This computation is perfo ⁇ ned only once.
- FFT fast Fourier transform
- Step 2 The received signal is preferably sampled at the rate of 5 samples per spreading code chip (or 4 may be used as well).
- a real input fast Fourier transform (FFT) 4020 is performed on an input record 4015 one code period long.
- Step 3 A circular indexing shift operation of v -f s /44030 is performed on the output points 4024 so as to downconvert from the IF to baseband, and the resulting 63 output (frequency) points 4034 centered on 0 Hz are saved. The remaining output points are then zeroed, which results in an ideal low pass filtered baseband received signal at a frequency shift v.
- Step 4 These 63 frequency points 4034 are multiplied in a multiplier 4040 by the complex conjugate 4045 ofthe 63 reference code frequency points 4014.
- An inverse fast Fourier transform (IFFT) operation 4050 is performed on the product, and the result is a slice of the ambiguity function at one frequency shift v.
- IFFT inverse fast Fourier transform
- Step 5 Steps 3 and 4 are repeated for each frequency shift so as to complete the computation of an ambiguity function 4060, and from this result the receiver can be synchronized using the methods disclosed elsewhere herein.
- This algorithm is exemplified with a 63 chip spreading sequence, although parameters of the algorithm may be changed to accommodate other spreading sequence lengths, intermediate frequencies, and sampling rates.
- Fast Frequency Domain Fine Search After resolving the ca ⁇ ier frequency shift v between transmitter and receiver, it is preferable to resolve the spreading code phase ⁇ to 54 of a chip. This is preferably accomplished by repeating step 3 with v set for greatest received signal energy. See Figure 40.
- the 63 frequency points 4034 are multiplied in the multiplier 4040 by the complex conjugate 4045 ofthe 63 reference code frequency points 4014.
- the 63 point product is zero padded to 252 points (i.e., add points having zero value) in zero pad operator 4070, and perform an inverse fast Fourier transform
- IFFT IFFT 4080 on the zero padded product.
- the result is a slice of an ambiguity function 4090 at the optimum frequency shift v with a phase resolution of 54 of a chip, from which the receiver can be synchronized to within ⁇ 1/8 of a chip using the methods discussed herein.
- the pu ⁇ ose of this algorithm is to synchronize the PN code ofthe receiver to that ofthe transmit signal.
- Two parameters need to be resolved in order to achieve this end: transmitter-receiver frequency offset and code-delay ⁇ .
- the processor can chose the best parameters for synchronization.
- This 2-dimensional co ⁇ elation function over code-delay and frequency is called the Ambiguity function A( ⁇ , v). Assuming a strong-enough signal is indeed being transmitted, the ( ⁇ , i ⁇ -pair that best aligns with the transmit signal will have the strongest Ambiguity function value. See Figures 41 through 45.
- Figure 41 illustrates the conventional process of evaluating the Ambiguity function at a specific ( Figure 41 shows N samples over atime span of one code period, dfnj 4101 and N coefficients of one code period, afnj 4102. Both enter a correlator 4103 and the correlation between the two signals 4104 is the Ambiguity function evaluated at ( ⁇ , v).
- Figure 42 illustrates a conventional process where a slice of the Ambiguity function 4201 is evaluated for all delays ⁇ using a circular correlation operator 4202 with the same inputs.
- Figure 43 illustrates a conventional circular co ⁇ elation process that is very similar to a process known as circular convolution. Reversing one input sequence a[n] 4301 produces a sequence b[n] 4302, as shown and thus the circular convolution operator 4303 can be used as part ofthe circular co ⁇ elation operator 4304 to produce the ambiguity function.
- a conventional circular convolution process is shown in Figure 44 and is based on an understanding that convolution in the time domain is equivalent to multiplication operator 4401 in the frequency domain.
- Sequences 4402 and 4403 entering the circular convolver are reformatted into a frequency representation using the DFT operators 4404 and 4405, and combined in the multiplication operator 4401 an output as product 4406.
- the product 4406 is reformatted into a time-domain representation 4407 using an Inverse Discrete Fourier Transform operator (IDFT) 4408.
- IDFT Inverse Discrete Fourier Transform operator
- Figure 45 illustrates an inventive fast-frequency search process employed in the multi-channel receiver embodiment, which is relatively more computationally intensive than any search process employed in the single-channel receiver ofthe first embodiment, but uses bandpass filtering, and decimation-in-time as a way to reduce processing load.
- CfnJ 4501 is an extracted M-length frequency-domain subsequence from BfnJ 4502 centered around/74, where B[n] 4502 is a product of an N-point DFT performed on time domain representations (a[n] ... b[n]) ofthe spreading sequence, as generated by the receiver.
- E[n] 4503 is an extracted M-length frequency-domain sub-sequence from D[n] 4504 centered around (f/4) + v, where D[n] 4504 is an N-point result of a DFT operation performed on N time domain samples, d[n] ofthe received signal.
- C[n] and E[nJ are equivalent to ideal band-pass filtering in the frequency domain and decimating in the time domain.
- DfnJ 4504 are stored in RAM so that DfnJ
- E[n] 4505 can re-extract E[n] 4505 as the process steps through values of vto fill in the Ambiguity function, as shown in the graph portion of Figure 45.
- a gray region of Figure 45 represents precalculated values stored in ROM.
- a data structure of the stored data includes a field configured to hold the M points co ⁇ esponding to the portion of the code spectrum centered around f s /4.
- the product F[n] 4505 is transformed back to the time domain sequence f[n] 4506 before being put into the Ambiguity a ⁇ ay 4507, as shown in Figure 45.
- the DFT and its Inverse can be calculated using the Fast Fourier Transform process.
- the DFT (or the IDFT) takes N 2 multiply-accumulate operations, just as many as circular convolution.
- the FFT algonthm breaks the large DFT into smaller DFT's
- the Winograd DFT method may be used as a substitute for the smaller prime DFTs Winograd 's method minimizes the number of multiply operations for certain prime DFTs but also incurs higher indexing complexity
- Most effective digital signal processing devices will perform multiply operations as efficiently as addition operations, and may have provisions for successive and modulo indexing Winograd' s method will not be as advantageous in such processors as it could be with a processor that does not have smgle-instruction multiply operations
- the Winograd method is not used m the present embodiment for the indivisible DFTs because digital signal processing devices are generally more efficient m the N 2 calculation in general
- 3 and 7 are relative low number pnmes and thus N 2 is somewhat small
- prime factors should also play a role selecting a spreading sequence, as they are in the preferred case of 63 chip spreading sequence
- the multi-channel receiver ofthe present embodiment offers relatively fast signal acquisition and reduced transmitter preamble time
- False tnps events are received power fluctuations at an e ⁇ oneous code phase that are sufficient to cause the receiver to dwell at that code phase and evaluate the incoming signal to determine if correlation has, in fact, been obtained
- Sources of received RF signals include ambient noise, keyed earner wave (CW) jammers, non-co ⁇ elated spread spectrum signals, and co ⁇ elated spread spectrum signals ⁇ on-co ⁇ elated spread spectrum signals are signals that may properly be decoded by the receiver, provided that the receiver can eventually obtain code phase coherence with the received signal, a correlated spread spectrum signal is one m which spreadmg code phase coherence has already been achieved
- a tnp event occurs when there is a measurable increase in received signal power over successive penods of time, however, this increase may be due to several sources and, perhaps, many of these increases will not result in a legitimate, true tnp event signifying that the received signal should be demodulated
- the presently descnbed inventive process is a ⁇ anged
- tnp event decisions are made after the signals have been despread and after the signal has been separated mto vanous frequency bins, where a highest performance is obtained by usmg 11 overlappmg frequency bms (channels)
- the aforementioned signal types will have unique power distnbution charactenstics (e g , signal "signatures") as cumulatively viewed in the frequency bins
- Figures 47-50 depict the power levels of these signals distributed throughout the bins Figure 47 represents random noise and m Figures 48-50, a center frequency of a received signal is depicted as bemg coincident with the center frequency 4805, 4905, 5005 (l e , in bm 5) ofthe channel filters in the respective figures
- the signals have similar characteristics, even though Figure 48 depicts an undesired CW jammer while Figure 49 depicts a desired signal at an unco ⁇ elated relative code phase
- the power level ofthe frequency bms 4805, 4905 is lower than the
- Figure 50 illustrates the power distnbution in the respective bins when the co ⁇ elated spread spectrum signal is present
- Frequency b 5 (5005) holds the center frequency ofthe transmitted signal as depicted by the maximum signal level Because the frequency bins overlap, some ofthe energy present in bm 5 will also be in bins 4 (5004) and 6 (5006), but powers in the remaining bins begins to drop off sha ⁇ ly after that, as set by the attenuation provided by each channel filter (1 e , because much, or all, of the signal energy falls outside ofthe filter passband) Steps in the false t ⁇ p avoidance process are explained with reference to Figure 51 where the method begins in step 5105 , where the power level is measured in each channel filter The process proceeds to step 5110 where the frequency bin with the maximum signal strength is determined and designated as maxl Subsequently, step 5120 ignores the frequency bins that are adjacent to maxl providing for channel overlap Step 5120 calculates the average value ofthe signal strength values m the remaining frequency bms and design
- Figure 51 also illustrates another process that uses the approach discussed earlier for the 1-bit ADC for the single chaimel embodiment
- the process begms m step 5105, as previously discussed, and proceeds to step 5110, as previously discussed
- the process flows to step 5141, where a stored predetermined threshold is ret ⁇ eved from memory and, in step 5145 is compared with maxl obtained in step 5110 If the response to the inquiry in step 5145 is affirmative, the process proceeds to step 5140, where the fine search process is initiated However, if the response to the inquiry m step 5145 is negative, the process proceeds to step 5150, where the course search process continues by returning to step 5105 Enhancing Coarse Search
- Averagmg similarly improves signal acquisition performance in the present multi-channel recerv er embodiment, as was the case for the single channel receiver embodiment
- the averaging process is a different m several respects
- the correlation data being represented as vectors
- the co ⁇ elation data exists m another dimension as well, so as to be a ⁇ anged in a plane of information, each data pomt being described by three axes coordmates frequency channel
- Figure 52 depicts a sample data set from one code period (i.e., no averaging), while Figure 53 shows the collection of several data sets, appropriately averaged.
- a most noticeable result of averaging is a suppression of background noise, as is evident from a comparison of noise floors 5220 and 5320 in Figures 52 and 53, respectively.
- averaging may be performed as a boxcar or FIR structure where the last N symbols are averaged.
- averaging may be performed in an exponential or IIR averaging process where the previous results are decayed and added to a fraction of a present sample.
- Figures 52 and 53 depict the desired signal co ⁇ elation peak at points 5210 and 5310, respectively, in a plane of frequency channel versus correlation code phase.
- the prefe ⁇ ed multi-channel receiver embodiment employs 11 frequency channels and 63 code chips, although the number of channels and chips may be varied in accordance with the discussion of trade-offs as presented herein.
- Figure 54 is a histogram of power versus occurrences that illustrates a reduction in false alarm rate achieved by averaging 6 samples in the multi-channel receiver embodiment.
- Curves 5410 and 5420 show the power distribution of a 20 kHz noise bandwidth with and without averaging respectively.
- Curves 5430 and 5440 show the power distribution of a -110 dBm signal in 20 kHz noise bandwidth with and without averaging respectively.
- the mean power for the noise and signal plus noise distributions remain unchanged, yet the deviations are reduced creating a greater distance between the minimum "On” and the maximum “Off". Consequently, extending the distance between the minimum "On” and the maximum “Off” corresponds directly with decreasing the probability of reporting a false trip condition.
- Frequency domain averaging is identical to the multi-channel case depicted in Figure 45, where the result ofthe fast frequency coarse search is a plane of power versus frequency and code phase. This process, however, uses different mathematical operations to achieve the same result, yet the result may be averaged as in the channelized time domain coarse search to achieve better SNR. Applying the method for reducing false trips for impulsive interference following averaging provides the maximum sensitivity achievable, under the presently described circumstances.
- AGC Automatic Gain Control
- AGC is used to adjust a signal level of a received signal to fall within an instantaneous dynamic range of the ADC. At times this is a challenge, because the receiver may be exposed to signals of varying strengths. For example, a receiver placed within a few feet of a transmitter will be exposed to a very strong signal level, but a receiver located far from the transmitter will be exposed to a very weak signal level. AGC allows the received signal, in either case, to be adjusted to within a predetermined range, prior to being applied to the ADC.
- One factor considered in the AGC mechanism is a level of a received noise floor and thus the AGC mechanism monitors the received noise floor, attempting to keep it within an operable range ofthe ADC
- the noise floor nses, there is a nsk that the AGC mechanism will not act to lower the signal level applied to the ADC and will result in clipping an intended signal, as a result of madequate "headroom", which has profound adverse affects on signal correlation and reception Accordmgly, if the AGC mechanism detects that the noise level has risen too much, the AGC mechanism will act to attenuate the received signal (and noise) to a lower level, ensuring that the received signal will remain withm the ADC's dynamic range
- the AGC process is implemented in software and is executed once per code period while the search process is attempting to correlate If an attenuation change is deemed necessary by the AGC process determining that the sample values are above a predetermined threshold, for example, the search process is interrupted while AGC adjusts the receiver gam, over several code periods, which m turn adjusts the co ⁇ esponding signal strength ofthe received signal Decisions made by the AGC process are based on the measured noise floor (where the measurement may be made with a discrete level detector or by digital analysis on the received sample stream) and serves to keep the noise floor within the operable region ofthe ADC
- the AGC process may be augmented with tune constant mechanisms to offset the effect of impulsive interference, and averaging mechamsms that combme several sample sets so as to avoid invokmg an AGC adjustment if short-term perturbances in the noise floor are observed Similarly, the AGC process may be adapted to operate off of the strongest received signal, so as to avoid dnvmg the ADC outside of the
- Attenuation ofthe received signal is set with two controls, implemented m hardware, although other software or firmware driven control may be used as well
- the signal level may be adjusted (preferably attenuated) in the attenuator 3502 by a maximum of 75 dB usmg a step and digital attenuator that operates under the control ofthe AGC signal (as shown in Figure 35)
- a 4-bit digital attenuator located in the attenuator 3502 is positioned prior to the ADC and provides attenuation in 3 dB steps up to a maximum of 45 dB attenuation
- a coarse 30 dB step attenuator may optionally be applied in front ofthe first RF amplifier, thus protecting the mixer from very strong signals and related lntermodulation products created by excessively strong signals being applied to the mixer
- a related problem caused by excessively strong signals is that the signals may result in the digital signal processmg operations performed on the signals to enter an overflow state
- the digital signal processor used to compute the co ⁇ elation sum on the received signal also implements the decimation process concu ⁇ ently therewith
- a digital signal processor that computes this correlation sum has the undesirable attribute of failing to retam an indication of intermediate overflow This means that m the decimation process, should an accumulator m the digital signal processor overflow at some intermediate point, there may be no report ofthe overflow condition after the decimation process is complete
- the digital signal processor may reset the overflow flag on the next mathematical instruction
- the overflow concern is easily avoidable by using modern digital signal processors having sufficient processing capability, overflow indication mechanisms, and/or large accumulators
- identifying the source of the problem and solution to the problem requires innovative processes and mechanisms
- the present multi-channel receiver uses a small accumulator while managing the possibility of overflow by integrating signal scaling mto the AGC process
- the receiver's processes and mechanisms must be able to detect the presence of strong or weak signals and act accordmgly, making adjustments in the attenuator 3502 ( Figure 32) to keep the signal m the desired received power band Weak signals do not create a problem, because the signal power drops monotonically with signal attenuation, and a low threshold near the minimum co ⁇ elation limit triggers a signal drop event
- the present multi-channel receiver uses a threshold set near the maximum co ⁇ elation limit ofthe accumulator so as to create a value d ⁇ ven overflow condition
- the threshold is effective in determinmg a need for AGC (e g , provides a warning signal), yet the value reported is not used because it becomes non-monotomc
- the AGC process addresses this unreliable reporting of an overflow condition by searching backward, keeping a range of untrustworthy samples (l e , perhaps tainted by an unreported overflow condition) shadowed in previous evaluation ranges where the power can be trusted
- the range of ambiguity can be eliminated by asserting first maximum attenuation and then subsequently stepping through progressively less attenuation.
- the AGC process When first initiated, the AGC process starts by asserting maximum attenuation (so as to produce a minimum signal level applied to the ADC) and then progressively lowering the amount of attenuation in roughly 9 dB steps (or other suitable step sizes), through 7 coarse acquisition steps. By first applying maximum attenuation, there is no ambiguity regarding whether the data samples have been caused an overflow condition during the decimation process.
- the noise level detected in one of these steps is near optimal (i.e., at a prefe ⁇ ed level within the ADC's instantaneous dynamic range)
- the AGC process causes a fine attenuation step to be executed so as to place the received noise floor within 3 dB of the desired level. Subsequently, the AGC process terminates and the normal correlation (search function) resumes.
- the AGC process as implemented in the present embodiment accounts for a three-code period delay set by pipeline processing.
- the AGC process causes an AGC attenuation change
- the next two code periods are already being processed.
- the third code period following a setting operation, will hold data that reflects the change. For this reason, the AGC acquisition process is heavily pipelined to minimize waiting for data.
- Figures 55 through 65 depict the state process implemented in the AGC process and mechanism. The following description details the steps used in the most sensitive exemplary embodiment ofthe multi-channel receiver.
- the AGC process flow shown in Figure 55 begins in step 5501 and then to step 5502 where a Boolean flag is maintained. An inquiry is made so the AGC process recalls, between program calls, whether the AGC process is cu ⁇ ently acquiring a signal. If the response to the inquiry is affirmative, the process proceeds to step 5506 so as to determine where the AGC process is in the acquisition cycle. If AGC is not acquiring, the process continues by computing a time averaged noise floor in step 5503 using the last 8 code periods for smoothing the instantaneous noise. A counter (code interval timer) is decremented and tested in steps 5504 and 5505 so as to add hysterisis to the AGC process.
- code interval timer code interval timer
- step 5507 the instantaneous noise floor is monitored so as to determine if there exists enough headroom in the ADC and decimation process to support a co ⁇ elation operation. If the noise level is too high, and there exists more attenuation as inquired in step 5508 for use, the process proceeds to step 5506 so as to initiate the acquisition process . However, if the instantaneous noise value requires attenuation but there is not any additional attenuation available, the process proceeds to step 5511, where the process aborts. If the instantaneous noise level is not too high, the process continues at 5509 where the time averaged noise floor is evaluated as being too low.
- step 5506 If the time averaged noise floor is too low, and attenuation can be removed from the cu ⁇ ent setting 5510, an acquisition is necessary, so the process proceeds to step 5506 to properly set the lower attenuation level If the time averaged noise level is too low, but no further attenuation can be removed, the algonthm aborts m step 5511
- Figure 56 is a flowchart of a decision tree for determining where the AGC algonthm is in the AGC acquisition cycle Step 5601 continues from step 5506 as shown on Figure 35 After step 5601 the process proceeds to step 5602 where an inquiry is made regarding the AGC processing state, which is determmed by checking a state vanable Depending on the value of the state vanable, the process continues to respective of steps 5603 through 5613, as will be explained below with respect to Figures 57-61
- Figure 57 is a flowchart of four ofthe decision tree branches depicted in the flowchart of Figure 56 Step 5701 is the continuation of step 5603, Step 5704 is the continuation of step 5604 Step 5711 is the continuation of step 5605 Step 5714 is the continuation of step 5606
- the acquisition process begins m step 5701
- the maximum attenuation (mimmum sensitivity) is applied m step 5702
- the state vanable is advanced to step 5703 and the AGC process terminates in step 5710 and waits for a new code period of data
- the noise value has crept up to the decision threshold and only a small adjustment is needed
- the last two noise samples are averaged in step 5706 and a small adjustment is made
- step 5714 On the next code interval, the process flow resumes through step 5714 and then in step 5715, attenuation is lowered to continue the search process Subsequently, the state vanable is advanced in step
- step 5716 the process waits for a new code mterval of data in step 5717
- Figures 58, 59 and 60 are flowcharts of six ofthe decision tree branches depicted m Figure 56 Step 5801 is the continuation of step 5607 Step 5810 is the continuation of step 5608 Step 5901 is the contmuation of step 5609 Step 5910 is the continuation of step 5610 Step 6001 is the continuation of step 5611 Step 6010 is the contmuation of step 5612
- the processes depicted in Figures 58, 59 and 60 demonstrate the evaluation ofthe attenuation levels set 3 code intervals previous (due to pipeline delay)
- the first evaluation step 5801 the instantaneous noise level is evaluated in step 5802 If the noise level is too high, the optimum pomt has already been passed, and thus a blmd 9 dB is added in step 5806 before the AGC process terminates in step 5807, instructing the calling module that it has completed acquisition
- the noise level as determined in step 5802 is not too high, the noise level is tested for being too low m step 5803 indicating the attenuation is still to great
- the next attenuation step is applied m step 5804, the state is advanced in step 5805 and the process is suspended in step 5809, waiting for the next code mterval of data If the test performed in step 5802
- the evaluation steps 5810, 5901, 5910, 6001, 6010 evaluate the instantaneous noise level 5811, 5902, 5911, 6002, 6011, respectively If the noise level is too high, the optimum pomt has already been passed, and a blmd 9 dB is added in steps 5815, 5906, 5915, 6006, 6015 respectively before the AGC process terminates in steps 5816, 5907, 5916, 6007, 6016 respectively, instructing the calling module that it has completed acquisition If the noise level of steps 5811, 5902, 5911, 6002, 6011 is not too high, the noise level is tested for being too low m steps 5812, 5903, 5912, 6003, 6012 indicating the attenuation is still to great The next attenuation step is applied in steps 5813, 5904, 5913, 6004, 6013, the state is advanced in steps 5814, 5905, 5914, 6005,
- Figure 61 is a flowchart ofthe last evaluation step and the small step algonthm process flow
- the last attenuation step is evaluated if the search thus far has not found a solution
- Step 6101 is the contmuation of step 5613 depicted m
- Step 6109 is the contmuation of steps 5707, 5808, 5817, 5908, 5917, 6008, 6017 or 6108
- the attenuation is set to a minimum three bit code intervals previous, so the cu ⁇ ent data represents the maximum sensitivity setting
- the noise level is tested m step 6102 and if the noise level is too high, the optimum pomt has already been passed, and a blmd 9 dB is added in step 6106
- the algonthm suspends operation in step 6107, instructing the calling module that the AGC process is finished If the noise value measured in step 6102 is not too high, it is evaluated as being too low step 6103 If too low, there are no further steps to minimize atten
- the conventional approach has been to avoid drift problems altogether by ensuring the transmitter and receiver reference components not experience frequency drift, primarily by using crystal controlled or direct digital synthesis frequency references
- Cost efficient transmitters often have frequency references which are sensitive to changes in power supply voltage or electro-mechamcal mterference, even self interference This is especially true for OOK transmitters which often enable and disable amplification stages to modulate data which can effect local frequency references such as voltage controlled oscillators
- the combination of an OOK transmitters with an inaccurate frequency references causes particular challenges for a low-cost receiver that has available only minimal processmg capacity
- the present invention employs cost efficient components and combines them so as to be used in systems havmg transmitters that transmit messages with, perhaps, significant frequency drift and offset
- Conventional practice accommodates the sizable transmitter frequency dnft by quantifying the total frequency error budget, for all ofthe relevant system components, and expanding the channel bandwidths in the receiver to exactly match the worst case frequency dnft The wider receiver bandwidth de-sensitizes the receiver because the mcrease
- the present multi-channel receiver embodiment uses several channels, each matching the data bandwidth, so as to track frequency drift throughout a message Figure 62 depicts a bank of channel filters where a specific filter matched to the data bandwidth has shape 6200 A signal exactly aligned in channel 6203 transmitting a " 1 " would have a measured mean power denoted as 6201 in Figure 62 Because the channel filters have independent roll- off charactenstics, a signal adjacent to the desired channel will be attenuated according to the shape ofthe filter 6200 As such, there exists a between-channel loss (l e , because the signal falls in between to channels) denoted by point 6202, signifying a worst case system sensitivity for signals which have no frequency drift A signal exactly centered between two channel filters would be measured in either filter with a mean power as denoted at 6202 For this reason, it is most beneficial to overlap the channel filters to limit the between channel loss The system loss budget can then be specified using this worst case estimation The above description remains valid as long as the transmitters do
- the Curve 6204 depicts the ideal signal 6203 which has been pulled off frequency beyond the between-channel point 6202 to a high attenuation pomt 6205
- the signal from the initial channel 6200 would progressively drop power, durmg bit interval, because the dnft would cause signal to move away from the center ofthe channel and toward an edge ofthe channel
- the transmitter dnft was constramed between the frequency excursions shown as curves 6203 and 6204
- the signal power will fluctuate between pomts 6201 and 6206 (heavy line 6206)
- the present multi-channel receiver uses several channel filters to track frequency fluctuations during data demodulation The total frequency excursion must be quantified for the transmitters in question and system application The techmque is most feasible for co ⁇ ecting small scale frequency dnft on the order ofthe data bandwidth Wide scale frequency drift could be corrected in the transmitter
- the steady state condition is defined as the restmg frequency of the transmitter Typically frequency dnft is caused by changes m the transmitter power structures, most typically caused by keymg an OOK transmitter As such, it is common for the frequency to have error coincident with a change m amplitude key state The steady state condition is therefore measured when there is a run of same state values while the transmitter is keyed, perhaps in a preamble or initiation sequence ofthe signal data structure
- the lines 6301 represent the respective powers measured m a smgle channel filter over a sequence of bit intervals Vanation between the heights ofthe lmes indicates that there is a time vanable power vanation
- the transmitter exhibits signal loss dunng a 0 to 1 transition state shown as line 6303
- the power is recovered by the bit interval co ⁇ esponding with the line 6304 This recovery coincides with the transmitter dnft co ⁇ ection over tune
- the loss in power when the sequence of Is is transmitted effects the bit error rate, and may influence the decision threshold mechanism to call the bit a "0" (l e , a bit e ⁇ or) in cases where there is low SNR, l e , where the noise floor 6302 approaches the Is level (6303)
- the trip determination step 6400 may be any ofthe processes discussed herein or any other determination of signal activity
- the pnmary channel determination is determined in step 6401 where the pnmary channel is determined as the channel which most closely aligns with the steady state power of the transmitter, while the transmitter is transmitting a preamble portion ofthe signal
- the pnmary channel is the channel with the largest measured mean power dunng a run of Is in the preamble ofthe transmitted message
- the process proceeds to step 6402 when an initial primary OOK decision threshold for determining a 1 or a 0 is set This may be static based on the measured amplitude of a 1, a zero or combination thereof, or it may be dynamic and change to track with the message as received
- Data demodulation commences following initialization, and at each new bit interval collected step 6404, the received signal power is measured m each ofthe candidate channels in step 6405 where the signal may deviate
- the power in the primary channel is compared to the primary OOK decision threshold in step 6406 If the power exceeds the threshold,, a Is determination is made in step 6408 and the next bit is processed If the power is below the pnmary OOK decision threshold, the alternate channels are evaluated in step 6407 usmg the alternate decision threshold If any ofthe alternate channels exceed the alternate decision threshold, a Is decision is made in step 6408 and the next bit is processed If none of the alternate channels exceed the alternate decision threshold, a 0's determination is made in step 6409 and the next bit is processed
- the difference between the pnmary and alternate channel decision threshold effects the bit e ⁇ or rate (BER)
- the alternate decision threshold must be at least equal to the pnmary decision threshold and preferably larger so as to minimally impact the receiver BER Figure 65 depicts noise versus signal
- a second threshold is used for the alternate channels which is set such that the combined zeros determination BER contribution for the alternate channels is small relative to the primary zeros BER The overall system BER is not adversely affected and the benefit of using the alternate channels is achieved
- Exact placement for decision thresholds and separation for primary and alternate decision thresholds is determined based on system requirements for signal detection and data integ ⁇ ty Predictive Code Reposition
- the present receiver embodiments use the results ofthe initial search process to predict the rate of time base drift
- This method requires that the transmitter use one time base to control the RF frequency as well as to generate the code chip rate Conversely, the receiver must use one time base to generate the downconversion tones as well as generate its code chip rate
- This method also requires that the receiver be able to quantify the frequency error so that the spreadmg code phase drift can be predicted
- one of the eleven channels will be selected as the candidate filter by the coarse search process
- the receiver uses the channel mdex (e g , channel number) relative to 0 frequency error to predict the tune base drift as follows
- the predictive reposition method may be sufficient to maintain code coherence over a message duration without the use ofthe standard reposition method
- the effects of reposition are explamed m Figures 66 A, 66B, and 66C wherein points 6610, 6620, and 6630 represent the signal level after the coarse and fine search algo ⁇ thms have been performed After the duration ofthe message 6611, the signal strength ofthe message will have decreased to points 6615, 6625, and 6635 due to crystal dnft Item 6613 shows the signal strength of an ideal message with no loss of process gain Items 6626 and 6636 show
- the feature 6627 shows a signal recovery provided by the predictive reposition method
- An amount of signal recovery 6628 is determmed by the system's ability to discern the frequency error ofthe received RF signal
- the repetition rate 6634 ofthe predictive reposition method is set by the worst-case system loss requirement and the amount of signal recovery 6628 that can be achieved
- the two reposition methods can be used together to provide enhanced performance Feature 6638 shows the combination ofthe two methods as providing better results (signal levels) than either method working alone Elimination of Redundant Data in a Multi-Drop Network
- a network with multiple transmitters 6710 through 6715 and multiple receivers 6720 through 6724 are installed in vanous locations and each of which may be required to assure adequate coverage
- a common processor 6740 with some type of shared medium 6730, such as a multi-drop bus, such as an RS- 485 bus, a local area network, USB, FireWire, etc
- Poll-response, Ethernet, and token-ring protocols are just three of many methods that would serve this pu ⁇ ose, and would be used whenever some type of data collection and/or processmg is to be performed at a central location
- multiple receivers R2, R3, and R4 may, or may not, receive the same transmitted message 6717 from transmitter T4 Each of these receivers would then attempt to forward the message to the application processor 6740
- Present network systems allow the bus penpherals (the receivers) to forward all messages to the common processor 6740, forcing the processor 6740 to detect and eliminate redundant messages
- this technique increases bus traffic and forces the processor to perform extra processmg to detect and eliminate redundant data messages
- the present invention eliminates this extra bus traffic by requi ⁇ ng that the receivers monitor the bus 6730 for redundant data messages Whenever a data message is received, the receiver will store the message m a queue until it is time for that receiver to relay the messages to the common processor 6740 Smce the receiver is attached to a multi-drop network, the receiver is able to momtor all messages transmitted on the bus 6730 Whenever a receiver is not transmitting data to the common processor 6740, that receiver will monitor the bus 6730, reading
- the waiting receiver will compare each data message on the bus with the messages stored in its local message queue Whenever the waitmg receiver detects that another receiver is transmitting a message to the processor 6740 that is identical to a message in its local queue, that waiting receiver will delete the message from its local queue Each waitmg receiver will attempt to eliminate as many messages from its local queue pnor to relaying the messages to the common processor, thereby reducmg bus traffic and reducing the processmg requirements ofthe common processor
- Figure 67 shows that transceivers and/or receivers on the same hard-wired interface communicate with all remote transmitters and transceivers withm a defined proxmuty Further, the present network embodunent uses the same CDMA and system property code for all devices associated with a particular hard-wired line This method allows redundancy and the ability of the system to eliminate redundant messages
- Another embodiment of the present mvention is a very small, battery operated transceiver that inco ⁇ orates combinations of features ofthe single-channel and multi-channel transceiver embodiments
- transceiver can be installed in places and in quantities that are not possible or practical for larger devices
- an attribute of being small is that the transceiver may operate for long periods of time off of battery power, and thus may be used in remote locations where commercial power service (e g , electncal wall outlets) are not available (e g , on top of flagpoles, buildings, and mobile platforms, such as cars, ai ⁇ lanes, etc )
- Such applications might include two-way smoke detection, strobe light and/or sounder control, two-way keypad, two-way thermostate, remote auto-dialer, remote sensor/controller, two-way remote meter reading/power cut-off, and process control/energy management
- Using a battery operated remote transceiver creates problems with feasibility of use and battery life
- conserve power is a challenge for battery operated transceivers that may be located in accessible locations where it is difficult to replace the batteries
- Conventional transmitters conserve power by operatmg in sleep modes where the transmitter alternately sleeps, wakes up, transmits, and then returns to sleep These transmitters are not restncted to transmit on any particular schedule and thus do not care when they transmit, because these transmitters assume that a receiver is continuously available (powered on)
- the BORT will go mto alternate sleep and active cycles, which m turn creates an additional difficulty when the BORT is used in a network setting
- the transceivers must be active dunng predetermined windows of time (l e , scheduled events) Otherwise, one device m the network may transmit while the would-be receive devices are m sleep mode, resultmg m lost data messages To maintain this network coherency, a
- each BORT device turns off its RF front-end (905 in Figure 9) and signal processmg sections (907, 909, 911, 913, 915, 917, and 919, m Figure 9) when not in use Upon a wake-up event and once a full power-up condition is completed, the BORT device
- the BORT device will re-apply power to the RF front-end 905, use the data to determine code phase coherency, and then re-acquire the data signal
- This acquisition process uses a fast search process as previously described, but if no signal is detected, the BORT device must reacquire system timmg, which it does by remainmg active and continuing to acquire data samples until a network synchronization pulse is detected
- the BORT device can query the system transceiver, by transmitting a query message, requesting network timing information
- Figure 68 depicts a BORT application where several system transceivers 6811-6813 maintain communication with a plurality of BORT devices 6801-6803
- a system controller 6820 maintains supervision ofthe system transceivers via multi-drop bus 6825, such as an RS-485 bus or the like
- the transceivers 6811-6813 and BORT devices 6801 -6803 have access to 6 code-division multiple access (CDMA) channels, based on 6 umque PN sequences
- CDMA code-division multiple access
- the network uses CDMA channel 1 for ALOHA-type transmissions 6832, 6833, and the system transceivers use CDMA channel 2 to broadcast system synchronization messages 6830
- a phase ofthe PN sequence will be random throughout the system transceivers, so as to allow all transceivers to broadcast the synchronization message simultaneously This method allows fast signal acquisition without undue destructive self-interference due to the fact that the correlation function is only one chip wide
- the BORT device will power up at a tune 6910 ( Figure 69B) from a low-power sleep mode
- the BORT device will sample one code penod of data at time 6911 and then go off-line at time 6912
- the BORT device will reacquire the signal at time 6914 and wait until the end of the synchromzation signal 6916
- the BORT device will measure and store the duration of the received synchronization signal By keeping a running log ofthe signal duration, the BORT can determine if its wake-up timer is moving relative to the system synchromzation timing If so, the BORT device can then make co ⁇ ections to its wake-up tuner so as to better maintain system coherency
- the system transceivers 6811 -6813 have multiple options after the completion ofthe sync message at time 6916 If no commands need to be transmitted to the BORT devices 6801 -6803, the transcei
- the transceiver pauses for 700 ms pnor to transmitting command message 6904
- the system transceivers 6811-6813 can maintain code phase coherence when changing from CDMA channel 2 to CDMA channel 3 In this manner, the BORT devices 6801 -6803 may achieve instant spreading code synchromzation with CDMA channel 3 codes smce there will be no code phase ambiguity
- protocol messages may also be used to mamtam system coherency If one ofthe the BORT devices 6801-6803 wakes up and does not detect a system sync message on CDMA channel 2, then that BORT device may send a 'not acknowledge' (NAK) message to the system transceivers 6811-6813 on CDMA channel 1 Upon receipt ofthe NAK message, the closest ofthe system transceivers 6811-6813 will transmit a timing co ⁇ ection message to the BORT device on CDMA channel 1 The BORT device will adjust its sleep timer accordmgly, and may or may not reply to the transceiver with an ACK message on CDMA channel 1 The BORT device will then go mto sleep mode and wake up during the next available system sync message
- the system controller 6820 can send commands to the system transceiver of the system transceivers 6811-6813 nearest the desired BORT device of the BORT devices 6801-6803 at any time
- This command will be queued and sent behind the next sync pulse, the system controller 6820 creates the timing and gives the command to initiate the sync pulse
- the BORT system includes two types of devices, namely the BORT devices 6801- 6803 and the system transceivers 6811-6813, each of which may include the single channel or the multichannel transceivers ofthe first and second embodiments, respectively
- a flowchart explaining the control process implemented m respective processors m the BORT devices 6801 -6803 begms in Figure 70A
- the process begms m step 7001, where one ofthe BORT devices 6801-6803 is in a low-power sleep state, and then the process contmues to step 7002, where the BORT device powers up mto an active state based upon a wake-up signal provided by a wake-up timer that is preferably contained m the BORT device
- the BORT device executes a coarse search process on CDMA channel 2, where the steps for this coarse search routine begin m step 7070, continuing in step 7071 where the device powers up the RF section on the CDMA channel provided by the calling routine
- the BORT device will
- step 7004 the BORT device makes a tnp event decision in step 7004 If m step 7004 it was decided that a t ⁇ p event occurred, the process proceeds to step 7005 where the BORT device powers up its RF front-end for reception on CDMA channel 2 and demodulates the data message m step 7006 In step 7007, the BORT device determines whether or not the BORT device acquired a synchromzation message If a synchromzation message was present, the BORT device performs an additional coarse search on CDMA 3 (m steps 7008 and 7009) and then searches for an additional data message m step 7020, which is continued m Figure 70B If the respective condition of either step 7004 or step 7007 is not met, the BORT device has become active and has not detected a valid synchronization message, and so control is then passed to step 7010
- step 7010 If the BORT device is receive only, the BORT device remains active, repeating steps 7003 through 7006 until a subsequent synchronization message is detected, satisfying the condition of step 7007 From step 7010, if the device has transmit capability, then the device has the option to power up its RF section m step 7011 m preparation for transmitting a handshaking message The process then proceeds to step 7012 where the BORT device initiates a handshaking protocol with a system transceiver on CDMA channel 1 to acquire system timing information and then proceeds to step 7060, which is the beginning of a shutdown routme
- step 7062 the BORT device sets the low-power sleep timer correctly so that the BORT device will awaken during the next network synchronization penod Other tasks are performed as necessary to minimize sleep cu ⁇ ent loading and to assist the BORT device in its subsequent wake-up interval Finally, the shutdown process proceeds to step 7063 where the BORT device enters a low-power sleep state
- Step 7020 initiates a data message search process which occurs after the BORT device has performed a coarse search, as was discussed in reference to step 7007 in Figure 70A
- the BORT device starts a message tuner m step 7022 and receives and demodulates the message m step 7023
- m step 7024 the BORT device ve ⁇ fies that the mcommg message was mtended for that device If that BORT device was the mtended recipient ofthe message, the process contmues to step 7025 where the BORT device verifies that the incommg message was valid If the message was valid, then the process continues to step 7026 where the BORT device transmits an acknowledgment on CDMA channel 1 and then in step 7027 responds to any commands that were embedded within the message
- the process proceeds to step 7028, where BORT device determines if there are any outgoing messages to be transmitted to the system transceivers 6811-6813 From step 7021 , if the BORT device
- step 7060 which initiates the shutdown procedure If there are one or more messages to be transmitted to the system transceivers 6811-6813, the BORT device will initiate preparations for transmission m step 7029 From step 7026, if the received message had an error, the process proceeds to step 7032 where the device determines if the message timer has expired If the tuner has expired, then the BORT device will quit (e g , time out) and pass control to step 7028 If the timer has not expired, the BORT will send a "not acknowledge" command on CDMA 1 (step 7033) The process then proceeds to step 7034 where the device performs a coarse search on CDMA channel 1 In step 7035, if no tnp condition is met, then the device performs the steps of 7033 and 7034 until either a trip condition is met or the timer expires If a trip condition is met m 7035, the process proceeds to step 7036 where the BORT device will apply power to its RF front-end
- step 7038 the BORT device ve ⁇ fies that the mcommg message was mtended for that device If the BORT device was the mtended recipient ofthe message, the process continues to step 7039 where the BORT device verifies that the commg message was valid If the message was valid, the process contmues to step 7026 where the BORT device transmits an acknowledgment on CDMA channel 1 If the conditions of either steps 7038 or 7039 are not met, then process control is returned to step 7032
- step 7030 the device will power down its RF front-end and then seed a random timer as shown m step 7030
- the process continues in step 7040, as will be discussed m reference to Figure 70C
- step 7042 the BORT device powers up its RF front-end with channel CDMA 1 settings as its default settings
- the BORT device is configured so that an external event (step 7080) can cause the device to awaken from sleep mode (step 7041 ) and power up its RF section in CDMA channel 1 (step 7042)
- step 7043 the BORT device will start its message timer in 7043, and then transmit the outgomg messages in step 7044 At this point, the BORT device is expecting an acknowledgment from the system transceiver
- step 7045 the device performs a coarse search on CDMA channel 1
- step 7046 a trip decision is made If a trip occurred, the BORT device will receive and demodulate the message m 7047
- step 7118 If an acknowledgment is received m step 7118, the transceiver clears its message queue for that particular BORT device step 7120 and then the proceeds to step 7110, (as will be discussed in reference to Figure 7 IB) From step 7118, if the transceiver does not receive an acknowledgment from the BORT device, it will then check to see if the message timer has expired If the timer has not expired, control is returned to step 7116. where the message is retransmitted to the BORT device If the timer has expired, control is passed to step 7110 ( Figure 7 IB)
- step 7130 the system transceiver monitors CDMA channel 1 for mcommg messages from the BORT devices 6801 -6803
- the transceiver remains in this loop until in step 7132 it is determined that either a message is received in step 7134 or (as was discussed m reference to Figure 71 A) the transceiver receives a message from the system controller to transmit a synchromzation pulse (step 7104)
- step 7134 the transceiver starts its message tuner and then in step 7136 transceiver receives and demodulates the message
- Decision step 7138 determines whether or not the message was valid If the message was invalid, the process proceeds to step 7140 where the transceiver transmits a "not acknowledgment" message If the message tuner has expired (step 142), then process control returns to step 7130 to momtor for additional messages Otherwise, process control returns to step 7130
- step 7136 to attempt to re-acquire the message From step 7138, if the message was valid, the transceiver will transmit an acknowledgment message (step 7144) and respond to the message if necessary (step 7146) If there is any queued message for this particular BORT device, process control returns to step 7150 (as is seen in Figure 71 A), otherwise, control is returned to step 7130
- Figures 72, 73 , 74, 75, 76 and 77 show an alternative time division multiple access-based (TDMA) system/network architecture for the BORT devices The following discussion explains the low level operation ofthe BORT system devices, as were previously discussed
- Figure 72 shows a steady state communication timing diagram between a system transceiver and a BORT device for three types of messages
- the term steady state means that these are messages used for normal exchange of information in three modes of operation Initialization and exception handling will be discussed following the steady state discussion
- the system architecture is configured to minimize power dram at the BORT device A significant amount of battery power is expended m the BORT device whenever it receives RF energy or transmit messages, a modest amount of battery power is expended whenever the BORT device is active, but has selected circuitry in a reduced power state, examples including initialization, Fast Serial Search as discussed earlier, and sleep mode preparation, and a minimum amount of battery power is expended while the BORT device is m sleep mode because the only active circuit is a low power oscillator and counter
- the overall system architecture is configured to maintain positive control of the BORT devices with recovery mechamsms for re-establishing a communication link in the event of a lost message due to tuning error or interference
- the system transceivers behave predictably over time, and as discussed before, the BORT devices wake up on a schedule so as to retneve a system sync message
- the system controller manages the synchronization process, which is a different approach than pre-arranged options such as staggered, coincident or mterleaved system transceiver sync intervals
- the system sync interval is fixed at 5 seconds with all transceivers interleaved and timmg controlled by the system controller
- Other options are also available, the preferences for each option depending on unplementation trade-offs including consideration of on-air time, probability of receipt based on mterleaved system controllers and asynchronous neighbor interference
- Figures 72A-C respectively show three messages which are all used to maintain sync with the system transceiver
- the sync message is the most common system message (Figure 72A), where this message occurs once every sync interval, 5 seconds for the pu ⁇ oses of this discussion
- the sync message is the most common system message
- the BORT device continues to demodulate the remaining data 7218, detecting the message type and transceiver ID.
- the message type data field instructs the BORT device that the message is for sync only and no further action is required.
- the transceiver ID data field instructs the BORT device that it is accurately tracking the same system transceiver and has not drifted off with another transceiver. A positive lock for system integrity is therefore established by the BORT device without a need to energize a transmit circuit for the most common of system exchanges.
- Figure 72B shows a second steady state communication exchange denoted as a Point to Point message between a system transceiver and a BORT device.
- This message may occur once every sync interval in place of a sync message. In normal operation this message is infrequent relative to the sync message by an order of magnitude.
- the system transceiver appends additional data to a sync message intended for a specific BORT device. It is assumed that the system controller maintains an allocation database for which BORT devices are slaved to which system transceivers. The allocation mechanism will be discussed later in the discussion of system initialization.
- Figure 72B shows the system transceiver transmit process followed by the receive process.
- the bottom line shows the BORT receive process followed by the acknowledge (transmit) process.
- the system transceiver sends the Point to Point message leader 7222, followed by the sync 7226, message type 7228 and transceiver ID 7230 data patterns.
- additional data is appended to include a BORT ID 7231 and optional data 7232 followed by the CRC 7234.
- the BORT device follows the normal wake-up process and samples a code repetition interval 7242, performs search processes and demodulates the message 7244.
- the BORT decodes the message as a Point to Point message, notes the transceiver ID and his BORT ID and responds with an acknowledge (ACK).
- ACK acknowledge
- the ACK follows similar structure including a leader 7246, followed by data fields of sync 7248, message type (ACK) 7250, BORT ID 7252, optional data 7254 and a CRC 7256.
- the system transceiver is always in listen mode when not transmitting, and so the transceiver detects the BORT acknowledge 7236 and demodulates the ACK 7238 completing the point to point exchange.
- the system controller either polls the ACK from the system transceiver or the transceiver initiates the interchange completing a positive handshake to the system controller.
- Figure 72C shows a third steady state communication exchange denoted as an "All Call" message between a system transceiver and a BORT device. This message may occur once every sync interval in place of a sync message.
- the message may optionally include end-user data 7268 followed by the CRC 7270 Every BORT device slaved to the system transceiver issuing the All Call follows its normal wake-up process and samples a code repetition mterval 7278, performs search processes and demodulates the message 7280 When the BORT decodes the message as an All Call message, the BORT notes the transceiver ID and responds with an acknowledge
- ACK A high potential for collision exists as all BORT devices are trying to ACK the message simultaneously So as to reduce contention probability, a delay is initiated by the BORT pnor to sending the ACK to stagger the respective replies to the system transceiver
- the BORT calculates the delay 7282 based on the sync interval divided by the BORT ID (or a number of bits in the BORT ID) which staggers the BORT devices to assist in collision avoidance
- the ACK data structure mcludes a leader 7284, followed by data fields of sync 7286, message type (ACK) 7288, BORT ID 7290, optional data 7292 and a CRC 7294
- the system transceiver is always m listen mode when not transmitting 7272
- the transceiver detects the BORT acknowledge 7273 and demodulates the ACK 7274 completing the communication exchange
- the system controller either polls the ACK from the system transceiver or the transceiver initiates the interchange completing a positive handshake to the system controller
- FIG. 73 A and 73B show a flow diagram ofthe steady state processing co ⁇ esponding with Figure 72
- the steady state process begins m step 7300 where once per sync interval the BORT wakes up, performs a search in step 7302 and makes a decision as to whether a trip condition exists in step 7304
- the coarse search step 7302 is implemented as a subroutme call which is shown starting in step 7380 where the receiver RF front-end components are energized in step 7382, one code repetition interval is sampled and stored m step 7384 and the RF front-end is de-energized prior to a fast serial search step 7388 where the co ⁇ elation function is performed pnor to returning, m step 7390, to step 7302
- This coarse search subroutine is also called, as shown in Figures 75 and 77 Because the present portion ofthe process is a sync processmg thread, the BORT device expects to find a tnp condition, but if no tnp
- the receive thread is initiated m step 7306 and the BORT device performs fine search, waits for the sync byte in order to establish a tune-tag for use later in setting the sleep interval (in step 7308)
- the message is demodulated and data fields extracted
- a check is made to determine if the message originated from the correct transceiver m step 7310 If the transceiver ID is not as expected, then synchronization with the desired transceiver is lost and a re-sync operation is performed m step 7318 If the transceiver ID is correct, then the BORT device has mamtained sync and the message type is evaluated m steps 7312, 7314 and 7316
- the exception handler defaults to the re-sync function of step 7318 If the message type does not match one ofthe three allowed steady state messages, the exception handler defaults to the re-sync function of step 7318 If the received message type is a standard sync message, the algorithm continues through steps 7324 and 7330 to 7332 where the time of sync byte relative to the wake up time is used in a digital lock loop in step 7334 to calculate the sleep tune which will wake up the BORT device in the leader ofthe next sync message The sleep timer is set in step 7336 and the BORT device enters a power down mode in step 7338 awaiting sleep timer wake up in the next sync interval
- step 7314 If the received message was a Point to Pomt message in step 7314, the algonthm continues through steps 7326 and 7340 to 7342 where the BORT ID is evaluated in step 7342 If the received BORT ID matches the ID of the BORT device, the data bits are used to instruct the BORT on which function to perform in step 7344 An optional short delay is performed in step 7346 prior to a BORT ACK message in step 7348 The delay may be necessary to ensure the system transceiver is ready to receive the message, l e settling time for reversal of transmit to receive Once the ACK has been sent, the BORT is ready to enter sleep mode and exits through the sync message process 7330 as discussed before If the received message was an All Call message in step 7316, the algonthm continues through steps 7328 and 7350 to 7352 where the BORT performs the All Call function based on the message data in step 7352 The delay is calculated in step 7354 to stagger the BORT devices acknowledge messages and the ACK
- Figures 74A and B depict the system initialization sequence, where Figure 74A shows a timeline of two system transceivers, both being received by a BORT device on the lines shown m Figure 74B Transceiver A and Transceiver B of Figure 74A are shown staggered to demonstrate this process and the blocks on each line depict a complete transmitted or received message, solid blocks representing message steps in the acquisition flow.
- Each system transceiver continues to transmit sync messages 7402 and 7406 at a predefined system interval.
- the BORT device on power-up or initialization remains active continually searching at 7408 looking for atrip.
- the message is demodulated at times 7410, 7412 for a period so as to establish a good estimate of signal to noise ratio per system transceiver.
- a running average of SNR is maintained for several transceivers. This process is continued until at least four sync messages are collected from at least one system transceiver.
- the BORT device nominates its selection to the system controller at time 7414 which contains as data the transceiver ID and SNR for the best of up to three system transceivers evaluated. All system transceivers hearing the nomination receive it at 7413 , and 7415 and relay it to the system controller along with the SNR of receipt by the system transceivers.
- the system controller now has the SNR measurements relative to the BORT device and all system transceivers able to hear the BORT device where a determination is made as to allocation.
- the system controller allocates which system transceiver is associated with the BORT device and the chosen system controller relays this information to the BORT device at 7416.
- the BORT device continues to receive all messages following its nomination at time 7414 awaiting the allocation assignment which comes in the form of a Point to Point message at time 7416 from the system controller assigned.
- the BORT device receives the allocation Point to Point message at 7418 and acknowledges at time 7420 to complete the Point to Point exchange.
- the BORT device now has its transceiver ID and timing to enter sleep mode and enter steady state operation.
- the BORT device If the allocation message at 7416 does not arrive within a predetermined time-out interval 7422, the BORT device assumes its nomination was not heard and re-issues it. Alternatively, the BORT may sleep for an extended period of time and attempt a new initialization, which may be a reasonable strategy for non-critical systems to compensate for extended power outages or system failures while preserving valuable BORT battery life.
- Figure 75 is a flowchart ofthe above-described procedure, where upon wake-up or initialization determination in step 7500 an array of sync counters is initialized in step 7502 to keep track of how many sync messages have been received from a few system transceivers.
- the BORT device continues to search in step 7504 until a trip is found in step 7506 where the RF front-end section is re-energized in step 7508 and the message is captured and demodulated in step 7510.
- the RF front-end section is placed in a reduced power state in step 7516 and the message is evaluated to see if it is a sync type (repetitive) message in step 7518.
- step 7504 a running average is made for the SNR of each transceiver being evaluated and a counter is incremented in step 7524 counting the number of sync messages received from a specific transceiver. If none ofthe counts exceed a predetermined number as determined in step 7526 the BORT resumes search in step 7504.
- step 7526 If any ofthe counts exceed a predetermined number as determined in step 7526 the three best transceivers are selected based on SNR in step 7528 and a BORT nomination message is sent containing the transceiver ID and SNR for the best three candidates as observed by the BORT 7530.
- a response time-out is started in step 7532 and the BORT searches continually in step 7534 until a trip is received in step 7536, the trip may or may not be the response expected.
- the RF front-end section is energized in step 7542 and the message is demodulated in step 7544 and considered in step 7546. If the message is not the expected response, the BORT device resumes search in step 7534. If the message is the response to the nomination, the allocated system transceiver ID is decoded from the data in step 7548 and stored for future reference in non-volatile memory.
- a Point to Point ACK is formed in step 7550 and sent and the BORT device enters sleep mode in steps 7552 and 7554. If while the BORT is waiting for a response at 7536 and not found, a time-out is incremented in step 7538 and evaluated at step 7540. If the time-out expires before the response is received the process starts over step 7502 (or alternatively the
- BORT device may enter an extended sleep interval to preserve battery conditions before resuming at step 7502).
- a BORT device detects loss of sync, it enters a re-sync mode depicted in Figures 76A-C and 77.
- Figure 76A depicts a first tier of re-sync where the BORT device initiates a negative acknowledge (NAK) exchange. If re-sync fails according to that method, the procedure according to Figure 76B is used as a second tier where the BORT device waits for the next sync message and resets. If re-sync fails according to that method, the procedure according to Figure 76C is used as a third and final tier where the BORT device eventually enters the initialization mode, discussed earlier.
- NAK negative acknowledge
- FIG 76 A the top line illustrates exemplary system transceiver activity at particular times such as sending sync messages 7602 and 7604, as shown.
- the BORT device processes the sync message at time
- the BORT device initiates a NAK message 7612 and begins to immediately listen at 7616 for a NAK Reply 7614. When the system transceiver hears the NAK it repeats the previous message sent at the sync interval as a NAK Reply 7614 which includes a time value to the next scheduled sync message.
- the BORT device seeds the sleep mode timer and resumes normal processing at 7620.
- the BORT device If the system controller fails to respond with the NAK Reply of 7614 or the BORT device cannot hear the NAK Reply, the BORT device continues to listen 7622 until the next sync message is heard at 7624 and normal processing resumes. If the BORT device fails to reacquire by either the NAK or waiting for sync, the BORT assumes the transceiver has failed, and enters an initialization mode 7630 following a predetermined time-out at 7628.
- Figure 77 is a flow diagram ofthe re-sync process starting at step 7700.
- a deterination is made that a re-sync is necessary (steps 7318 or 7320), thus initiating the re-sync process in step 7700, after which in step 7704, a wait time is calculated for generating a NAK message based on the BORT ID (or some number of bits of the BORT ID).
- the wait time is necessary to compensate for the situation where a jammer jams reception ofthe sync message to several BORT devices at the same time. By staggering their reply, the reliability, at the system level, of re-acquiring sync improves.
- the NAK is transmitted by the BORT device in step 7706 and a time-out interval is started in step 7708.
- the BORT device continually searches in step 7710 and upon finding a trip event in step 7712 energizes the RF front-end at step 7718 and demodulates the message in step 7720.
- the sleep timer is seeded with a value to wake up the BORT device in the next sync interval in step 7726 based on the time value passed in the NAK Reply.
- the BORT system then enters a sleep mode in step 7728 and resumes normal operation. If the response received was not a NAK Reply, the response is evaluated to determine if the response is a standard steady state sync type message in step 7724. If so, the timer is set for a standard sync interval in step 7726 and the BORT device sleeps in step 7728.
- the NAK time-out is incremented at step 7713 and evaluated at step 7714. While waiting for a NAK Reply in step 7712, the NAK time-out is incremented in step 7713 and evaluated in step
- the BORT device enters the initialization mode 7716, 7500.
- the mechanisms and processes set forth in the present description may also be implemented using a conventional general pu ⁇ ose microprocessor or digital signal processor (such as a TMS320C40, although, as discussed many of the inventive mechanisms and processes disclosed herein may be implemented in lower cost, lower performance processors) programmed according to the teachings in the present specification, as will be appreciated to those skilled in the relevant art(s).
- Appropriate software coding can readily be prepared by skilled programmers based on the teachings ofthe present disclosure, as will also be apparent to those skilled in the relevant art(s).
- the present invention thus also includes a computer-based product which may be hosted on a storage medium and include instructions which can be used to program a computer to perform a process in accordance with the present invention.
- This storage medium can include, but is not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, magneto-optical disks, ROMs, RAMs, EPROMs, EEPROMs, flash memory, magnetic or optical cards, or any type of media suitable for storing electronic instructions.
- an exemplary single channel embodiment of a transceiver has been described as a first embodiment ofthe present invention (see e.g., Figures 9, 10, 11), and a multi-channel embodiment has also been described as a second embodiment (see, e.g., Figures 9, and 35-36), where features ofthe respective embodiments may be exchanged with one another, albeit for potential penalties of cost, performance and complexity, as has been discussed. Accordingly, the present invention is directed not only to the claims as individually described, but also directed to combinations of the claims and alternative mechanisms as discussed herein.
- the multi-channel transceiver and single channel transceiver may both use a one- bit limited ADC or a multi-bit linear ADC.
- the simplicity ofthe one-bit limited ADC does not require the
- AGC function as discussed in reference to the multi-channel embodiment, and Figure 35 for example, but the single channel embodiment could also use the multi-bit linear ADC, with AGC as discussed herein, although requiring additional processing power.
- both the digital offset approach discussed with respect to Figure 14, as well as the frequency offsetting of the first local oscillator, and cycling through various offsets may be employed in either the single channel or the multi-channel embodiment. Simultaneously computing all the offsets was an option discussed herein, such an option may be more suitable for use in a multi-channel embodiment or a hybrid embodiment between the multi-channel embodiment and single channel embodiment due to processing complexity and cost concerns. As with the other alternatives, penalties paid are in terms of cost and complexity. Similarly, the averaging approach discussed with regard to improving trip sensitivity and limiting decimation loss may also be employed in both the single channel and multi-channel embodiments, albeit for an increase in processing complexity.
- the set-on channel filter approach was discussed with respect to the multi-channel embodiment, see e.g., Figure 39, although it may also be applicable in the single channel embodiment, albeit at a more expensive computation cost to improve sensitivity and process gain during demodulation.
- the various fine search center of mass methods may be implemented in either the single channel or the multichannel embodiment.
- Both the single channel and the multi-channel embodiments are directed to direct sequence spread spectrum transceivers, that may be used in a system or network and both using a PN code as previously been discussed.
- the particular features of the PN code length discussed with respect to Table 3, for example, is applicable to both the single channel and multi-channel embodiments.
- the selection ofthe PN code length is an enabling feature regarding partial decimation as well as FFT radix based on small prime numbers, implemented in both embodiments.
- Figures 30A-F have been presented in the context of the first embodiment, however, these approaches may be employed in either single channel or multi-channel embodiment, albeit for increased computational complexity as discussed herein.
- Figure 34 described a circuit for precharging a voltage controlled oscillator for fast settling acquisition, however, this circuit may also be used in the multi-channel embodiment as well, and any hybrid between the single channel embodiment and the multi-channel embodiment.
- Figures 40-45 discussed various frequency domain code correlators, which were presented in the context ofthe multi-channel embodiment.
- these approaches may also be implemented in the single channel embodiment so as to provide an FFT based down conversation despread and decimation operation subsequent decimation in die frequency domain may be used to expand or set the predetection bandwidth as necessary for system requirements.
- the fast serial search approach discussed with respect to Figures 15A-B and 16, for example, are equally applicable in the multi-channel receiver implementation.
- various power management features ofthe inventive transceiver, as discussed with respect to Figure 9, the battery pack of Figure 10, and that as discussed with respect to the BORT, are equally applicable in a single channel or multi-channel transceivers.
- Figure 25 may be applicable to either the single channel or multi-channel transceivers that use the one-bit limited ADC.
- the respective diversity approaches (antenna and frequency, for example, discussed with respect to Figures 9, 24-27, and Figures 68 (CDMA)), are applicable to both the single channel and multi-channel embodiment, and therefore are also applicable to hybrid embodiments.
- the discussion regarding the BORT system and network (see e.g., Figures 67-77) are equally applicable to the single channel embodiment and the multi-channel embodiment, as either the single channel transceiver, multi-channel transceiver or a hybrid, may be employed in the BORT system network.
Abstract
Description
Claims
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AU86561/98A AU744940B2 (en) | 1997-05-20 | 1998-05-18 | Direct sequence spread spectrum method, computer-based product, apparatus and system tolerant to frequency reference offset |
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US08/929,891 US5999561A (en) | 1997-05-20 | 1997-09-15 | Direct sequence spread spectrum method, computer-based product, apparatus and system tolerant to frequency reference offset |
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Also Published As
Publication number | Publication date |
---|---|
US5999561A (en) | 1999-12-07 |
EP0986860A4 (en) | 2003-05-02 |
US6639939B1 (en) | 2003-10-28 |
EP0986860A2 (en) | 2000-03-22 |
AU8656198A (en) | 1998-12-11 |
AU744940B2 (en) | 2002-03-07 |
WO1998053556A3 (en) | 1999-03-04 |
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