WO1998058385A1 - Memory element with energy control mechanism - Google Patents
Memory element with energy control mechanism Download PDFInfo
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- WO1998058385A1 WO1998058385A1 PCT/US1998/012601 US9812601W WO9858385A1 WO 1998058385 A1 WO1998058385 A1 WO 1998058385A1 US 9812601 W US9812601 W US 9812601W WO 9858385 A1 WO9858385 A1 WO 9858385A1
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- memory
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- memory material
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- electrical
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Classifications
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/80—Arrangements comprising multiple bistable or multi-stable switching components of the same type on a plane parallel to the substrate, e.g. cross-point arrays
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of the switching material, e.g. layer deposition
- H10N70/023—Formation of the switching material, e.g. layer deposition by chemical vapor deposition, e.g. MOCVD, ALD
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/021—Formation of the switching material, e.g. layer deposition
- H10N70/026—Formation of the switching material, e.g. layer deposition by physical vapor deposition, e.g. sputtering
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/841—Electrodes
- H10N70/8413—Electrodes adapted for resistive heating
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/861—Thermal details
- H10N70/8616—Thermal insulation means
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
- H10N70/8828—Tellurides, e.g. GeSbTe
Definitions
- the memory elements of the present invention have the capability of allowing for the creation of a novel, non-hierarchal "universal memory system". Essentially all of the memory in the system can be low cost, archival and fast. As compared to original Ovshinsky-type phase change electrical memories, the memory materials described herein provide over sir, orders of magnitude faster programming time (less than 30 nanoseconds) and use extremely low programming energy (less than 0.1 to 2 nanojoules) with demonstrated long term stability and cyclability (in excess of 10 trillion cycles) . Also, experimental results indicate that additional reductions in element size can increase switching speeds and cycle life.
- EEPROM universal memory Yet another requirement of a EEPROM universal memory is high thermal stability of the information stored therein.
- present computer memory arrays, especially "hard” or archival memory must be thermally stable even at relatively high temperatures. Without this thermal stability data loss may occur leading to the aforementioned loss of credibility.
- an electrically operated, directly overwritable memory element comprising: a volume of memory material having two or more electrical resistance values, the memory material being setable to one of the electrical resistance values in response to a selected electrical input signal without the need to be set to a specific starting or erased electrical resistance value; a pair of spacedly disposed electrical contacts for supplying the electrical input signal; and energy control means for controlling the energy environment of at least a portion of the volume of memory material.
- the energy control means may include thermal control means for controlling the thermal environment of at least a portion of the volume of memory material.
- the energy control means may include electrical control means for controlling the distribution of current within at least a portion of the volume of memory material.
- an electrically operated memory array comprising: a plurality of electrically activated, directly overwritable memory elements, each of the plurality of memory elements including: a volume of memory material having two or more electrical resistance values.
- the volume of memory material can be set to one of the electrical resistance values in response to a selected electrical input signal without the need to be set to a specific starting or erased electrical resistance value; a pair of spacedly disposed electrical contacts for supplying the electrical input signal; and energy control means for controlling the energy environment of at least a portion of the volume of memory material.
- the energy control may include thermal control means for controlling the thermal environment of at least a portion of the volume of memory material.
- the thermal control means may include thermal isolating means for thermally isolating each of the plurality of memory elements from all other of the plurality of memory elements .
- Each of the plurality of memory elements may further include an electrical isolation device electrically isolating each of the plurality of memory elements from all other of the plurality of memory elements.
- Figure la is a stylized cross-sectional view of a single memory element specifically illustrating the heating layers and thermal insulation layers
- Figure lb is a stylized cross-section view of a single memory element specifically illustrating the thermal plug
- Figure 2a is a stylized top view of an array of multiple memory elements showing how the elements would be connected to a set of X-Y addressing lines;
- Figure 2b is a stylized side view of an array of multiple memory elements including a thermal channel for thermally isolating one memory element from all other of the memory elements;
- Erasable electrical memories fabricated from the broad class of chalcogenide materials have employed structural changes that were accommodated by large scale movement of certain atomic species within the material to permit change of phase as the material switched from the amorphous state to the crystalline state.
- electrically programmable chalcogenide alloys formed of tellurium and germanium such as those comprising about 80% to 85% tellurium and about 15% germanium along with certain other elements in small quantities of about one to two percent each, such as sulfur and arsenic
- the more ordered or crystalline state was typically characterized by the formation of a highly electrically conductive crystalline Te filament within the programmable pore of the memory material.
- the formation of the crystalline Te filament required large scale migration of the Te atoms from their atomic configuration in the amorphous state to the new locally concentrated atomic configuration in the Te crystalline filament state.
- the Te which had precipitated out into the crystalline filament was required to migrate within the material from its locally concentrated form in the filament back to its atomic configuration in the amorphous state.
- This atomic migration, diffusion or rearrangement between the amorphous and crystalline states required in each case a relatively long holding or dwell time sufficient to accommodate the migration, thereby making the requisite programming time and energy relatively high.
- the electrically operated, directly overwritable memory element of the present invention comprises a volume of memory material having at least two electrical resistance values.
- the memory material can be set to one of the electrical resistance values in response to a selected electrical input signal without the need to be set to a specific starting or erased resistance value.
- the resistance values of the memory material are electrically detectable.
- the memory material is non-volatile and will maintain the integrity of the information stored by the memory cell (within a selected margin of error) without the need for periodic refresh signals .
- the memory material may be formed from a plurality of constituent atomic elements, each of which is present throughout the entire volume of memory material.
- the memory material includes one or more elements selected from the group consisting of Te, Se, Ge, Sb, Bi, Pb, Sn, As, S, Si, P, 0 and mixtures or alloys thereof. More preferably, the memory material includes one or more chalcogen elements.
- the memory material may further include one or more transition metal elements.
- transition metal as used herein includes elements 21 to 30, 39 to 48, 57 and 72 to 80.
- the one or more chalcogen elements are selected from the group consisting of Te, Se, and mixtures or alloys thereof. More preferably, the one or more chalcogen elements includes a mixture of Te and Se.
- the one or more transition metal elements are selected from the group consisting of Cr, Fe, Ni, Nb, Pd, Pt and mixtures or alloys thereof. More preferably the transition metal includes Ni . Specific examples of such multi-element systems are set forth hereinafter with respect to the Te:Ge:Sb system with or without Ni and/or Se.
- the specific semiconductor alloys employed in fabricating the memory devices include chalcogenide elements which are characterized by the presence of "lone pair" valence electrons.
- the tellurium alloys described herein have a valence band made up of lone pair states. Since four (4) p shell electrons are present in Te, and the Te atom is chemically bonded by two of these bonding electrons in the p shell, the other two outer electrons (the lone pair) are not utilized for bonding purposes and hence do not substantially change the atomic energy of the system. In this regard, note that the highest filled molecular orbital is the orbital which contains the lone pair electrons.
- modulation of the programming characteristics of two or three terminal semiconductor devices fabricated from the microcrystalline materials of the present invention may be controlled such that repeatable and detectable resistance values can be effected. It has been found that, in order for the materials of the present invention to be quickly set by low energy input signals to a desired conductivity (determined by the Fermi level position) , it is only necessary that said materials are capable of stable (or long lived metastable) existence within at least two different Fermi level positions, which Fermi level positions are characterized by substantially constant band gaps but different electrical conductivities. As noted above, it is also believed that the relatively small crystallite size may contribute to the rapid transition between detectable values of resistance.
- Crystallite sizes of the widest preferential range of representative materials embodying the present invention have been found to be far less than about 2000 A, and generally less than the range of about 2,000 A to 5,000 A which was characteristic of prior art materials. Crystallite size is defined herein as the diameter of the crystallites, or of their "characteristic dimension" which is equivalent to the diameter where the crystallites are not spherically shaped.
- this composition may be characterized as Te,Ge b Sb,r, r ,- ia - R) .
- Te,Ge b Sb,r, r ,- ia - R these ternary Te-Ge-Sb alloys are useful starting materials for the development of additional memory materials having even better electrical characteristics.
- Melts were prepared from various mixtures of Te, Ge and Sb, the melts segregated into multiple phases upon rapid solidification. Analysis of these rapidly solidified melts indicated the presence of ten different phases (not all present in any one rapidly solidified melt) . These phases are: elemental Ge, Te and Sb, the binary compounds GeTe, and Sb,Te, and five different ternary phases.
- the elemental compositions of all of the ternary phases lie on the pseudobinary GeTe-Sb,Te, line.
- the memory elements of the instant patent application possess substantially non-volatile set resistance values. However, if the resistance value of the instant memory elements does, under some circumstances, drift from its original set value, "compositional modification", described hereinafter, may be used to eliminate for this drift.
- the term “non-volatile” will refer to the condition in which the set resistance value remains substantially constant for archival time periods.
- software including the feedback system discussed hereinafter
- drift of the resistance value of the memory elements can, if left unimpeded, hinder gray scale storage of information, it is desirable to minimize drift.
- the memory element further includes a pair of speacedly disposed electrical contacts for supplying the electrical input signal to the memory material.
- at least one of the spacedly disposed electrical contacts is a thin-film electrical contact layer.
- each of the electrical contacts is an electrical contact layer.
- the electrical contact layers are shown in Figure la as thin-film layers 32 and 40.
- the instant inventors have focused on ways of controlling the thermal environment of the material. This includes, but not limited to, ways of increasing the amount of heat energy entering at least a portion of the volume of memory material, ways of reducing the amount of heat loss from at least a portion of the volume of memory material, and ways of controlling the distribution of heat energy within at least a portion of the volume of memory material .
- the memory element may include only a single heating layer deposited adjacent or remote to the memory material, and either above or below the memory material. As well, heating layers may be positioned laterally from at least a portion of the volume of memory material.
- At least one of the heating layers may include one or more elements selected from the group consisting of Ti, V, Cr, Zr, Nb, M, Hf, Ta, W, and mixtures or alloys thereof, and two or more elements selected from the group consisting of B, C, N, 0, Al, Si, P, S, and mixtures or alloys thereof.
- at least one of the heating layers includes Ti, Al, and N. More preferably, at least one of the heating layers includes a compound having a composition of, in atomic percent, between about 10% to 60% titanium, 5% to 50% aluminum and 10% to 60% nitrogen.
- each of the heating layers 34 and 38 may include titanium aluminum nitride.
- the heating layers may be deposited by such methods as physical vapor deposition including evaporation, ion plating as well as DC and RF sputtering deposition, chemical vapor deposition, and plasma assisted chemical vapor deposition.
- physical vapor deposition including evaporation, ion plating as well as DC and RF sputtering deposition, chemical vapor deposition, and plasma assisted chemical vapor deposition.
- the exact method used depends upon many factors, one of which being deposition temperature constraints imposed by the composition of the chalcogenide target material.
- the thermal control means may further include thermal insulation means for controlling the transfer of heat energy out of at least a portion of the memory material 36.
- the thermal insulation means may be embodied by one or more thermal insulation layers which partially encapsulate the memory material 36 and which reduce the transfer of heat energy from at least a portion of the volume of memory material.
- Figure la shows an embodiment of the memory element 30 using two thermal insulation layers, a first thermal insulation layer 31 deposited remote to and below the memory material 36 and a second thermal insulation layer 41 deposited remote to and above the memory material 36. As shown in Figure la, thermal insulation layer 41 has been appropriately etched to permit electrical contact between electrode 42 and electrical contact layer 40.
- thermal insulation layer 41 has been etched so that electrode 42 is laterally displaced from the volume of memory material proximate the region of contact between thermal insulation layer 34 and memory material 36. Such lateral displacement further reduces the transfer of heat out of at least a portion of the volume of memory material by reducing the effect of the thermal conducting properties of layer 42.
- the thermal insulation layers are chosen to have good thermal insulating properties.
- the insulating properties of the thermal insulation layers depend upon the specific heat and thermal conductivity of the thermal insulation layer material. Decreasing the specific heat and/or the thermal conductivity of the material increases the insulating properties of layers thereby slowing the rate of heat loss from the volume of memory material. Hence, manipulation of these material properties may be used as a means of controlling and optimizing the cooling rate of the memory material.
- At least one of the thermal insulation layer has a thermal conductivity less than about 0.2 joule-cm per cm 2 - Kelvin-sec. More preferably, at least one thermal insulation layer has a thermal conductivity less than about 0.01 joule-cm per cm-Kelvin-sec. Most preferably, at least thermal insulation layer has a thermal conductivity less than about 0.001 joule-cm per cm 2 -Kelvin-sec.
- each of the thermal insulation layers affects the insulating properties of the layers (and hence the cooling rate of the memory material) .
- increasing the thickness of the insulation layers increases the insulating properties, further slowing the cooling of the memory material.
- At least one of the thermal insulation layers has a thickness between about 100 A to about 10,000 A. More preferably, at least one the thermal insulation layers has a thickness between about 500 A to about 7500 A. Most preferably, at least one of the thermal insulation layers has a thickness between about 1000 A and about 5000 A.
- the thermal control means may include a volume of thermal insulating material that is at least partially encapsulated within the volume of memory material.
- This volume of thermal insulating material is referred to herein as a "thermal plug".
- the thermal plug provides a means of controlling the distribution of the heat energy within the volume of memory material.
- the thermal plug may be formed from the same materials selected for the thermal insulation layers described above.
- Figure lb shows an embodiment of a memory element using a thermal plug 45 encapsulated within the volume of memory material 36.
- the layer of memory material 36 may be formed of a multielement semiconductor material, such as the chalcogenide materials disclosed herein.
- the pore diameter is the average cross-section of the smallest region of contact between the memory material 36, and the heating layers 34, 38.
- the pore diameter of memory material 36 is less than about one to two micrometers or so, although there is no practical limit on the lateral dimension. It has been determined that the diameter of the actual conductive 'path of the high conductivity material is significantly less than a micrometer.
- the pore diameter can thus be as small as lithography resolution limits will permit and, in fact, the smaller the pore, the lower the energy requirements for programming. It is preferred, that the pore diameter be selected such that it conforms substantially with the cross section of the memory material whose resistance is actually altered when the material is programmed to a different resistance.
- the pore diameter of the memory material 36 is therefore preferably less than about one micrometer so that the volume of the memory material 36 is limited, to the extent lithographically possible, to that volume of material 36 actually programmed.
- the energy control means discussed above may include an electrical control means for controlling the distribution of electrical current within at least a portion of the volume of memory material.
- the electrical control means may be implemented by one or more resistive layers.
- at least one of the resistive layers is deposited adjacent to the volume of memory material.
- Each resistive layer is formed from material having sufficient electrical resistivity to spread the distribution current within at least a portion of the volume of memory material, thereby reducing electromigration within the material.
- at least one resistive layer has a resistivity greater than about 1 x 10 "r ' ohm-cm. More preferably, at least one resistive layer has a resistivity greater than about 1 x 10 "1 ohm-cm. Most preferably, at least one resistive layer has a resistivity greater than about 1 x 10 "1 ohm-cm.
- Materials from which at least one of the resistive layers may be formed include, but are not limited to, titanium aluminum nitride, titanium carbonitride, and titanium silicon nitride.
- Other materials include amorphous carbon, amorphous silicon or a dual amorphous carbon/amorphous silicon structure.
- the memory element shown in Figure la may be formed in a multi-step process. Layers 31, 32, 34 and 46 are first deposited and layer 46 is etched to form the pore. The layers 36, 38, 40, and the thermal insulation layer 41 are then deposited. The entire stack of layers is then etched to the selected dimensions. Deposited on top of the entire structure is electrical dielectric material 39 such as Si0 2 or Si,N 4 . The electrical dielectric material 39 and the thermal insulation layer 41 may then be selectively etched so that electrode 42 is appropriately positioned relative to the pore.
- the electrode grid structure 42 extends perpendicular in direction to conductors 12 and completes the X-Y grid connection to the individual memory elements. Overlaying the complete integrated structure is a top encapsulating layer of a suitable encapsulant such as Si 3 N 4 or a plastic material such as polyimide, which seals the structure against moisture and other external elements which could cause deterioration and degradation of performance.
- a suitable encapsulant such as Si 3 N 4 or a plastic material such as polyimide, which seals the structure against moisture and other external elements which could cause deterioration and degradation of performance.
- the Si 3 N 4 encapsulant can be deposited, for example, using a low temperature plasma deposition process.
- the polyimide material can be spin deposited and baked after deposition in accordance with known techniques to form the encapsulant layer.
- an electrically operated memory array comprising a plurality of the memory elements described above.
- One embodiment of a memory array is a two-dimensional memory array of memory elements. The top view of this embodiment is shown in Figure 2a. As shown, the devices form an X-Y matrix, of memory elements.
- the memory array includes an X-Y electrode grid of addressing lines for selectively setting and reading the individual memory elements.
- the horizontal strips 12 represent the X set of an X-Y electrode grid and the vertical strips 42 represent the Y set of addressing lines.
- each memory element in the memory array is an electrical isolation device which electrically isolates each memory element from all other memory elements in the memory array.
- Figure 3 shows a schematic diagram of the two-dimensional memory array from Figure 2a. Figure 3 shows how electrical isolation can be accomplished using diodes.
- the circuit comprises an X-Y grid with the memory elements 30 being electrically interconnected in series with isolation diodes 26.
- Address lines 12 and 42 are connected to external addressing circuitry in a manner well known to those skilled in the art.
- the purpose of the electrical isolation devices is to enable each discrete memory element to be read and written without interfering with information stored in any other memory element of the matrix.
- the dynamic range of resistances also allows for broad gray scale and multilevel analog memory storage.
- Multilevel memory storage is accomplished by dividing the broad dynamic range into a plurality of sub-ranges or levels.
- the continuous resistance programmability allows for multiple bits of binary information to be stored in a single memory cell.
- This multilevel storage is accomplished by mimicking multiple bits of binary information in pseudo-analog form and storing this analog information in a single memory cell.
- each memory cell would be provided with the capability of storing n bits of binary information.
Abstract
Description
Claims
Priority Applications (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE69827598T DE69827598T2 (en) | 1997-06-19 | 1998-06-16 | MEMORY ELEMENT WITH ENERGY CONTROL MECHANISM |
EP98931330A EP0938731B1 (en) | 1997-06-19 | 1998-06-16 | Memory element with energy control mechanism |
AU81482/98A AU8148298A (en) | 1997-06-19 | 1998-06-16 | Memory element with energy control mechanism |
CA002269857A CA2269857C (en) | 1997-06-19 | 1998-06-16 | Memory element with energy control mechanism |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US08/878,870 | 1997-06-19 | ||
US08/878,870 US5933365A (en) | 1997-06-19 | 1997-06-19 | Memory element with energy control mechanism |
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WO1998058385A1 true WO1998058385A1 (en) | 1998-12-23 |
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PCT/US1998/012601 WO1998058385A1 (en) | 1997-06-19 | 1998-06-16 | Memory element with energy control mechanism |
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US (1) | US5933365A (en) |
EP (1) | EP0938731B1 (en) |
AU (1) | AU8148298A (en) |
CA (1) | CA2269857C (en) |
DE (1) | DE69827598T2 (en) |
RU (1) | RU2214009C2 (en) |
TW (1) | TW421893B (en) |
WO (1) | WO1998058385A1 (en) |
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Also Published As
Publication number | Publication date |
---|---|
TW421893B (en) | 2001-02-11 |
US5933365A (en) | 1999-08-03 |
CA2269857A1 (en) | 1998-12-23 |
DE69827598D1 (en) | 2004-12-23 |
AU8148298A (en) | 1999-01-04 |
CA2269857C (en) | 2005-12-20 |
RU2214009C2 (en) | 2003-10-10 |
EP0938731B1 (en) | 2004-11-17 |
EP0938731A1 (en) | 1999-09-01 |
DE69827598T2 (en) | 2005-12-29 |
EP0938731A4 (en) | 2002-03-20 |
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