WO1998059375A1

WO1998059375A1 - Non-volatile nano-cristalline storage cell

Info

Publication number: WO1998059375A1
Application number: PCT/DE1998/001136
Authority: WO
Inventors: Hans Reisinger
Original assignee: Siemens Aktiengesellschaft
Priority date: 1997-06-19
Filing date: 1998-04-23
Publication date: 1998-12-30
Also published as: DE19726085A1

Abstract

The invention relates to a non-volatile nano-cristalline storage cell comprising an MOS transistor with a first dielectric layer (51) acting as a gate dielectric and a second dielectric layer (53) between which nano-crystals (52) are arranged. The gate electrode of the MOS transistor contains p<+> doped silicon so that when a negative voltage is applied to the gate electrode, holes chiefly from the channel area (4) tunnel through the first dielectric layer (51) into the nano-crystals (52).

Description

description

NON-VOLATILE NANO CRYSTAL STORAGE CELL

For permanent storage of data, non-volatile memory cells, so-called SONOS cells or MNOS cells, have been proposed, each comprising a special MOS transistor (see, for example, Lai et al, IEDM Tech. Dig. 1986, pages 580 to 583). The MOS transistor comprises a gate dielectric, which comprises at least one silicon nitride layer below the gate electrode and a SiÜ ₂ layer between the silicon nitride layer and the channel region. Charge carriers are stored in the silicon nitride layer to store the information.

The thickness of the SiO 2 layer in these non-volatile memory cells is at most 2.2 nm. The thickness of the Si3N ₄ layer in modern SONOS memories is usually about 10 nm. Another SiO ₂ layer is usually provided between the silicon nitride layer and the gate electrode which has a thickness of 3 to 4 nm. These non-volatile memory cells can be electrically written and erased. During the writing process, such a voltage is applied to the gate electrode that charge carriers tunnel out of the substrate through the maximum 2.2 nm thick SiO 2 layer into the silicon nitride layer. To erase the gate electrode is wired so that the charge carriers stored in the silicon nitride layer tunnel through the maximum 2.2 nm thick SiO 2 layer into the channel area and from the channel area charge carriers of the opposite conductivity type tunnel through the SiÜ2 layer into the silicon nitride layer. At the same time, charge carriers of the first conductivity type tunnel from the gate electrode into the silicon nitride layer. The layer thicknesses are dimensioned such that the charge carrier transport to the channel area predominates in comparison to the charge carrier transport from the gate electrode. The deletion process typically requires times of 100 ms. The SONOS cells have a data retention time of ≤ 10 years. This time is too short for many applications, for example for storing data in computers.

For applications in which longer times are required for data retention, it is known to use EEPROM cells with a floating gate as the non-volatile memory. In these memory cells, for example from Lai et al, IEDM Tech. Dig. 1986, pages 580 to 583, a floating gate electrode is arranged between a control gate electrode and the channel region of the MOS transistor, which is completely surrounded by dielectric material. The information is stored in the form of charge carriers on the floating gate electrode. These memory cells, which are also referred to as FLOTOX cells, can be electrically written and erased. For this purpose, the control gate electrode is connected to such a potential that charge carriers flow from the channel area onto the floating gate electrode (writing) or charge carriers flow from the floating gate electrode into the channel area (erase). The deletion process in FLOTOX cells requires times of typically 100 ms. The FLOTOX cells have data retention times greater than 150 years.

Compared to the SONOS cells, however, they are complicated to set up. Furthermore, the space requirement of the FLOTOX cells is greater in comparison to the SONOS cells, since the control gate electrode has to overlap the floating gate electrode laterally. Finally, the so-called radiation hardness of FLOTOX cells is limited. Radiation hardness refers to the insensitivity of the stored charge to external radiation sources and / or electromagnetic fields.

Furthermore, it has been proposed (see Tiwari et al., Appl. Phys. Lett. 68 (19), No. 4, March 1996) to use a MOS transistor as the memory cell, which acts as a gate dielectric has two silicon oxide layers with nanocrystals arranged between them. The nanocrystals consist of silicon and are small, independent silicon bodies. They have a diameter of approximately 5 nm and spacings of approximately 5 nm. Charge is stored in these nanocrystals and, like the charge stored on a floating gate of an EEPROM, influences the threshold voltage of the MOS transistor. The silicon oxide layer arranged below the nanocrystals acts as a tunnel oxide. The thickness of the tunnel oxide is approximately 1 to 2 nm. The time for data retention in these memory cells is a few weeks and is therefore too short for many applications, for example for storing data in computers.

The invention is based on the problem of specifying a non-volatile memory cell which takes less than 1 s for the deletion process, which is simple in construction and can be integrated in a high packing density and which has improved radiation hardness in comparison with the FLOTOX cells.

According to the invention, this problem is solved by a memory cell according to claim 1. Further developments emerge from the subclaims.

The non-volatile memory cell comprises a MOS transistor with source region, channel region, drain region, gate dielectric and gate electrode. The gate dielectric has a first dielectric layer and a second dielectric layer, nanocrystals being arranged between the first dielectric layer and the second dielectric layer. The gate electrode contains p ⁺ -doped silicon. Compared to FLOTOX cells, this memory cell has a lower write / erase voltage and, compared to SONOS cells, a longer time for data retention (retention time). The memory cell according to the invention differs from the known memory cell in that the gate electrode contains p ⁺ -doped silicon. In comparison to n-doped silicon or metal, which is used as a gate electrode in conventional cells, the p ⁺ -

Doping reduces the occupancy probability of electronic states in the gate electrode by approximately a factor of 10 ²⁰ . During the quenching process, therefore, no electrons can tunnel from the gate electrode into the nanocrystals. The memory cell according to the invention is therefore erased by tunneling holes from the channel region through the first dielectric layer into the nanocrystals and by tunneling electrons from the nanocrystals into the channel region.

If n-doped silicon or metal is used as the gate electrode, electrons also tunnel from the gate electrode into the nanocrystals, which also have to be neutralized during the quenching process. This electron current is suppressed in the memory cell according to the invention in that the number of electrons in the gate electrode is reduced through the use of p ⁺ -doped silicon. The time for the erase process is reduced in the memory cell according to the invention by a factor of approximately 10 ⁵ to 10 ⁸ compared to conventional memory cells, with the tunnel oxide thickness being the same in each case.

This applies regardless of the thickness of the first dielectric layer, which acts as a tunnel oxide. The layer thickness of the first dielectric layer is therefore freely selectable and is preferably set so that the memory cell has the time required for the respective application to receive data, which also depends on this layer thickness.

The first dielectric layer and the second dielectric layer are preferably formed from silicon oxide. The thickness of the first dielectric layer is 2 to 5 nm, the thickness of the second dielectric layer is 1 to 2 nm larger than that of the first dielectric layer. The thickness of the first dielectric layer in the range between 2 and 5 nm is greater than that of the memory cell known from Tiwari and thereby improves the time for data retention (retention time) compared to the memory cell known from Tiwari.

This embodiment of the invention makes use of the knowledge that, in conventional memory cells, the charge transport through the first dielectric layer takes place primarily through direct tunneling because of the thickness of at most 2 nm. The tunnel probability for direct tunneling and thus the amperage for the transport of charge carriers through direct tunneling and modified Fowler-Nordheim

Tunneling depends mainly on the thickness of the tunnel barrier, i.e. the thickness of the first dielectric layer, and on the electric field. With a layer thickness of the tunnel oxide of at most 2 nm, in the case of electrical fields below 10 MV / cm, the current always prevails through direct tunneling through the first dielectric layer. Via this direct tunnel current and modified Fowler-Nordheim tunneling, both the writing and the deletion of the information is carried out by appropriate wiring of the gate electrode.

The embodiment of the invention also makes use of the knowledge that even without wiring the gate electrode in the known memory cell, a tunnel current, which is due to direct tunneling, flows from the nanocrystals through the first silicon oxide layer to the channel region. It was found that this direct tunnel current is decisive for the time for the data retention.

Furthermore, the knowledge is exploited that the tunnel probability for direct tunneling decreases sharply with increasing thickness of the first dielectric layer and is very small with a thickness of at least 3 nm. Since in this embodiment of the memory cell according to the invention the first dielectric layer is at least 2 nm thick and the second dielectric layer is 1 to 2 nm thicker than the first dielectric layer, a charge carrier transport from the nanocrystals to the gate electrode or to the channel region takes place in this memory cell by direct tunneling largely avoided. This means that the charge stored in the nanocrystals remains virtually unlimited. The time for data retention in the memory cell according to the invention is therefore significantly longer than in conventional memory cells.

The thicknesses of the first dielectric layer and the second dielectric layer in the memory cell according to the invention are preferably selected such that they differ by an amount in the range between 0.5 and 2 nm. The smaller of the two thicknesses of the first dielectric layer and the second dielectric layer is in the range between 2 and 5 nm. In this embodiment, the gate dielectric is electrically symmetrical. Due to the different thicknesses of the first dielectric layer and the second dielectric layer, the work function differences between the channel region and the gate electrode and mainly the generally positive gate voltage applied during reading operation are taken into account.

Since the thicknesses of the first dielectric layer and the second dielectric layer are each at least 2 nm, the tunneling probability for direct tunneling of charge carriers through the two dielectric layers is very small. The charge carrier transport takes place during writing and reading only through Fowler-Nordheim tunnels through the first dielectric layer or second dielectric layer. The current strength of the charge carrier transport through Fowler-Nordheim tunnels only depends on the strength of the adjacent one electric field. It is not explicitly dependent on the thickness of the tunnel barrier.

When a positive voltage is applied to the gate electrode, Fowler-Nordheim tunneling of electrons from the channel region through the first dielectric layer into the nanocrystals predominates. By applying a positive voltage to the gate electrode, information is written into the memory cell. Since the number of electrons in the conduction band of the gate electrode is reduced due to the use of p ⁺ -doped silicon, tunneling of holes from the channel region through the first dielectric layer into the nanocrystals predominates when a negative voltage is applied to the gate electrode. Because of the potential relationships, Fowler-Nordheim tunneling of electrons from the gate electrode through the second dielectric layer into the nanocrystals would be more energy-efficient, but since the Fermi level in the gate electrode is reduced to the level of the valence band, the Fowler Nordheim tunnel current of electrons from the gate electrode into the nanocrystals is negligible. By applying a negative voltage to the gate electrode, the information stored in the nanocrystals in the form of electrons is therefore deleted by tunneling holes from the channel region through the first dielectric layer into the nanocrystals. A voltage level of approximately ± 3.5 V to 5.5 V is required to write or delete information. The voltage level required for writing or erasing is therefore only 1 to 3 V higher than for the memory cell known from Tiwari. The times required for the erase process are typically 1 ms in the memory cell according to the invention. The times required for the write process are typically 1 μs.

Since the probability of direct tunneling through the first dielectric layer and the second dielectric layer is negligible in this memory cell, is the time for data retention in the memory cell, for example for a thickness of the first dielectric layer, which acts as a tunnel oxide, of 5 nm is more than a thousand years.

As is generally customary, the memory cell is integrated in memory cell arrangements which have a plurality of identical memory cells in the form of a matrix.

The nanocrystals preferably contain silicon and / or germanium. They have an average diameter of 2 to 10 nm and distances of 2 to 10 nm.

Since the memory cell has no floating gate electrode, its radiation hardness is greater than for the comparable FLOTOX cell. The MOS transistor in the memory cell can be designed both as a planar and as a vertical MOS transistor.

The invention is explained in more detail below with the aid of the exemplary embodiments and the figures.

Figure 1 shows a memory cell with a planar MOS transistor.

Figure 2 shows a memory cell with a vertical MOS transistor.

A source region 2 and a drain region 3, which are n-doped, for example, are provided in a substrate 1, which comprises monocrystalline silicon at least in the region of a memory cell (see FIG. 1). A channel region 4 is arranged between the source region 2 and the drain region 3. Arranged above the channel region 4 is a gate dielectric 5, which comprises a first SiO 2 layer 51, nanocrystals 52 and a second SiO 2 layer 53. The first SiO 2 layer 51 is arranged on the surface of the channel region 4 and has a thickness of 2 to 5 nm, preferably 4 nm The nanocrystals 52 are arranged on the surface of the first SiO 2 layer 51. They contain silicon and have a diameter of 5 nm and an average distance of 5 nm. For the sake of clarity, the nanocrystals 52 are shown in FIG. 1 as a continuous layer. The second SiO 2 layer 53 is arranged on the surface of the nanocrystals 52, the thickness of which is 0.5 to 2 nm greater than the thickness of the first SiO 2 layer 51, that is to say in the range between 2.5 and 7 nm, preferably at 4.5 to 5 nm.

A gate electrode 6 made of p ⁺ -doped polysilicon is arranged on the surface of the gate dielectric 5. The gate electrode 6 has a thickness of, for example, 200 nm and a dopant concentration of, for example, 5 x 10 ²⁰ cm ^"3 .

A semiconductor layer structure 11 made of, for example, monocrystalline silicon comprises a source region 12, a channel region 14 and a drain region 13 in vertical succession (see FIG. 2). The source region 12 and the drain region 13 are, for example, n-doped with a dopant concentration of 10 ²¹ cm ^-3 . The channel region 14 is, for example, p-doped with a dopant concentration of 10 ¹⁷ cm ^"3. The source region 12, the drain region 13 and the channel region 14 have a common flank 110, which preferably runs perpendicularly or slightly inclined to the surface of the semiconductor layer structure 11. The flank 110 can be both the flank of a trench or a step in a substrate and the flank of a raised structure, for example a mesa structure.

A dielectric triple structure 15 is arranged on the flank 110, which comprises a first SiO 2 layer 151, nanocrystals 152 and a second SiO ₂ layer 153. The surface of the second SiO 2 layer 153 is covered with a gate electrode 16. The gate electrode 16 is, for example, in the form of a spacer made of p ⁺ -doped polysilicon with a doping Concentration of 5 x 10 ²⁰ cm ^-3 formed. The first SiO 2 layer 151 has a thickness of, for example, 2 to 5 nm, preferably 4 nm. The second SiO ₂ layer 153 is 0.5 to 2 nm thicker than the first SiO ₂ layer 151, that is, it has a thickness between 2.5 and 7 nm. It preferably has a thickness of 4.5 nm. The thicknesses of the first SiO ₂ layer 151 and the second SiO 2 layer 153 are each measured perpendicular to the flank 110.

The nanocrystals 152 contain silicon and have a diameter of 5 nm and an average distance of 5 nm. For the sake of clarity, the nanocrystals 152 are shown in FIG. 2 as a continuous layer. For example, they are produced by CVD deposition.

Claims

claims

1. Non-volatile memory cell

- With a MOS transistor, which has a first dielectric layer (51) and a second dielectric layer (53) as gate dielectric (5), wherein between the first dielectric layer (51) and the second dielectric layer (53) nanocrystals (52 ) are arranged,

- The MOS transistor has a gate electrode (6) which contains p ⁺ -doped silicon.

2. The memory cell of claim 1, wherein the first dielectric layer (51) and the second dielectric layer (53) are each at least 2 nm thick.

3. Memory cell according to claim 1 or 2, wherein the first dielectric layer (51) and the second dielectric layer (53) each contain SiÜ2.

4. Memory cell according to one of claims 1 to 3,

- The difference in the thicknesses of the first dielectric layer (51) and the second dielectric layer (53) in

Range between 0.5 nm and 2 nm,

- In which the smaller of the thicknesses of the first dielectric layer (51) and the second dielectric layer (53) is in the range between 2 nm and 5 nm.

5. Memory cell according to one of claims 1 to 4, in which the p ⁺ -doped silicon in the gate electrode (6) has a dopant concentration of at least 1 x 10 ²⁰ cm ^"3 .

6. Memory cell according to one of claims 1 to 5, in which the nanocrystals (52) have silicon.

7. Memory cell according to claim 6, wherein the nanocrystals (52) have a diameter between 2 and 10 nm.