WO1999005605A1

WO1999005605A1 - A device and a process for the locating of an interrupt request allocated to a source

Info

Publication number: WO1999005605A1
Application number: PCT/EP1998/004555
Authority: WO
Inventors: Bernd Moser
Original assignee: Nokia Networks Oy
Priority date: 1997-07-23
Filing date: 1998-07-21
Publication date: 1999-02-04
Also published as: AU8732098A; DE19731634A1

Abstract

The invention concerns a device and a process for the locating of an interrupt request (interrupt) allocated to a source from a multitude of possible sources, several of which in each case are combined into a group, with a software (SW) for locating the wanted interrupt within a group and for the subsequent execution of a routine provided for the source allocated to the wanted interrupt in the case of an interrupt and with a hardware facility (HW) having an identification facility (A) which, in the case of an interrupt request provides the software (SW) with an address vector identifying the group. In order to enable a preferential reaction to interrupt requests of high priority and simultaneously ensure rapid reaction to an interrupt request, the sources of interrupt requests are combined into groups in the hardware device by means of interrupt group registers, one of at least two different priorities are allocated to each group and the hardware facility (HW) is provided with a separate identification facility (A) for each priority provided.

Description

A DEVICE AND A PROCESS FOR THE LOCATING OF AN INTERRUPT REQUEST ALLOCATED TO A SOURCE

A device for the locating of an interrupt request allocated to a source from a multitude of possible sources several of which are combined into a group in each case, with a software (SW) for locating the wanted interrupt within its group and for the subsequent execution of a routine provided for the source allocated to the wanted interrupt in the case of an interrupt and with a hardware facility having an identification facility which in turn includes a multiplexer, the input signals of which are formed by the output signals of the groups, for sequential scanning of the output signals with a certain clock frequency, and a counter, the one input (disable) of which is connected with the output of the multiplexer, for changing an address vector with the clock frequency, for stopping the changing of the address vector upon input of a stop signal by the output value of the multiplexer, for making available the address vector for the software, where the address vector serves as allocation vector for the software for locating the group containing the interrupt request, and for controlling the multiplexer (Ml) with the current address vector.

The invention likewise concerns a process for the locating of an interrupt request allocated to a source.

Events in the hardware requiring rapid reaction of the software are generally reported to the software by means of interrupt requests. As a consequence the software interrupts its normal process in order to be able to execute the process routines corresponding to a certain source of an interrupt process. However, in order to do so the software will first have to locate the source of the interrupt request. With growing complexity of the hardware, more and more possible sources of interrupt requests are contained in a hardware facility and more and more independent hardware facilities are arranged in a system or on a board. Frequently these facilities are supplied by a single processor with limited capacity and a limited number of lines for the interrupt requests. For this reason a simple device for locating the origin of an interrupt request must be provided.

Devices and processes for locating the source of an interrupt request in hardware facilities are known in practice. Such devices provide that several possible sources of an interrupt request are combined in a hardware facility in groups, wherein usually that number of possible sources is combined in each case which can be checked by the software by a single access operation. In this way it is possible for instance to check eight possible sources with a 1-byte read access operation. If a large number of these groups is still present after this combination, additional hierarchy levels are formed at each of which several groups are combined into new groups (Figure 1) . As a rule, the groups are combined until the software is able by single access to access all groups of the uppermost hierarchy level. Accordingly, the more possible sources exist for interrupt requests, the more hierarchy levels are required. When reporting an interrupt request the software must trace the path of the request through all hierarchy levels in order to be able to locate the source of the interrupt request. This means that an additional hardware access operation is required for each additional hierarchy level and the passing of an evaluation process in the software for determining the next group in the subordinate level which needs to be read.

A disadvantage of this device consists in that in a hardware facility with a large number of possible sources of interrupt requests the time for locating a requesting source grows very long since the time required to locate the interrupt request of a source depends on the number of hierarchy levels which the software has to pass through each time. If furthermore some of the interrupt requests appear frequently, this may slow down the software to an unacceptable degree.

A possibility for a more rapid locating of sources of interrupt requests is explained in the European patent application EP 0 509 746 A2. According to this publication a number of interrupt sources is combined into a group each of which issues a joint interrupt request. The output of the different groups is scanned in that a selector sequentially reads the outputs wherein a counter counts up one value for each scanned group if the respective group does not issue an interrupt request. The values passed by the counter in this process correspond to the number of groups so that the current value always unambiguously identifies the current group. In the case of an interrupt request the counter writes the current value on a bus from which a CPU reads the value if it has been informed of the interrupt request by the selector. With such a device a rapid reaction to an interrupt request is possible since through the use of the counter the group triggering the interrupt request, even with a large number of possible interrupt requests, is directly known from the current status of the counter. The reaction to an interrupt request however possesses different grades of importance to the system depending on the triggering source. In the case that several interrupt requests are present at the same time, preferably the request most important to the system, i.e. the request with the highest priority, should be processed first. Such a possibility for the processing of interrupt requests in the sequence of their priorities is not provided for in EP 0 509 746 A2. Consequently the task of the invention is to create a device or a process which ensures a preferential reaction to interrupt requests with higher priority while simultaneously maintaining the speed of the reaction to an interrupt request.

On the one hand this task in a device according to the general definition of claim 1 is solved in that the sources of interrupt requests are combined in groups in the hardware device by means of interrupt group registers, that one of at least two different priorities are allocated to each group, and that the hardware installation contains a separate identification facility for each provided priority.

On the other hand the task is solved by a process for locating an interrupt request allocated to a source from a multitude of possible sources with a hardware facility containing interrupt group registers for interrupt requests in which several sources are combined into a group at a time and with a software for locating the wanted interrupt request within its group and for subsequent execution of a routine provided for the source allocated to the wanted interrupt request in the case of an interrupt request in that

at least two different priorities are allocated to the individual groups, one identification facility is allocated to each of the groups of a priority, a multiplexer contained in each identification facility, the input signals of which are formed by the output signals of the groups allocated to the identification facility, which sequentially scans the output signals with a certain clock frequency, a counter contained in each identification facility the one input (disable) of which is connected with the output of the multiplexer, changes an address vector with the clock frequency where the address vector forms an allocation vector for the group just scanned, the change of the address vector upon input of a stop signal is stopped by the output value of the multiplexer indicating an interrupt request, the counter provides the multiplexer with the current address vector for controlling the multiplexer, the counter provides the software with the address vector in the case of an interrupt request wherein with simultaneous presence of interrupt requests from identification facilities of different priorities the address vector from the identification facilities of the highest priority is passed on to the software, and the software identifies the group which has issues an interrupt request by means of the address vector. The advantage of the solution according to the invention consists in that the identification facilities are able to conduct a continuous check of the individual groups at high speed and that with the information of the identification facilities the software is already able to clearly identify the group issuing the interrupt request and consequently able to locate an interrupt request generally after two hardware access operations (reading of the address vector and checking the interrupt group registers in the group concerned) . With the hardware having a large number of possible sources of an interrupt request the device according to the invention and the process according to the invention require a limited processor capacity and permit a very rapid reaction to interrupt requests.

Furthermore, with the solution according to the invention the priority of the group with the triggering source is directly known by the allocation of one of at least two different priorities to each of the individual groups and by the provision of a separate identification facility for each priority. In this way a preferential reaction to the interrupt request with the highest priority is possible if several interrupt requests are present simultaneously.

In a preferential embodiment of the invention a notification unit is provided in addition to the identification facility which is linked with all groups and the output of which issues a logic information to the software if an interrupt request is present in at least one group such that when the logic information is placed the current value of the address vector of the identification facility can be taken over by the software. Further preferential embodiments of the invention are explained in the subordinate claims.

In the following, the invention is explained in more detail by means of the drawings containing the embodiment examples. There it shows:

Figure 1 A grouping in hierarchy levels for a device according to the state of the art, Figure 2 a first embodiment example according to the invention, Figure 3 a second embodiment example according to the invention, Figure 4 a third embodiment example according to the invention, and Figure 5 a fourth embodiment example according to the invention with different priorities.

Figure 2 clearly shows the principle of the device according to the invention. All statuses of interrupt requests placed in an interrupt group register are linked through an OR gate (ORl-ORX) . The outputs of the OR gates (ORl-ORX) are connected with an identification facility (A) which is connected with the software (SW) through an output. If the number of interrupt sources combined into a group for instance amounts to up to eight, access to all interrupt sources of a group is possible with a 1- byte read access operation.

In the instance of an interrupt request the value of the interrupt allocated to the requesting source is placed from 0" to "1". After linking the outputs of an interrupt group register through the OR gate (ORl-ORX) a "1" is likewise issued at the output of the OR gate belonging to the interrupt requesting an interrupt. The identification facility (A) checks sequentially and continuously the outputs of the OR gates (ORl-ORX) to see if an interrupt is requested by one of the groups (for instance with the clock frequency of the micro processor) . As long as this is not the case, it allocates an unambiguous address vector to each of the scanned groups and continues with the next group. However, if an interrupt request occurs, the current address vector for the software is provided for readout. The query mechanism can be interrupted during this process.

The software then reads out the address vector with which it is able to clearly identify the group concerned and searches for the interrupt concerned within this group. The interrupt source requesting an interrupt can therefore be located by the software with only two hardware access operations. Provided the query mechanism has been interrupted, the hardware (HW) automatically continues checking the groups after the software (SW) has read out the address vector, while the software processes the interrupt.

Figure 3 shows a further embodiment example of the invention corresponding to the example in Figure 2, however additionally containing a notification block (B) . Again, all statuses for interrupt requests placed in an interrupt group register are linked through an OR gate (ORl-ORX) . The outputs of the OR gate (ORl-ORX) on the one hand are connected with the notification device (B) which in turn is connected with the software (SW) . On the other hand the outputs of the OR gate (ORl-ORX) are connected with the identification facility (A) which is also connected with the software (SW) . In the instance of an interrupt request the value of the interrupt allocated to the requesting source is placed from "0" to "1". After linking the outputs of an interrupt group register through the OR gate (ORl-ORX) a "1" is likewise issued at the output of the OR gate belonging to the interrupt requesting an interrupt.

The identification facility (A) sequentially and continuously checks the outputs of the OR gates (ORl-ORX) to see if one of the groups is requesting an interrupt (for instance with the clock frequency of the micro processor) . As long as this is not the case it allocates an unambiguous address vector to the respective group being queried and proceeds with the next group. However, if an interrupt request occurs, the current address vector readout is provided for the software.

If a l" for an interrupt request is present at the output of one of the OR gates (ORl-ORX) the notification block (B) of the software (SW) reports that an interrupt request is present and an address vector must be read out from the identification facility (A) .

The software then reads out the address vector with which it is able to clearly identify the group concerned and searches for the interrupt concerned within this group. The interrupt source requesting an interrupt can consequently be located by the software with only two hardware access operations.

Figure 4 shows a further preferential embodiment of the invention. All statuses for interrupt requests placed in an interrupt group register are linked through an OR gate (ORl-ORX) . The outputs of all X OR gates (ORl-ORX) on the one hand are linked with a further OR gate (Gl) . The output of this OR gate (Gl) is connected with a flipflop (F) through an input of an AND gate (G2) the output of which provides a connection to the (not shown) software and which is clocked for instance at the clock frequency of the microprocessor (up elk) .

On the other hand, the X outputs of the OR gates (ORl- ORX) are connected with the X inputs of a multiplexer (Ml) . The output signal of the multiplexer (Ml) on the one hand provides one of the input signals of a further OR gate (G3) the output of which provides the second input for the AND gate (G2) . On the other hand the output signal of the multiplexer (Ml) provides an input signal of a counter (Z) which for example is also clocked with the clock frequency of the microprocessor (up elk) . The output of the counter (Z) is also connected with the software through a further multiplexer (M2) . An "idle" value is present at the second input of the multiplexer (M2) . This "idle" value should be a value which cannot be otherwise issued, for instance the maximum counter value or another value above the reset value of the counter. The output signal of the first multiplexer (Ml) additionally supplies a control signal to the second multiplexer (M2) . The counter (Z) possesses a further input which is directly connected with the software. The output signal of the counter (Z) additionally supplies a control vector for the first multiplexer (Ml) .

The second input signal for the OR gate (G3) is provided by the output signal of the flipflop (F) .

In the following is described the operation of the embodiment of the invention according to Figure 4: We first examine a situation without hardware interrupt request. This means that a "0" to the OR gates (ORl-ORX) is issued by all outputs of the interrupt group register. Consequently the outputs of all OR gates (ORl-ORX) are also "0". Linking the outputs of the OR gates (ORl-ORX) with the OR gate (Gl) results in a further "0" signal which is issued to the software through the AND gate and the flipflop. Here a signal from "0" to the software means that no interrupt request is present and the software can continue working as normal.

The output signals "0" of the OR gates (ORl-ORX) additionally are present at the outputs of the multiplexer (Ml) . The latter multiplexes the signals in one after the other and passes the "0" on to the OR gate (G3) and to the counter (Z) . As long as the counter receives a "0" it adds one to the counter reading from zero to X with each clocking (up elk) . As soon as the "X" value has been reached a reset is conducted and the counter starts from 0 again. In this way each check of a group provides a clear counter reading. The current counter value is passed onto the second multiplexer (M2) . However, since the second multiplexer (M2) receives a control signal of "0" from the first multiplexer (Ml), not the counter value but the "idle" value available at the second input of the multiplexer (M2) is provided for the software. The output value of the counter additionally informs the first multiplexer (Ml) as to which input signal should be allowed to pass next.

The output signal of the OR gate (G3) is "0" since both input signals - the output signal of the first multiplexer (Ml) and the output signal of the flipflop (F) - supply a "0". The input signal for the flipflop (F) consequently is also "0", since a "0" is present at both inputs of the 7AND gate (G2) which, as output signal, provides the input signal of the flipflop.

Next is described a situation in which at least one interrupt request is present. Consequently a "1" is issued at the output of at least one of the OR gates (ORl-ORX) . As a result the output of the OR gate (Gl) with which the OR gates (ORl-ORX) are being linked, also supplies a "1" to the one input of the AND gate.

The multiplexer (Ml) continues to consecutively pass on to the counter (Z) the values supplied by the OR gates (ORl-ORX) , wherein the output of the counter (Z) supplies a control signal to the multiplexer (Ml) as to which group signal will be passed on next. With each clocking the counter adds 1 to the counter value as long as a "0" is received at the "disable" input. However, if it receives a "1" as one of the group signals passed on by the multiplexer (Ml), the multiplexer (Ml) has located the requesting group and the counter (Z) stops until it is given an add-on impulse for counting up (+1) from the software. The stopped value is passed on to an input of the second multiplexer (M2) which is additionally given a signal from the first multiplexer not to keep issuing the "idle" value any longer but the counted value which is now available to the software as read-out address vector.

At the same time the output of the first multiplexer (Ml) applies a "1" to the OR gate (G3) . Since the output of the OR gate (G3) is present at the second input of the AND gate (G2) and a "1" from the OR gate (Gl) is already present at the first input of the AND gate (G2) as notification that an interrupt has indeed been requested, the flipflop (F) receives a "1" as input signal. The flipflop (F) passes the "1" on to the software which in this way is informed that at the output of the second multiplexer (M2) an address vector is ready for readout which identifies the group issuing the interrupt request. After reading out the address vector the software enables the counter (Z) to continue counting and searches the group concerned for the exact origin of the interrupt request in order to be able to execute the corresponding processing routine.

If several interrupt requests are present, the software, after having located the first group requesting an interrupt, receives a continuous message about an interrupt request in order to avoid a continuous jumping between the actual routines of the software and the interrupt routines. This is achieved in that the output of the flipflop (F) is fed back through the OR gate (G3) so that the output of the OR gate (G3) is either "1" if the origin of an interrupt request was located by the query device or it concerns an interrupt request which was already present before the previous one could be executed. In very rare cases it can occur with a large number of possible sources of interrupts that the software has executed the preceding interrupt request before the hardware has located the next requesting group so that at the output of the multiplexer (M2) the new address vector is not yet available. However, the software already reads out the output of the multiplexer (M2) since it has been requested by the signal of the flipflop (F) to do so. For this reason an "idle" value is available at an input of the multiplexer (M2) which, controlled by the output of the first multiplexer (Ml) is issued by the second multiplexer (M2) as long as no group with interrupt request has been recognised. The software clearly identifies the "idle" value as such and consequently conducts a further reading attempt. On the other hand, if no further interrupt requests are present after the software has read out an address vector, the counter can stop once more at the same group if the software has not yet completely executed the interrupt. The signal of an interrupt request to the software is maintained until the software has executed all queuing interrupts.

The maximum period of time within which the counter has located the next queuing interrupt depends on the number of interrupt group registers:

max. time = number_ interrupt_ group_register_ sources * clock time

Figure 5 finally shows a further preferred embodiment of the invention in which two different priorities (high/low) are assigned to the possible sources of an interrupt request.

From (not shown) OR links of the outputs of an interrupt group register, connections, depending on the priority allocation of the groups, lead to a first query facility (Al) or to a second query facility (A2) each containing the characteristics according to figures 2 or 3. In this example the first 20 groups have been assigned a high priority and the additional 63 groups a low priority. However, this example can be expanded to any number of priority stages in each with any number of groups.

A first output of each of the two query facilities (A1/A2) is connected with the (not shown) software through an OR gate (G4) . A second output of each of the two query facilities (A1/A2) is connected with the software through a multiplexer (M3) . The multiplexer (M3) is additionally given a control signal from the first output of the query facility for the high priority (Al) . This output signal additionally places a bit of the output value of the multiplexer (M3 : [6]), which, itself, in this example places only 6-bit ([0:5]) which it receives as address vector from the query facilities. In addition, an additional connection is provided from the software to each of the two query facilities. The first of each of the two output signals of the two query facilities (A1/A2) is issued as interrupt request to the software linked through an OR gate (G4) .

The second output signals which are applied to the inputs of the multiplexer (M3) , are given the address vector of a group requesting an interrupt or "idle" values. The first output of the query facility with a high priority (Al) additionally provides a control signal to the multiplexer (M3) which ensures that with simultaneous input of an address vector from both query facilities (A1/A2) the address vector from the query facility with the high priority (Al) is issued first. As information to the software as to which query facility is the source of the address vector provided, the first output signal of the query facility with the high priority (Al) places a dedicated bit ([6]) of the word issued by the multiplexer on "0" or "1". The resulting word can then be read out and processed by the software.

After reading out the address vector provided by the multiplexer (M3) the software re-activates the counter of the corresponding query facility (Al or A2) through the input of the corresponding query facility.

Claims

A device for the locating of an interrupt request allocated to a source from a multitude of possible sources several of which are combined into a group in each case, with a software (SW) for locating the wanted interrupt within its group and for the subsequent execution of a routine provided for the source allocated to the wanted interrupt in the case of an interrupt and with a hardware facility (HW) having an identification facility (A) which in turn includes a multiplexer (Ml) the input signals of which are formed by the output signals of the groups for sequential scanning of the output signals with a certain clock frequency, and a counter (Z) the one input (disable) of which is connected with the output of the multiplexer (Ml) , for changing an address vector with the clock frequency, for stopping the changing of the address vector upon input of a stop signal by the output value of the multiplexer (Ml) , for making available the address vector to the software (SW) , wherein the address vector serves as allocation vector for the software for locating the group containing the interrupt request, and for controlling the multiplexer (Ml) with the current address vector, characterised in that the sources of interrupt requests are combined into groups in the interrupt group register so that each group is allocated one of at least two different priorities and that the hardware facility (HW) contains a separate identification facility (A) for each provided priority.

A device according to claim 1, characterised in that the hardware facility (HW) contains a notification device (B) linked with all groups allocated to this priority for each priority, the output of which issues a logic information (1/0) to the software (SW) if an interrupt request is present at least in one group of this priority so that when the logic information is placed the address vector of the identification facility (A) can be accepted by the software.

A device according to one of the preceding claims, characterised by an OR gate (G4) the inputs of which form the outputs of all notification facilities (B) and the output of which is connected with the software (SW) for notification by means of an interrupt request.

A device according to one of the preceding claims characterised by a multiplexer (M3) the inputs of which are connected with the outputs of the identification facilities (A) wherein the multiplexer (M3) is controlled by the outputs of the notification devices (B) for issuing an address vector of the highest priority to the software (SW) .

A device according to one of the preceding claims, characterised in that the address vector of the found interrupt request of a group can be passed on to the software without interrupt of the query mechanism.

A device according to one of the preceding claims, characterised in that in each identification facility (A) allocated to a certain priority the counter (Z) counts up the value of the address vector by one with each cycle as long as no interrupt request has been detected, and is reset to "zero" when the address vector has reached the value "X", where X corresponds to the number of groups.

A device according to claim 6, characterised in that a connection between the software (SW) and the counter of each identification facility (A) allocated to a certain priority exists for transferring a signal from the software (SW) to the counter (Z) following which after acceptance of the value by the software (SW) the respective counter (Z) is raised by one and continued querying of the groups of the respective priorities is reactivated.

A device according to one of the preceding claims, characterised in that each identification facility (A) allocated to a certain priority incorporates a further multiplexer (M2) at the input of which an "idle" value is present and on the other input of which the address vector issued by the counter (Z) is present for issuing the value selected according to the output of the multiplexer (Ml) to the software (SW) .

A device according to one of the claims 2-8, characterised in that each of the groups of notification devices (B) allocated to a certain priority incorporates a flipflop (F) for passing on an interrupt request from the groups, the output signals of which are linked through an OR gate (Gl), to the software (SW) and an AND gate (G2) at the first input of which the output signal of the OR gate (G3) is present and at the second input of which the output signal of the multiplexer (Ml) is present for issuing an interrupt request to the flipflop (F) if both an interrupt from the entirety of the group has been reported and the specific group issuing the report has already been detected by the multiplexer (Ml) .

10. A device according to claim 9, characterised in that each of the groups of a notification device (B) allocated to a certain priority incorporates a further OR gate (G4) at the first input of which the output signal of the multiplexer (Ml) is present, at the second input of which the output signal of the flipflop (F) is present and the output signal of which supplies the second input signal of the AND gate (G3) .

11. A process for locating an interrupt request allocated to a source from a multitude of possible sources with a hardware facility (HW) containing interrupt group registers for interrupt requests within each of which several sources are combined into a group, and with a software (SW) for locating the wanted interrupt within its group and for subsequent execution of a routing provided for the source allocated to the wanted interrupt in the case of an interrupt, characterised in that at least two different priorities are allocated to the individual groups, an identification facility (A) is allocated to each of the groups of a priority, a multiplexer (Ml) contained in each identification facility (A) , the input signals of which are formed by the output signals of the groups allocated to the identification facility (A) , sequentially scans the output signals with a certain clock frequency, a counter (Z) contained in each identification facility (A) , the one input (disable) of which is connected with the output of the multiplexer (Ml), changes an address vector with the clock frequency wherein the address vector forms an allocation vector for the group just scanned, the changing of the address vector upon input of a stop signal is stopped by an output value of the multiplexer (Ml) indicating an interrupt request, the counter (Z) provides the multiplexer (Ml) with the current address vector for controlling the multiplexer (Ml), the counter (Z) provides the software (SW) with the address vector in the case of an interrupt request whereas with simultaneous presence of interrupt requests from identification facilities (A) of different priorities the address vector from the identification facilities (A) for the highest priority is passed on to the software and the software (SW) by means of the address vector identifies the group which has issued the interrupt request.

12. A process according to claim 11, characterised in that each of the groups of a priority have allocated to them a separate notification facility (B) included in the hardware facility (HW) , the notification device (B) linked with all groups of a priority issues a logic information (1/0) to the software (SW) if an interrupt request is present in at least one group of a certain priority and on placing the logic information the software (SW) takes over the address vector from the identification facility (A) allocated to the same priority.