WO1999009599A3 - Vertical interconnect process for silicon segments with dielectric isolation - Google Patents

Vertical interconnect process for silicon segments with dielectric isolation Download PDF

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Publication number
WO1999009599A3
WO1999009599A3 PCT/US1998/016900 US9816900W WO9909599A3 WO 1999009599 A3 WO1999009599 A3 WO 1999009599A3 US 9816900 W US9816900 W US 9816900W WO 9909599 A3 WO9909599 A3 WO 9909599A3
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WO
WIPO (PCT)
Prior art keywords
segments
segment
die
stack
interconnected
Prior art date
Application number
PCT/US1998/016900
Other languages
French (fr)
Other versions
WO1999009599A2 (en
Inventor
Alfons Vindasius
Kenneth M Sautter
Original Assignee
Cubic Memory Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US08/915,620 external-priority patent/US6255726B1/en
Priority claimed from US08/920,273 external-priority patent/US6080596A/en
Application filed by Cubic Memory Inc filed Critical Cubic Memory Inc
Priority to AU91976/98A priority Critical patent/AU9197698A/en
Priority to KR1020007001498A priority patent/KR100593567B1/en
Priority to JP2000510170A priority patent/JP2001516148A/en
Priority to EP98944438A priority patent/EP1029360A4/en
Publication of WO1999009599A2 publication Critical patent/WO1999009599A2/en
Publication of WO1999009599A3 publication Critical patent/WO1999009599A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L24/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L24/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18—High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24—Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/241—Disposition
    • H01L2224/24135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
    • H01L2224/24145—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28—Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29—Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001—Core members of the layer connector
    • H01L2224/29099—Material
    • H01L2224/2919—Material with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06524—Electrical connections formed on device or on substrate, e.g. a deposited or grown layer
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    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06551—Conductive connections on the side of the device
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    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/04—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers
    • H01L2225/065—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L2225/06503—Stacked arrangements of devices
    • H01L2225/06593—Mounting aids permanently on device; arrangements for alignment
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    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01033—Arsenic [As]
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/01—Chemical elements
    • H01L2924/01074—Tungsten [W]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
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    • H01L2924/01075—Rhenium [Re]
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    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits

Abstract

An apparatus vertically interconnects stacks of silicon segments (36). Each segment (36) includes a plurality of adjacent die on a semiconductor wafer (30). The plurality of die on a segment are interconnected on the segment using one or more layers of metal interconnects which extend to all four sides of the segment to provide edge bonding pads (42) for external electrical connection points. After the die are interconnected, each segment is cut from the backside of the wafer using a bevel cut to provide four inwardly sloping edge walls (102) on each of the segments (36). After the segments are cut from the wafer, the segments are placed on top of one another to form a stack. Vertically adjacent segments in the stack are electrically interconnected by applying electrically conductive epoxy to one or more sides of the stack. The inwardly sloping edge walls of each of the segments in the stack provide a recess which allows the electrically conductive epoxy to access the edge bonding pads and lateral circuits on each of the segments once the segments are stacked. A dielectric coating is applied to the die to provide a conformal coating to protect and insulate the die and a laser is used to ablate the area over the bond pads to remove the dielectric coating in order to provide for electrical connections to bond pads.
PCT/US1998/016900 1997-08-21 1998-08-14 Vertical interconnect process for silicon segments with dielectric isolation WO1999009599A2 (en)

Priority Applications (4)

Application Number Priority Date Filing Date Title
AU91976/98A AU9197698A (en) 1997-08-21 1998-08-14 Vertical interconnect process for silicon segments with dielectric isolation
KR1020007001498A KR100593567B1 (en) 1997-08-21 1998-08-14 Vertical Interconnect Process for Silicon Segments with Dielectric Insulation
JP2000510170A JP2001516148A (en) 1997-08-21 1998-08-14 Method for vertically interconnecting silicon segments with dielectric insulation
EP98944438A EP1029360A4 (en) 1997-08-21 1998-08-14 Vertical interconnect process for silicon segments with dielectric isolation

Applications Claiming Priority (4)

Application Number Priority Date Filing Date Title
US08/915,620 1997-08-21
US08/915,620 US6255726B1 (en) 1994-06-23 1997-08-21 Vertical interconnect process for silicon segments with dielectric isolation
US08/920,273 US6080596A (en) 1994-06-23 1997-08-22 Method for forming vertical interconnect process for silicon segments with dielectric isolation
US08/920,273 1997-08-22

Publications (2)

Publication Number Publication Date
WO1999009599A2 WO1999009599A2 (en) 1999-02-25
WO1999009599A3 true WO1999009599A3 (en) 1999-04-15

Family

ID=27129674

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Application Number Title Priority Date Filing Date
PCT/US1998/016900 WO1999009599A2 (en) 1997-08-21 1998-08-14 Vertical interconnect process for silicon segments with dielectric isolation

Country Status (5)

Country Link
EP (1) EP1029360A4 (en)
JP (1) JP2001516148A (en)
KR (1) KR100593567B1 (en)
AU (1) AU9197698A (en)
WO (1) WO1999009599A2 (en)

Families Citing this family (20)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
AU9105298A (en) * 1997-08-22 1999-03-16 Cubic Memory, Inc. Vertical interconnect process for silicon segments with thermally conductive epoxy preform
US7215018B2 (en) 2004-04-13 2007-05-08 Vertical Circuits, Inc. Stacked die BGA or LGA component assembly
US7705432B2 (en) * 2004-04-13 2010-04-27 Vertical Circuits, Inc. Three dimensional six surface conformal die coating
US7245021B2 (en) 2004-04-13 2007-07-17 Vertical Circuits, Inc. Micropede stacked die component assembly
US8723332B2 (en) 2007-06-11 2014-05-13 Invensas Corporation Electrically interconnected stacked die assemblies
WO2009035849A2 (en) 2007-09-10 2009-03-19 Vertical Circuits, Inc. Semiconductor die mount by conformal die coating
KR101554761B1 (en) 2008-03-12 2015-09-21 인벤사스 코포레이션 Support mounted electrically interconnected die assembly
US9153517B2 (en) 2008-05-20 2015-10-06 Invensas Corporation Electrical connector between die pad and z-interconnect for stacked die assemblies
US7863159B2 (en) 2008-06-19 2011-01-04 Vertical Circuits, Inc. Semiconductor die separation method
WO2010151578A2 (en) 2009-06-26 2010-12-29 Vertical Circuits, Inc. Electrical interconnect for die stacked in zig-zag configuration
US9147583B2 (en) 2009-10-27 2015-09-29 Invensas Corporation Selective die electrical insulation by additive process
TWI544604B (en) 2009-11-04 2016-08-01 英維瑟斯公司 Stacked die assembly having reduced stress electrical interconnects
KR101887084B1 (en) 2011-09-22 2018-08-10 삼성전자주식회사 Multi-chip semiconductor package and method of forming the same
US9490195B1 (en) 2015-07-17 2016-11-08 Invensas Corporation Wafer-level flipped die stacks with leadframes or metal foil interconnects
US9825002B2 (en) 2015-07-17 2017-11-21 Invensas Corporation Flipped die stack
US9871019B2 (en) 2015-07-17 2018-01-16 Invensas Corporation Flipped die stack assemblies with leadframe interconnects
US9508691B1 (en) 2015-12-16 2016-11-29 Invensas Corporation Flipped die stacks with multiple rows of leadframe interconnects
US10566310B2 (en) 2016-04-11 2020-02-18 Invensas Corporation Microelectronic packages having stacked die and wire bond interconnects
US9595511B1 (en) 2016-05-12 2017-03-14 Invensas Corporation Microelectronic packages and assemblies with improved flyby signaling operation
US9728524B1 (en) 2016-06-30 2017-08-08 Invensas Corporation Enhanced density assembly having microelectronic packages mounted at substantial angle to board

Citations (2)

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US4835593A (en) * 1986-05-07 1989-05-30 International Business Machines Corporation Multilayer thin film metallurgy for pin brazing
US5445994A (en) * 1994-04-11 1995-08-29 Micron Technology, Inc. Method for forming custom planar metal bonding pad connectors for semiconductor dice

Family Cites Families (4)

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Publication number Priority date Publication date Assignee Title
US4877752A (en) * 1988-10-31 1989-10-31 The United States Of America As Represented By The Secretary Of The Army 3-D packaging of focal plane assemblies
US5675180A (en) * 1994-06-23 1997-10-07 Cubic Memory, Inc. Vertical interconnect process for silicon segments
US5657206A (en) * 1994-06-23 1997-08-12 Cubic Memory, Inc. Conductive epoxy flip-chip package and method
US5653019A (en) * 1995-08-31 1997-08-05 Regents Of The University Of California Repairable chip bonding/interconnect process

Patent Citations (2)

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Publication number Priority date Publication date Assignee Title
US4835593A (en) * 1986-05-07 1989-05-30 International Business Machines Corporation Multilayer thin film metallurgy for pin brazing
US5445994A (en) * 1994-04-11 1995-08-29 Micron Technology, Inc. Method for forming custom planar metal bonding pad connectors for semiconductor dice

Non-Patent Citations (1)

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Title
See also references of EP1029360A4 *

Also Published As

Publication number Publication date
EP1029360A4 (en) 2006-04-12
WO1999009599A2 (en) 1999-02-25
KR100593567B1 (en) 2006-06-28
AU9197698A (en) 1999-03-08
EP1029360A2 (en) 2000-08-23
JP2001516148A (en) 2001-09-25
KR20010022894A (en) 2001-03-26

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