WO1999017372A1 - Heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction - Google Patents
Heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction Download PDFInfo
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- WO1999017372A1 WO1999017372A1 PCT/US1998/018686 US9818686W WO9917372A1 WO 1999017372 A1 WO1999017372 A1 WO 1999017372A1 US 9818686 W US9818686 W US 9818686W WO 9917372 A1 WO9917372 A1 WO 9917372A1
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- layer
- emitter
- bipolar transistor
- gaas
- silicon
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- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 claims abstract description 35
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims abstract description 29
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical group [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 claims abstract description 27
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 24
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 24
- 239000010703 silicon Substances 0.000 claims abstract description 24
- 229910005540 GaP Inorganic materials 0.000 claims abstract description 23
- 239000002674 ointment Substances 0.000 claims description 22
- 238000000034 method Methods 0.000 claims description 20
- 239000000758 substrate Substances 0.000 claims description 18
- 230000001747 exhibiting effect Effects 0.000 claims 1
- 239000004065 semiconductor Substances 0.000 abstract description 22
- 238000012545 processing Methods 0.000 description 22
- 239000000463 material Substances 0.000 description 21
- 230000008901 benefit Effects 0.000 description 12
- 230000007547 defect Effects 0.000 description 11
- 238000009792 diffusion process Methods 0.000 description 11
- 230000008569 process Effects 0.000 description 10
- 238000005530 etching Methods 0.000 description 7
- 238000002347 injection Methods 0.000 description 6
- 239000007924 injection Substances 0.000 description 6
- 238000001465 metallisation Methods 0.000 description 5
- 238000007796 conventional method Methods 0.000 description 4
- 238000002955 isolation Methods 0.000 description 4
- 238000002161 passivation Methods 0.000 description 4
- 150000001875 compounds Chemical group 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 229910052732 germanium Inorganic materials 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 238000000059 patterning Methods 0.000 description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 description 3
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 2
- 239000013078 crystal Substances 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000012986 modification Methods 0.000 description 2
- 230000004048 modification Effects 0.000 description 2
- 229910010271 silicon carbide Inorganic materials 0.000 description 2
- 235000012431 wafers Nutrition 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 230000001133 acceleration Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 239000002019 doping agent Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052733 gallium Inorganic materials 0.000 description 1
- BHEPBYXIRTUNPN-UHFFFAOYSA-N hydridophosphorus(.) (triplet) Chemical compound [PH] BHEPBYXIRTUNPN-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 235000012239 silicon dioxide Nutrition 0.000 description 1
- 239000000377 silicon dioxide Substances 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 238000010561 standard procedure Methods 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000001629 suppression Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66234—Bipolar junction transistors [BJT]
- H01L29/66242—Heterojunction transistors [HBT]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/26—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys
- H01L29/267—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, elements provided for in two or more of the groups H01L29/16, H01L29/18, H01L29/20, H01L29/22, H01L29/24, e.g. alloys in different semiconductor regions, e.g. heterojunctions
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/70—Bipolar devices
- H01L29/72—Transistor-type devices, i.e. able to continuously respond to applied control signals
- H01L29/73—Bipolar junction transistors
- H01L29/737—Hetero-junction transistors
- H01L29/7371—Vertical transistors
- H01L29/7378—Vertical transistors comprising lattice mismatched active layers, e.g. SiGe strained layer transistors
Definitions
- HBTs formed on silicon substrates.
- Heteroj unction bipolar transistors theoretically provide advantages over conventional homojunction bipolar transistors by providing a heteroj unction between a base and emitter of a transistor.
- a heteroj unction is formed between two dissimilar semiconductor materials.
- Silicon (Si) exhibits a bandgap of around 1.12 eV, but a Si homojunction has no bandgap discontinuity at the junction.
- a bandgap discontinuity can occur at a junction by using dissimilar semiconductor materials on opposing sides of the junction. From the perspective of an NPN transistor, discontinuity in the valence band restricts hole flow from the base to the emitter, thus improving emitter injection efficiency and current gain.
- base region resistivity may be lowered (which lowers the base resistance) and emitter region resistivity may be raised (which lowers base- emitter junction capacitance) to create fast transistors without significantly compromising other device parameters.
- Such fast transistors would be useful for high speed digital, microwave and other integrated circuit and discrete transistor applications.
- HBT performance often falls far short of the theoretical expectations.
- One conventional Si-based HBT reduces the bandgap of the base region by creating a base material having a narrower bandgap than Si.
- a small amount of germanium (Ge) is mixed with Si in the base (Si ⁇ _ x Ge x ), and the emitter is more purely Si.
- the amount of bandgap difference ( ⁇ Eg) for as much as 20% Ge content in the base is only about 0.15 eV. This small ⁇ Eg achieves only a small portion of the performance benefits that HBTs theoretically promise. Slight improvements in HBT performance have been achieved by using materials other than Si for the emitter of an HBT.
- SiC silicon carbide
- GaAs gallium arsenide
- GaP gallium phosphide
- SiC silicon carbide
- SiAs gallium arsenide
- GaP gallium phosphide
- SiC silicon carbide
- SiAs gallium arsenide
- GaP gallium phosphide
- SiC has a 20% lattice mismatch
- GaAs has a 4% lattice mismatch
- GaP has a 0.34% lattice mismatch.
- thermal expansion coefficients which differ from Si.
- Si has a thermal expansion coefficient of around 2.6 * 10 ⁇ 6 (°C) ⁇
- GaAs has a thermal expansion coefficient of around 6.7 x 10 ⁇ 6 (°C) _1
- GaP has a thermal expansion coefficient of around 5.91 x 10 ⁇ 6 (°C) _1 . Because of these differences, only thin layers of these materials have been successfully grown on Si without the formation of significant defects.
- the maximum thickness for a low defect layer of SiC grown on Si is only a few angstroms (A) and for GaAs grown on Si is less than 200 A. At these thicknesses or less, strain which is caused by lattice mismatch is contained by lattice stretching rather than crystal defects.
- Thinner, low-defect thicknesses of these materials do not possess a sufficient thickness to protect the base-emitter junction from shorting due to diffusion of metal from the emitter contact region. Thicker, high-defect thicknesses of these materials exhibit degraded junction performance due to an excessive number of defects.
- the most successful HBT improvements to date are believed to have been achieved by forming a GaP layer over Si at the base-emitter junction. GaP is desirable because it has a relative large bandgap (i.e. about 2.24 eV) and little lattice mismatch with silicon (i.e. about 0.34%). Nevertheless, such conventional HBTs that use a GaP layer over Si still achieve only a small portion of the performance benefits that HBTs theoretically promise.
- a Si substrate is desirable for mechanical stability and because a manufacturing infrastructure exists for reliably mass producing rugged Si wafers at relatively low cost.
- the Si substrate is typically an extrinsic part of the photoelectric semiconductor not used in forming intrinsic photoelectric semiconductor junctions.
- Such buffer layers tend to incrementally shift lattice constants and thermal expansion coefficients so that the intrinsic direct gap photoelectric semiconductor materials may then be grown with fewer defects.
- Such applications often form relatively thick buffer layers which themselves may have numerous defects, at least closer to a Si interface, that are of little consequence to the intrinsic photoelectric semiconductor. Needless to say, such buffer layers are not used in forming semiconductor junctions.
- HBT heteroj unction bipolar transistor
- Another advantage of the present invention is that a HBT is provided which uses a Si substrate. Another advantage is that an HBT having a multilayer emitter is provided.
- HBT has a wide bandgap emitter along with a base-emitter junction that is substantially free of interdiffusion.
- an HBT is provided with a Si base region that forms a junction with a multilayer emitter having a thin GaAs layer proximate the base region and a distal GaP layer.
- Another advantage is that an HBT is provided that exhibits performance which more closely meets theoretical expectations than conventional HBTs.
- a heteroj unction bipolar transistor which includes a Si collector region of a first conductivity type.
- a Si base region of a second conductivity type resides adjacent to the collector region.
- a GaAs layer resides over and in contact with the Si base region.
- the GaAs layer forms a first portion of a multilayer emitter.
- a GaP layer of the first conductivity type resides over the GaAs layer and forms a second portion of the multilayer emitter.
- Figs. 1 — 10 shows sectional views of an HBT at first through tenth processing stages, respectively;
- FIG. 11 shows a schematic, zero biased, band diagram of a composite emitter HBT according to a preferred embodiment of the present invention.
- FIG. 1 illustrates a first processing stage in which a buried region 22 is formed in a silicon (Si) substrate 24.
- substrate 24 is lightly doped P-type conductivity
- buried region 22 is heavily doped through a standard ion implantation process to exhibit N-type conductivity for this NPN implementation.
- FIG. 2 illustrates a second processing stage that follows the first processing stage depicted in FIG. 1.
- a collector layer 26 is epitaxially grown on substrate 24. Buried region 22 is now diffused into both collector layer 26 and substrate 24.
- Collector layer 26 is a lightly doped N-type conductivity. Phosphorous, antimony or arsenic N-type dopants are used through conventional techniques, such as ion implantation or diffusion, to achieve the desired conductivity type. Buried region 22 allows collector layer 26 to exhibit a low resistance while controlling the breakdown voltage of HBT 20.
- the thickness of collector layer 26 is selected to achieve application-specific goals. For example, collector layer 26 is desirably thinner to increase the speed of HBT 20 and thicker to increase the breakdown voltage of HBT 20.
- FIG. 3 illustrates a third processing stage that follows the second processing stage depicted in FIG. 2.
- FIG. 3 shows several independent diffusion areas formed in collector layer 26.
- a highly doped P-type conductivity isolation diffusion area 28 is made to surround a collector region 30, which provides proper isolation for the final HBT 20.
- Collector region 30 will eventually serve as the collector of HBT 20. Area 28 desirably refrains from overlying any portion of buried region 22.
- a highly doped N-type conductivity contact-enabling diffusion area 32 is made at a location within collector region 30 where a metallized layer will eventually make an electrical collector contact. This location desirably overlies a portion of buried layer 22.
- a base region 34 is another diffusion area that is also formed within collector region 30. Base region 34 will eventually serve as the base of HBT 20. Base region 34 is doped to exhibit P-type conductivity for this NPN implementation. Desirably, base region 34 is heavily doped so that the base of HBT 20 will exhibit an unusually low resistance. Diffusion areas 28, 32 and 34 are formed using conventional ion implantation or other techniques.
- Isolation and contact enabling areas 28 and 32 are desirably formed using a much higher acceleration voltage than base region 34 to drive areas 28 and 32 deeper into collector layer 26 than base region 34.
- a small amount of germanium (Ge) is mixed with the
- Si of base region 34 to lower the bandgap of the base of HBT 20 when compared to the bandgap of a base formed using more pure Si.
- This mixing is desirably performed during the second stage depicted in FIG. 2.
- Small amounts of Ge (e.g. around 10%) with a P+ type doping can be mixed with the Si during only the later portion of epitaxial growth for collector layer 26 to form the base.
- FIG. 4 illustrates a fourth processing stage that follows the third processing stage depicted in FIG. 3.
- FIG. 4 illustrates heat being applied to further drive diffusion areas 28, 32 and 34 deeper into collector layer 26.
- Isolation diffusion area 28 is desirably driven through collector layer 26 to substrate 24.
- Contact enabling area 32 is desirably driven through collector region 30 to buried region 22.
- base region 34 is desirably driven only a shallow depth into collector layer 26. Desirably, base region 34 is around 1000 A deep. However, the resulting base of HBT 20 will be more shallow than this depth due to subsequent etching steps. This shallow depth of base region 34 leads to a low transit time, which increases the high current gain cut-off frequency (F t ) and high power gain cut-off frequency (F max ) parameters for HBT 20.
- F t current gain cut-off frequency
- F max high power gain cut-off frequency
- FIG. 5 illustrates a fifth processing stage that follows the fourth processing stage depicted in FIG. 4.
- FIG. 5 actually illustrates two epitaxial growth processes.
- the first epitaxial growth process grows a wide bandgap, non-silicon semiconductor, preferably gallium arsenide (GaAs), over and in contact with collector layer 26 to form a first emitter layer 36 of a multilayer emitter 38 (see FIG. 6).
- GaAs gallium arsenide
- First layer 36 may be of N-type conductivity for this NPN implementation or may not be intentionally doped, but is desirably configured so as not to exhibit P-type conductivity.
- a function of first emitter layer 36 is a diffusion barrier to provide a stable interface with the Si of base region 34.
- the second epitaxial growth process grows a second non-silicon, wide bandgap semiconductor, preferably gallium phosphide (GaP), over and in contact with first layer 36 to form a second emitter layer 40 of multilayer emitter 38.
- second layer 40 is degeneratively doped with a suitable N-type conductivity material for this NPN implementation, such as Si, to values in excess of 10 x 10 20 /cm 3 to provide a very low emitter contact resistance where a metallized layer will eventually make an electrical emitter contact.
- doping gradually increases as second layer 40 builds away from first layer 36 to reach the maximum value at the distal surface from first layer 36.
- the function of second emitter layer 40 is to provide maximum valence band discontinuity with minimum lattice mismatch and minimal thermal expansion mismatch with respect to Si.
- GaAs is a desirable material for use as an interface with Si because it can form an interface substantially free from interdiffusion, particularly when compared to the interdiffusion that results from forming a GaP layer on Si.
- an atomically abrupt interface forms between GaAs layer 36 and base region 34.
- first layer 36 is epitaxially grown using conventional techniques but at a relatively low temperature (e.g. 400-600° C) to keep the Si-GaAs junction as free from interdiffusion as possible. Alternate cycles of even lower temperatures (e.g. 150-250° C) may be applied during the growth process. This results in a substantially pure crystalline structure suitable for intrinsic semiconductor activity.
- first layer 36 is limited in thickness so that first layer 36 will be coherently strained between the Si of base region 34 and second layer 40. Thickness is limited in a manner understood to those skilled in the art by controlling the time over which first layer 36 is grown.
- a coherently strained layer is a layer so thin that lattice constant mismatches do not result in lattice mismatch crystal defects but are contained by lattice stretching.
- first layer 36 made from GaAs
- second layer 40 made from GaP
- a thickness for layer 36 of less than 200 A is preferred, with a thickness of less than 50 A being particularly desirable.
- the thickness of second emitter layer 40 is desirably much greater than the thickness of first emitter layer 36.
- Layer 40 is desirably at least 500 A thick, and preferably around 2000-3000 A thick. Less overall thickness is desired for emitter 38. Less thickness leads to a smaller emitter resistance and a faster HBT 20. However, the thickness of emitter 38, and primarily second emitter layer 40, is balanced with a need to prevent the emitter and base of HBT 20 from shorting. Shorting can occur when metallization, discussed below, diffuses through emitter 38 to reach base region 34. A sufficient thickness for second layer 40 prevents metallization from diffusing therethrough. Second layer 40 is desirably grown epitaxially using standard techniques at temperatures that generally remain in the 400-600° C range to preserve the substantially interdiffusion-free interface between first emitter layer 36 and base region 34.
- temperature may be lowered so that this portion of second emitter layer 40 becomes polycrystalline. Among other benefits, this lessens the time HBT 20 spends at elevated temperatures to further lessen risks of interdiffusion at the base-emitter junction.
- first emitter layer 36 provides an abrupt interface with Si base region 34
- second layer 40 provides as great of a bandgap discontinuity as is practical.
- the bandgap characteristics of HBT 20 in the vicinity of the base-emitter junction are determined primarily by the bandgap differences between materials used for base region 34 and second layer 40.
- the abruptness of the base-emitter junction i.e. the congruence of the metallurgical and electrical junctions
- base region 34 Due to the thin, coherently strained nature of first emitter layer 36, base region 34 exhibits few defects.
- second emitter layer 40 although relatively thick, exhibits few defects in part because first emitter layer 36 is sufficiently thin to be coherently strained.
- FIG. 6 illustrates a sixth processing stage that follows the fifth processing stage depicted in FIG. 5.
- FIG. 6 shows a patterning and etching process. Conventional photolithographic techniques can be used to pattern HBT 20, then etching is performed to remove portions of first and second emitter layers 36 and 40 that will not be used for emitter 38.
- FIG. 7 illustrates a seventh processing stage that follows the sixth processing stage depicted in FIG. 6.
- FIG. 7 shows a passivation process.
- Conventional techniques are used to apply a passivation layer 42 over the entire surface of HBT 20 at this point. Silicon nitride, silicon dioxide, or other conventional passivation materials may be applied in a conventional manner, so long as temperatures generally remain below about 800° C.
- FIG. 8 illustrates an eighth processing stage that follows the seventh processing stage depicted in FIG. 7.
- FIG. 8 shows another patterning and etching process.
- Conventional photolithographic techniques can be used to pattern HBT 20, then etching is performed to remove passivation layer 42 to form vias 44 in locations where a metallized layer will eventually make electrical contacts.
- FIG. 9 illustrates a ninth processing stage that follows the eighth processing stage depicted in FIG. 8.
- FIG. 9 shows a metallization process which uses conventional techniques to deposit a metallized layer 46 over the entire surface of HBT 20.
- FIG. 10 illustrates a tenth processing stage that follows the ninth processing stage depicted in FIG. 9.
- FIG. 10 shows yet another patterning and etching process.
- Conventional photolithographic techniques can be used to pattern HBT 20, then etching is performed to remove metallization layer 46 where not wanted over the surface of HBT 20.
- metallization layer 46 remains within and over vias 44 to form electrical contacts with the base, collector, and emitter regions of HBT 20.
- FIG. 11 shows a schematic, zero biased, band diagram for HBT 20.
- FIG. 11 depicts a conduction band (E c ) trace 48 and a valence band trace (E v ) 50 on vertically opposing sides of a Fermi level (Ef) 52.
- the band diagram of FIG. 11 is horizontally partitioned into four sections 30', 34', 36' and 40' corresponding to collector region 30, base region 34, first emitter layer 36, and second emitter layer 40 (FIG. 10), respectively.
- the bandgap energy equals E c -E v , or approximately 1.12 eV.
- base region 34 the bandgap energy still equals approximately 1.12. eV. In other words, base region 34 has roughly the same bandgap as collector region 30.
- the bandgap energy equals approximately 1.42 eV.
- This increase of roughly 0.3 eN from the bandgap of base region 34 and collector region 30 is due to the higher bandgap of GaAs compared to the bandgap of Si.
- substantially all of this 0.3 eV appears as a discontinuity 54 in the valence band E v .
- Very little of the increase in bandgap achieved by transitioning from Si to GaAs in first layer 36 appears in conduction band E c .
- the bandgap equals approximately 2.24 eV. This represents an increase of roughly 0.8 eV from the bandgap in first emitter layer 36. Accordingly, another discontinuity in the bandgap energy results. This discontinuity is divided between a valence band discontinuity 56 of approximately 0.5 eV and a conduction band discontinuity 58 of approximately 0.3 eV.
- the total bandgap discontinuity between second layer 40 and base region 36 is approximately 1.1 eV, with the majority of the discontinuity appearing in the valence band E v .
- the majority of the discontinuity appearing in the valence band E v is desirable for NPN transistors because it is the parameter that characterizes the suppression of hole injection.
- first layer 36 provides a stable, abrupt semiconductor junction at base region 34 and simultaneously allow second layer 40 to be epitaxially grown with few defects, but first layer 36 also causes a larger portion of the total bandgap discontinuity between emitter 38 and base region 34 to appear as a valence band discontinuity, which is particularly useful in suppressing hole injection.
- This relatively large valence band discontinuity significantly suppresses hole injection from base region 34 to emitter 38, creating an HBT with greatly improved emitter injection efficiency compared to prior art HBTs.
- an improved HBT having a wide bandgap with a low interdiffusion base-emitter junction is provided along with a method for forming the HBT.
- the HBT uses a Si substrate which is desirable because this takes advantage of the existing manufacturing infrastructure that reliably produces relatively rugged Si wafers at low cost.
- a multilayer emitter is provided in the HBT. This emitter exhibits a wide bandgap, and the resulting base-emitter junction is substantially free of interdiffusion.
- the HBT is provided with a Si base region that forms a junction with a multilayer emitter having a thin GaAs layer proximate the base region and a distal GaP layer.
- the base-emitter junction, which is substantially free of interdiffusion, and the wide bandgap multilayer emitter together allow an HBT configured in accordance with the present invention to exhibit performance more closely meeting theoretical expectations than does the performance of conventional HBTs.
Abstract
Description
Claims
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP98945940A EP1019966A4 (en) | 1997-09-29 | 1998-09-08 | Heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction |
AU93075/98A AU9307598A (en) | 1997-09-29 | 1998-09-08 | Heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction |
JP2000514337A JP2001518716A (en) | 1997-09-29 | 1998-09-08 | Heterojunction bipolar transistor with wide bandgap low interdiffusion base-emitter junction |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
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US08/939,487 US5912481A (en) | 1997-09-29 | 1997-09-29 | Heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction |
US08/939,487 | 1997-09-29 |
Publications (1)
Publication Number | Publication Date |
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WO1999017372A1 true WO1999017372A1 (en) | 1999-04-08 |
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Family Applications (1)
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PCT/US1998/018686 WO1999017372A1 (en) | 1997-09-29 | 1998-09-08 | Heterojunction bipolar transistor having wide bandgap, low interdiffusion base-emitter junction |
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US (2) | US5912481A (en) |
EP (1) | EP1019966A4 (en) |
JP (1) | JP2001518716A (en) |
AU (1) | AU9307598A (en) |
WO (1) | WO1999017372A1 (en) |
Families Citing this family (9)
Publication number | Priority date | Publication date | Assignee | Title |
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US6423990B1 (en) * | 1997-09-29 | 2002-07-23 | National Scientific Corporation | Vertical heterojunction bipolar transistor |
US6211095B1 (en) * | 1998-12-23 | 2001-04-03 | Agilent Technologies, Inc. | Method for relieving lattice mismatch stress in semiconductor devices |
US6362065B1 (en) * | 2001-02-26 | 2002-03-26 | Texas Instruments Incorporated | Blocking of boron diffusion through the emitter-emitter poly interface in PNP HBTs through use of a SiC layer at the top of the emitter epi layer |
US6696710B2 (en) * | 2001-02-27 | 2004-02-24 | Agilent Technologies, Inc. | Heterojunction bipolar transistor (HBT) having an improved emitter-base junction |
US7300849B2 (en) * | 2005-11-04 | 2007-11-27 | Atmel Corporation | Bandgap engineered mono-crystalline silicon cap layers for SiGe HBT performance enhancement |
US7439558B2 (en) | 2005-11-04 | 2008-10-21 | Atmel Corporation | Method and system for controlled oxygen incorporation in compound semiconductor films for device performance enhancement |
US7651919B2 (en) * | 2005-11-04 | 2010-01-26 | Atmel Corporation | Bandgap and recombination engineered emitter layers for SiGe HBT performance optimization |
US20070102729A1 (en) * | 2005-11-04 | 2007-05-10 | Enicks Darwin G | Method and system for providing a heterojunction bipolar transistor having SiGe extensions |
EP3664151A1 (en) * | 2018-12-06 | 2020-06-10 | Nexperia B.V. | Bipolar transistor with polysilicon emitter and method of manufacturing |
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1998
- 1998-09-08 EP EP98945940A patent/EP1019966A4/en not_active Withdrawn
- 1998-09-08 AU AU93075/98A patent/AU9307598A/en not_active Abandoned
- 1998-09-08 JP JP2000514337A patent/JP2001518716A/en active Pending
- 1998-09-08 WO PCT/US1998/018686 patent/WO1999017372A1/en not_active Application Discontinuation
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1999
- 1999-03-12 US US09/267,252 patent/US6171920B1/en not_active Expired - Fee Related
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Also Published As
Publication number | Publication date |
---|---|
EP1019966A1 (en) | 2000-07-19 |
US5912481A (en) | 1999-06-15 |
AU9307598A (en) | 1999-04-23 |
US6171920B1 (en) | 2001-01-09 |
EP1019966A4 (en) | 2000-07-19 |
JP2001518716A (en) | 2001-10-16 |
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