WO1999025023A1 - Asic routing architecture - Google Patents
Asic routing architecture Download PDFInfo
- Publication number
- WO1999025023A1 WO1999025023A1 PCT/US1998/022985 US9822985W WO9925023A1 WO 1999025023 A1 WO1999025023 A1 WO 1999025023A1 US 9822985 W US9822985 W US 9822985W WO 9925023 A1 WO9925023 A1 WO 9925023A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- metal layer
- parallel
- insulating layer
- conductors
- over
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0207—Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/118—Masterslice integrated circuits
Definitions
- the present invention generally relates to integrated circuits, and more specifically, to a routing architecture for interconnecting various IC devices to form a customized circuit.
- ASICs are widely used by electrical design engineers to include specialized circuitry in their designs using only a single chip.
- ASIC actually refers to a variety of integrated circuit (IC) styles that vary in degree of customizability, including standard cells, which are completely customizable, and gate arrays, which are partially customizable. As a general rule, the more customization that is required, the more expensive the ASIC will be and the longer the ASIC will take to fabricate and/or customize.
- Fig. 1 shows a cross-sectional view of a generic integrated circuit.
- active layers are formed on a semiconductor substrate.
- the active layers 110 include devices such as transistors and diodes. Most active layer devices are formed independently of one another, i.e., they are not connected to form a circuit.
- metal layers are formed over the active layers to interconnect the devices, thereby forming a circuit.
- metal layers may be required to completely interconnect the devices to form a useful circuit.
- Ml 120, M2 130, M3 140 and M4 150 are shown in Fig. 1.
- different types of ICs may require more or less than four metal layers for circuit interconnection.
- each metal layer In between each metal layer is an insulating layer 115, 125, 135, 145 as shown in Fig. 1. Insulating layers are present to prevent shorts between metal layers. To interconnect the metal layers, vias 116 are formed through the insulating layers.
- an insulating layer 115 is formed over the active layers 110, for instance, by growth or deposition of insulating material.
- a masking step is utilized to form vias in the insulating layer, as is generally known in the art.
- Such masking often entails depositing a photoresist layer and patterning the layer using ultra-violet light, enabling removal of only selected portions of the photoresist, and then etching the insulating layer in accordance with the photoresist pattern.
- a metal layer is deposited and then patterned using a similar masking process, so that metal remains only in desired locations. The process is repeated for each insulating layer and metal layer required to be formed.
- each metal layer required to be formed generally demands at least two masking steps: one step to form vias through the insulating layer to connect to the layer below and one step to form connection wires or lines.
- each mask step required generally entails significant time and expense.
- ASIC active devices are generally arranged to form an array of function blocks, also commonly referred to as cells or modules.
- To interconnect active devices within each function block i.e., form "local interconnections" a series of horizontal and vertical connection lines formed in the metal layers are utilized. As is well understood in the art, any two points can be connected using a series of horizontal and vertical connection lines. While such local interconnections can be done in one metal layer, more typically, horizontal connections are formed in a first metal layer (Ml) 120 and vertical connections are formed in a second metal layer (M2) 130 with an insulating layer 125 having vias
- Ml first metal layer
- M2 second metal layer
- horizontal is meant to describe all metal lines running in a first direction such that all horizontal lines lie substantially parallel to one another.
- Vertical is meant to convey all lines that run in a second direction which is substantially perpendicular to the first (horizontal) direction. Neither “horizontal” nor “vertical” is meant to convey anything more specific than relative position to one another.
- horizontal lines and vertical lines are formed in the metal layers which are parallel to the active layer surface. “Horizontal” and “vertical” do not convey lines that are pe ⁇ endicular to the active layer surface.
- each function block 160 (160a-160i) will have a unique number and arrangement of active devices and will thus vary in horizontal size with respect to one another (although they are typically structured to have the same vertical height).
- Function blocks 160 are shown with dashed lines to indicate their conceptual formation in active layers 110.
- local interconnections within each function block are typically formed by horizontal lines in Ml, e.g., 174, 176, and vertical lines in M2, e.g., 178.
- the horizontal and vertical lines are connected in their respective layers by vias, shown as “dots.” Vias may not only connect Ml and M2 to each other but may also connect Ml and/or M2 to an active layer.
- the function blocks 160 are further formed into rows 170a, 170b, 170c. Each row is separated from one another by a "channel" region 172a, 172b. The channel region is then used for horizontal routing between function blocks to avoid routing over the function block space. For instance, referring to Fig. 2, channel lines 180-182 and 184-186 are formed in channels 172a and 172b, respectively, using Ml.
- Vertical lines 190-199 are formed in M2. Vertical lines 190-193 are used to couple the active devices in function block 160d to channel lines. The channel lines in turn are further connected (in M2) to other function blocks, e.g., with vertical lines 194-199. As shown, the channel lines can run the entire length of the channel or can run for a short distance within the channel.
- Vias in the function block are connected to channel lines with connector lines that enter from above the function block, e.g., line 192, from below the function block, e.g., line 193, or double entry (connected from above and below), e.g., lines 190, 191. Lines could also simply "feed-through" the function block with no connection to a via; however, feed-throughs are often impractical because of dense local interconnections within the function blocks, limiting routing flexibility.
- Gate like standard cells, arrays have also used an approach as described above with reference to Fig. 2. That is, gate arrays have also been fabricated with channels to use for routing between function blocks. In gate arrays, however, the active layers are fixed (non-customizable), having a predefined number and arrangement of active devices in each function block. Thus, while fully- customizable standard cells can customize channel size larger or smaller, in gate arrays the channel size is fixed, further limiting routing flexibility.
- Each function block 302 (302a-302i) is substantially contiguous to adjoining function blocks on each side — in other words, no routing channels are formed.
- substantially contiguous function blocks can increase the functionality available per IC since no fixed space is wasted for channels.
- local interconnections within each function block are still typically formed with horizontal and vertical connections using Ml and M2, respectively, such as shown in function block 302g. Nonetheless, routing among function blocks is still restricted in that routing lines cannot always cross over the used function block space due to the local interconnect density. Therefore, typically in the channel-less structure of Fig. 3 routing is also done over selectively unused function blocks. Occasionally, even whole rows of function blocks are selectively unused in order to allow routing much like a channeled device, although more commonly only individual function blocks are selected to be reserved for routing, e.g., function blocks 302d and 302e.
- each custom mask step will take considerable time and money. Often important to an IC or electronic circuit designer is customization time. Particularly during the design stages, the engineer may want to obtain a model, or prototype, of his or her designs quickly so that the designs can be tested with other circuitry. In such circumstances, the engineer may opt for a gate array because, although not as flexible as standard cells, it will be faster to get a working chip because fewer mask steps are required for circuit customization (i.e., standard cells require formation of active devices, while gate arrays have pre-formed active devices and only require metalization). Nonetheless, gate arrays can still take several weeks' time to obtain because of the multiple custom mask steps that must be performed just for metalization.
- the routing architecture is generally designed for use with the uppermost two metal layers in an ASIC composed of an array of function blocks. At least some of the metal layers below the uppermost two metal layers are used for local interconnections within function blocks.
- the second-to-uppermost metal layer of an architecture in accordance with the invention has a predefined and fixed layout, including a plurality of parallel segmented conductors extending in a first direction in one embodiment of the invention.
- This second-to-uppermost, or "fixed”, metal layer also includes pin connections to the inputs and outputs of the function blocks.
- vias are formed through the insulating layer to the fixed metal layer below.
- these vias are formed to couple to the endpoints of each segment of the segmented conductors as well as to couple to various points between the endpoints of some of the segments.
- Other embodiments of the invention allow some or all of the vias to be placed in a customized manner.
- the uppermost metal layer On top of the insulating layer is formed the uppermost metal layer, or "customizable" metal layer.
- Metal in the customizable metal layer is selectively placed within a plurality of parallel predesignated tracks that are over the area space of the parallel segmented tracks of the fixed metal layer and that run in a second direction substantially perpendicular to the first direction.
- the routing architecture of the present invention permits flexible routing of horizontal and vertical connections among function blocks and does so in the area space directly above the function blocks without using channels for customized routing and without rendering function blocks unusable.
- an ASIC built in accordance with one embodiment of the invention can be customized with a single mask step, creating a customized ASIC in a short time period and at a reduced cost.
- the routing architecture still permits high performance designs to be implemented.
- Fig. 1 is a cross-sectional view of a generic integrated circuit
- Fig. 2 is a generalized block diagram of a standard cell ASIC using channeled routing
- Fig. 3 is a generalized block diagram of a gate array using a channel-less routing approach
- Fig. 4 is a generalized block diagram of an ASIC in accordance with the invention.
- Fig. 5 is a generalized block diagram of a function block in accordance with one embodiment of the invention.
- Figs. 6-9 are each generalized block diagrams of an architecture in accordance with the invention showing various features and/or enhancements utilized by some embodiments of the invention.
- Fig. 6a is a legend for use with Figs. 6-9;
- Fig. 10 shows a block diagram of an example of routing placement in accordance with one embodiment of the invention.
- Fig. 11 is a generalized block diagram of a routing architecture in accordance with the invention.
- Figs. 12a-12c show a portion of Fig. 11 and an example of routing using the architecture shown in Fig. 11 ;
- Fig. 13 is a generalized block diagram of a portion of an architecture in accordance with one embodiment of the invention and showing use of a power bar;
- Fig. 14 is a generalized block diagram of a portion of an architecture in accordance with one embodiment of the invention and showing use of a double- width wire as well as mode pins;
- Fig. 15 is a generalized block diagram of a portion of an architecture in accordance with one embodiment of the invention and showing pin "twisting;" and
- Figs. 16-18 are each generalized block diagrams of portions of an architecture in accordance with alternative embodiments of the invention.
- a generalized block diagram of an ASIC 400 in accordance with the invention is shown in Fig. 4.
- ASIC 400 includes an array 410 of function blocks 420.
- each function block 420 is identical to the other function blocks in array 410, although other embodiments of the invention allow for variance among function blocks.
- Some embodiments may include one or more other regions 421, which contain other circuitry such as memory blocks or logic cores.
- periphery area 430 surrounding array 410.
- Periphery area 430 includes circuitry such as IO pads and other support circuitry for array 410.
- Each function block 420 can be configured to perform combinational functions, sequential functions and/or memory functions (e.g., SRAM).
- one embodiment of function block 420 is generally composed of three modules: two computation modules 440 and 450 and a communication module 460, each having a fixed internal architecture, including arrangement and connection of active devices, but whose functions can be varied by varying input signals to each module. For instance, an input may be varied by tying the input to a logical high signal, a logical low signal, the output of the same or different module or a signal from off-chip.
- SRAM sequential functions and/or memory functions
- each module, and the entire function block 420 for that matter has any number of inputs, ⁇ ...I,, and any number of outputs, O j .-.O n ,.
- Computation modules 440 and 450 are identical mirror images of each other in one embodiment of the invention. A detailed description of one embodiment of the internal structure of each function block 420, including computation and communication modules 440, 450, and 460, can be found in application serial no. 08/821,475, filed on March 21, 1997, and entitled "Function Block Architecture for Gate Array,” incorporated by reference herein.
- each function block 420 is substantially contiguous to each adjacent function block. In other words, no channels are formed between the function blocks 420 in one embodiment of the invention.
- Each function block 420 has a fixed internal transistor structure with fixed connections between the transistors and/or other active devices within each function block 420. Thus, all of the routing internal to each function block 420 will be fixed (non-customizable) and lower metal layers, e.g., Ml and M2, can be pre-formed in a fixed and predetermined manner, using horizontal connectors in Ml and vertical connectors in M2 (or vice versa). Of course, more than two metal layers can be used to form the local interconnections within each function block 420 in other embodiments of the invention.
- an array in accordance with the invention will be customized by varying the inputs to each function block.
- the customization of the array entails forming the connections between the function blocks and connections to power and ground lines.
- customization is done by routing.
- the architecture in accordance with the invention allows routing between function blocks to be customized using the uppermost two metal layers for a given integrated circuit.
- these uppermost two metal layers will be referred to as M3 and M4. It is to be understood, however, that since there could be more than four layers, the uppermost two metal layers for a given integrated circuit may not actually be M3 and M4, but may be, for example, M5 and M6, M7 and M8, etc. Use of the terms M3 and M4 is not intended to limit the invention.
- a third metal (M3) layer (the second-to-uppermost metal layer) is composed of a plurality of a parallel segmented conducting lines 510, each composed of multiple segments 512. Each segment 512 has a via 530 formed at its respective ends to enable connections to the uppermost (M4) layer above.
- M4 layer horizontal tracks 550 run perpendicular to the segmented conducting lines 510.
- Tracks 550 are not fixed metal, but rather represent predesignated areas where metal can be placed in the M4 layer to form an interconnection.
- Fig. 6 represents a structure that allows horizontal and vertical connections to enable routing, where the vertically placed metal is fixed and pre-formed and the horizontally placed metal is customizable in a predesignated manner.
- M4 metal can be placed in horizontal M4 track 551, extending from M3 segment 512a to M3 segment 512b.
- M4 metal would also be placed to form a connection from the metal in track 551 to the via at point A and at point X.
- M4 metal would also be placed to form connections between vias 530a and 530b as well as vias 530c and 530d.
- Fig. 6 A shows a legend for Fig. 6.
- Fig. 6 A indicates that the metal of M3 for each segment 512 has a given width and is lain to surround the vias 530 at either end of each segment 512, resembling a "dogbone.”
- the segments 512 of each parallel segmented conducting line 510 are sometimes referred to herein as "dogbones.”
- Horizontal lines 550 represent the tracks where M4 metal can be placed in customizing the circuit.
- Fig. 7 As can be seen using the structure of Fig. 6, once particular tracks are utilized in M4, obstructions to forming other connections will occur. For instance, if tracks 551 and 554 have been utilized in forming other connections, tracks lying between these two tracks, 552, 553 may not be able to access a via. Therefore, in Fig. 7, additional vias 560 are added for each dogbone (segment) 512. Vias 560 are added such that each via 560 has unobstructed access to two M4 tracks: one track from above and one track from below. Note that although vias 530 and 560 are shown as different sizes in Fig. 7, no distinction in actual size need be made in various embodiments of the invention, and such size distinction is used merely for clarity of the illustration.
- Pin connections 570 to the inputs and outputs of the function blocks are placed in M3 between the ends of the short dogbones 572 and are formed in a manner similar to that used for forming vias. Therefore each pin 570 can be selectively connected to the M4 layer through the vias at the end of each short dogbone 572. In other words, the pins themselves do not reach M4 except through the vias at the ends of short dogbones 572 in one embodiment of the invention. Further, the pins 570 are easily connected to longer dogbones 512 for vertical routing by coupling the vias of the vertical segmented connectors 510. For instance, to connect pin 570a to point E, vias 530e and 53 Of are coupled in M4. Also in Fig.
- dedicated power and ground lines are formed in M4 at 574 and 576, where line 574 represents a dedicated power line and 576 represents a dedicated ground line. While other embodiments of the invention do not utilize the short segments 572, simply bringing pin connections to M3 amid longer dogbones 512, utilizing the short segments 572 allows additional flexibility. Without the short segments, the easy ability to connect to power and ground would disappear as routing to power and ground would be through the longer dogbones 512, decreasing active routing density and reducing flexibility.
- Fig. 10 shows a more detailed view of an example demonstrating how various pins are connected to signals.
- Fig. 10 shows pin 570c coupled to power while pin 570e is coupled to ground.
- Pin 570d is coupled to long dogbone 512e.
- Fig. 11 shows one embodiment of the routing structure as described with respect to Figs. 6-9. All of the vertical connectors shown (parallel segmented connectors 510 and freeways 580) are fixedly formed in M3. Horizontal lines 550 represent tracks in which M4 metal can be selectively placed for customized routing. All of the routing is formed over the area space where active devices for each function block are formed. Thus, as shown, the routing structures in M3 and M4 between lines 600 and 605 are over the area space of a first row of function blocks 420a while the routing structures shown between lines 605 and 610 is over the area space of a second row of function blocks 420b.
- the routing structure formed above line 600 and below line 610 are areas over function blocks adjacent to Function Block Row 420a and Function Block Row 420b, respectively.
- Pins 570 represent the inputs and outputs to the function blocks in rows 420a and 420b.
- the vertical connectors 510 in M3 are segmented to allow selective joining of the segments, permitting a flexible routing structure.
- long dogbones 512 in the M3 layer include in one embodiment, multiple vias between the long dogbone ends.
- Each via has access to two M4 tracks — one track above the via and one track below the via.
- Freeways 580 may be placed singly, with segmented connectors 510 on either side, as shown at 580 j . In other instances, more than one freeway may be placed next to one another as shown at 580 2 and 580 3 . Often, it will be useful to place a freeway next to a segmented conductor 510 having an output pin in a short dogbone 572 since outputs are often routed for longer distances.
- a flexible routing architecture is provided, allowing each pin to receive signals from above the function block 420 or from below the function block 420, as well as double entry signals. Further feed-through signals (using freeways 580) can easily be implemented. (Routing for specialized regions 421 can be done in accordance with the invention or by their own routing structure.)
- Fig. 12c shows an enlarged portion of function block row 420a shown in Fig. 11.
- Fig. 12c will be used to describe an example using a routing architecture in accordance with the invention.
- the active layers may define several transistors, which when connected by Ml and M2 layers (and/or by one or more layers below the uppermost two metal layers) form multiplexor 700 shown in Fig. 12b.
- Multiplexor 700 will have several inputs, D0-D3, SO, and SI.
- Multiplexor 700 will also have an output P.
- the multiplexor 700 can be configured to form the 3-input AND gate of Fig.
- each input and output of multiplexor 700 is coupled to a pin 570.
- Pin DO would be connected to ground, line 576, as would pin Dl and pin D2.
- Pin D3 is coupled by via 702 to via 704 and along track
- An architecture in accordance with the invention has thus been described that allows for flexible interconnections over the space provided for active (used) function block areas.
- the routing architecture is provided with the second-to- uppermost metal layer being fixed.
- An insulating layer with vias formed therein is formed over the second-to-uppermost metal layer.
- some embodiments of the invention allow the via placement to be customizable.
- the uppermost metal layer, formed over the insulating layer is customizable in a predetermined manner (i.e., M4 metal is to be placed in pre- designated places).
- M4 metal is to be placed in pre- designated places.
- Fig. 13 shows an additional benefit to the routing architecture of the present invention.
- a power bar 1010 is placed in M3 between the vertical boundary of each function block 420.
- the power bar 1010 is tied to a constant voltage and is used for power distribution among the function blocks 420.
- a freeway 580 is placed adjacent to the power bar 1010 in each function block.
- Next to freeway 580 is placed a segmented conductor 510. In this manner, the freeway 580 adjacent to the power bar has a high probability of avoiding adjacent long signals.
- M4 metal lines of variable width can be formed, e.g., a double- width wire can easily be formed in M4 by utilizing adjacent horizontal tracks 808 and 809 and filling in M4 metal in the tracks and in between the tracks, as shown in Fig. 14 at 810.
- double-width wires are particularly useful for distributing clocks or providing power and ground lines.
- clock trunks (or "spines") can easily be implemented by forming several double-width wires and interconnecting them.
- a double-width wire can be formed with tracks 808 and 809 (double width wire 810) as well as tracks 811 and 812, and tracks 814 and 815, and then connecting each of the double- width wires so formed to one another, for example, in the space over power bar 1010 shown in Fig. 13 (since the power bar will have few obstructing vias).
- M3 segments beneath the clock trunk can be coupled to ground to form a partially isolating ground plane.
- segmented connectors in M3 can also be formed of variable width, i.e., the invention should not be construed as limited to a fixed metal layer of segmented connectors of equal width. For instance, because freeways 580 often carry signals for relatively long distances, it may be desirable in some embodiments of the invention to form freeways 580 wider than segmented connectors 510.
- One alternative embodiment of the invention may utilize stacked mode pins, i.e., pins that are always known to be a constant value. Such mode pins are shown in Fig. 14 at 850 and 860. By providing an additional connection to ground at 852, mode pin 850 could easily be connected to power line 574 or ground at 852, using M4. Likewise by providing an additional connection to power at 862, mode pin 860 could easily be coupled in M4 to ground line 576 or to power at 862. Because mode pins are not coupled to an active, changing signal, mode pins can be "stacked" in the vertical direction, preserving routing space.
- Fig. 11 Still other methods can easily be utilized with the architecture of Fig. 11 to improve system performance. For instance, if one function block pin is known to have a high usage rate while other pins are known to have much lower usage, then in every other row of function blocks the pins can be "twisted", or alternated. For instance, in Fig. 15, suppose a function block 420 contains pin X and pin Y. If pin
- X is a high usage pin and pin Y is low usage
- the pins can be reversed as shown in Fig. 15.
- the high usage pins have a higher chance of being unobstructed both above and below and more flexibility in routing is obtained (e.g., double entry is available on more pins in the function blocks).
- Other ways to increase routing density are to place pins that are often connected together next to each other. In this manner, the vias connected to the pins can be directly connected together with a short M4 metal connection that avoids usage of other routing resources.
- some embodiments of the invention use configurable vias between M3 and M4 rather than the fixed vias described with respect to the embodiment of Fig. 11.
- Such customizable vias would allow each row of inner vias (those between the ends of the dogbones) to be replaced by an additional track; customizable vias could then be placed to couple M3 metal to any M4 track.
- having configurable vias will increase the number of mask steps for customization to two mask steps, the turn-around time will still be fairly rapid while at the same time maintaining circuit functionality and increasing routing flexibility.
- each pin 570 could be permanently coupled to the long dogbone 512 above (or below) the pin 570, as illustrated in Fig. 17. Such a permanent coupling would force routing entry to the pin in a single direction, e.g., routing to the pin would always occur as a result of entry above the pin.
- Fig. 18 shows still another alternative embodiment of the invention where vertical segmented conductors 910 are formed in layer M3 along with power and ground lines. Vias are formed between layers M3 and M4 at segment end points as well as at various other points along the segments. Pins 970 are vertically stacked and are also formed up through to layer M4. Horizontal tracks 930 are available for placement of metal in M4. As shown in Fig. 18, there are two horizontal tracks positioned between each pair of vias allowing unobstructed access to tracks and routing flexibility.
- IO and periphery circuitry 430 can also be easily configurable with a method in accordance with the invention. For instance, it is desirable for IO pads to perform any of a plurality of functions. By providing switches that can be configured using M4, IO pads can be easily customized with the same single mask step utilized for configuring function blocks. Similarly, phase-locked loops (PLLs), ROMs, and other periphery circuitry can be configurable in much the same method, i.e., by placing jumpers or switches in the PLL, ROM, or other circuit.
- PLLs phase-locked loops
- routing architecture of the present invention has been described as essentially “channel-less,” in some embodiments there may be separation between the function blocks. For example, in some embodiments of the invention, there could be fixed routing in the regions between function blocks.
- channel-less as used herein is thus meant to convey a routing architecture with a majority of customizable routing over function blocks rather than being limited to separate channel regions in between function blocks.
- lower metal layers below the uppermost two metal layers have been described as being utilized for local interconnections within function blocks, their function is not necessarily so limited. For instance, some of the lower metal layers (or portions of some of the lower metal layers) could be used, in some embodiments, for power distribution, clock distribution, or even some fixed routing.
Abstract
Description
Claims
Priority Applications (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2000519925A JP4562908B2 (en) | 1997-11-10 | 1998-10-29 | ASIC wiring architecture |
EP98957421A EP1029355A1 (en) | 1997-11-10 | 1998-10-29 | Asic routing architecture |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US08/966,946 | 1997-11-10 | ||
US08/966,946 US6242767B1 (en) | 1997-11-10 | 1997-11-10 | Asic routing architecture |
Publications (2)
Publication Number | Publication Date |
---|---|
WO1999025023A1 true WO1999025023A1 (en) | 1999-05-20 |
WO1999025023B1 WO1999025023B1 (en) | 1999-07-01 |
Family
ID=25512099
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/US1998/022985 WO1999025023A1 (en) | 1997-11-10 | 1998-10-29 | Asic routing architecture |
Country Status (4)
Country | Link |
---|---|
US (1) | US6242767B1 (en) |
EP (1) | EP1029355A1 (en) |
JP (1) | JP4562908B2 (en) |
WO (1) | WO1999025023A1 (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6853019B2 (en) | 2002-05-17 | 2005-02-08 | Nec Electronics Corporation | Semiconductor device and manufacturing method for the same |
US7047514B2 (en) | 2001-04-04 | 2006-05-16 | Nec Electronics Corporation | Semi-custom-made semiconductor integrated circuit device, method for customization and method for redesign |
Families Citing this family (58)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6838713B1 (en) | 1999-07-12 | 2005-01-04 | Virage Logic Corporation | Dual-height cell with variable width power rail architecture |
US6756811B2 (en) * | 2000-03-10 | 2004-06-29 | Easic Corporation | Customizable and programmable cell array |
US6617621B1 (en) * | 2000-06-06 | 2003-09-09 | Virage Logic Corporation | Gate array architecture using elevated metal levels for customization |
US6567290B2 (en) * | 2000-07-05 | 2003-05-20 | Mosaic Systems, Inc. | High-speed low-power semiconductor memory architecture |
JP3555080B2 (en) | 2000-10-19 | 2004-08-18 | Necエレクトロニクス株式会社 | General-purpose logic module and cell using the same |
US7316934B2 (en) * | 2000-12-18 | 2008-01-08 | Zavitan Semiconductors, Inc. | Personalized hardware |
US6601227B1 (en) * | 2001-06-27 | 2003-07-29 | Xilinx, Inc. | Method for making large-scale ASIC using pre-engineered long distance routing structure |
US6944842B1 (en) * | 2001-06-27 | 2005-09-13 | Xilinx, Inc. | Method for making large-scale ASIC using pre-engineered long distance routing structure |
US6823499B1 (en) | 2001-09-18 | 2004-11-23 | Lsi Logic Corporation | Method for designing application specific integrated circuit structure |
US6873185B2 (en) | 2002-06-19 | 2005-03-29 | Viasic, Inc. | Logic array devices having complex macro-cell architecture and methods facilitating use of same |
US7064579B2 (en) * | 2002-07-08 | 2006-06-20 | Viciciv Technology | Alterable application specific integrated circuit (ASIC) |
US6992503B2 (en) * | 2002-07-08 | 2006-01-31 | Viciciv Technology | Programmable devices with convertibility to customizable devices |
US7312109B2 (en) * | 2002-07-08 | 2007-12-25 | Viciciv, Inc. | Methods for fabricating fuse programmable three dimensional integrated circuits |
US20040004251A1 (en) * | 2002-07-08 | 2004-01-08 | Madurawe Raminda U. | Insulated-gate field-effect thin film transistors |
US7064018B2 (en) * | 2002-07-08 | 2006-06-20 | Viciciv Technology | Methods for fabricating three dimensional integrated circuits |
US7129744B2 (en) * | 2003-10-23 | 2006-10-31 | Viciciv Technology | Programmable interconnect structures |
US7112994B2 (en) * | 2002-07-08 | 2006-09-26 | Viciciv Technology | Three dimensional integrated circuits |
US7673273B2 (en) | 2002-07-08 | 2010-03-02 | Tier Logic, Inc. | MPGA products based on a prototype FPGA |
US7812458B2 (en) * | 2007-11-19 | 2010-10-12 | Tier Logic, Inc. | Pad invariant FPGA and ASIC devices |
US8643162B2 (en) * | 2007-11-19 | 2014-02-04 | Raminda Udaya Madurawe | Pads and pin-outs in three dimensional integrated circuits |
US6943415B2 (en) * | 2003-04-08 | 2005-09-13 | Lsi Logic Corporation | Architecture for mask programmable devices |
US7102237B1 (en) | 2003-05-28 | 2006-09-05 | Lightspeed Semiconductor Corporation | ASIC customization with predefined via mask |
US7770144B2 (en) * | 2003-05-28 | 2010-08-03 | Eric Dellinger | Modular array defined by standard cell logic |
US7030651B2 (en) | 2003-12-04 | 2006-04-18 | Viciciv Technology | Programmable structured arrays |
US7002191B2 (en) * | 2003-12-26 | 2006-02-21 | Lsi Logic Corporation | Single layer configurable logic |
US7176713B2 (en) * | 2004-01-05 | 2007-02-13 | Viciciv Technology | Integrated circuits with RAM and ROM fabrication options |
KR100564611B1 (en) * | 2004-02-14 | 2006-03-29 | 삼성전자주식회사 | Damping structure for hard disk drive |
DE102004063926B4 (en) * | 2004-03-24 | 2017-10-19 | Infineon Technologies Ag | Configurable driver cell of a logical cell field |
US7489164B2 (en) * | 2004-05-17 | 2009-02-10 | Raminda Udaya Madurawe | Multi-port memory devices |
US7149142B1 (en) | 2004-05-28 | 2006-12-12 | Virage Logic Corporation | Methods and apparatuses for memory array leakage reduction using internal voltage biasing circuitry |
US7098691B2 (en) * | 2004-07-27 | 2006-08-29 | Easic Corporation | Structured integrated circuit device |
US7463062B2 (en) * | 2004-07-27 | 2008-12-09 | Easic Corporation | Structured integrated circuit device |
AU2005269568A1 (en) * | 2004-07-27 | 2006-02-09 | Easic Corporation | Structured integrated circuit device |
US7334208B1 (en) | 2004-11-09 | 2008-02-19 | Viasic, Inc. | Customization of structured ASIC devices using pre-process extraction of routing information |
US7616036B1 (en) | 2005-09-12 | 2009-11-10 | Virage Logic Corporation | Programmable strobe and clock generator |
US7614024B2 (en) * | 2005-10-06 | 2009-11-03 | Broadcom Corporation | Method to implement metal fill during integrated circuit design and layout |
US7486111B2 (en) * | 2006-03-08 | 2009-02-03 | Tier Logic, Inc. | Programmable logic devices comprising time multiplexed programmable interconnect |
US7542324B1 (en) | 2006-04-17 | 2009-06-02 | Altera Corporation | FPGA equivalent input and output grid muxing on structural ASIC memory |
US7702978B2 (en) * | 2006-04-21 | 2010-04-20 | Altera Corporation | Soft error location and sensitivity detection for programmable devices |
US7692309B2 (en) * | 2007-09-06 | 2010-04-06 | Viasic, Inc. | Configuring structured ASIC fabric using two non-adjacent via layers |
US7635988B2 (en) * | 2007-11-19 | 2009-12-22 | Tier Logic, Inc. | Multi-port thin-film memory devices |
US20090128189A1 (en) * | 2007-11-19 | 2009-05-21 | Raminda Udaya Madurawe | Three dimensional programmable devices |
US7573293B2 (en) * | 2007-12-26 | 2009-08-11 | Tier Logic, Inc. | Programmable logic based latches and shift registers |
US7795913B2 (en) * | 2007-12-26 | 2010-09-14 | Tier Logic | Programmable latch based multiplier |
US7573294B2 (en) * | 2007-12-26 | 2009-08-11 | Tier Logic, Inc. | Programmable logic based latches and shift registers |
US7602213B2 (en) * | 2007-12-26 | 2009-10-13 | Tier Logic, Inc. | Using programmable latch to implement logic |
US7821039B2 (en) * | 2008-06-23 | 2010-10-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Layout architecture for improving circuit performance |
US8230375B2 (en) | 2008-09-14 | 2012-07-24 | Raminda Udaya Madurawe | Automated metal pattern generation for integrated circuits |
US8159266B1 (en) | 2010-11-16 | 2012-04-17 | Raminda Udaya Madurawe | Metal configurable integrated circuits |
US8159268B1 (en) | 2010-11-16 | 2012-04-17 | Raminda Udaya Madurawe | Interconnect structures for metal configurable integrated circuits |
US8159265B1 (en) | 2010-11-16 | 2012-04-17 | Raminda Udaya Madurawe | Memory for metal configurable integrated circuits |
US8533641B2 (en) * | 2011-10-07 | 2013-09-10 | Baysand Inc. | Gate array architecture with multiple programmable regions |
US9479456B2 (en) | 2012-11-02 | 2016-10-25 | Altera Corporation | Programmable logic device with integrated network-on-chip |
US9837398B1 (en) * | 2016-11-23 | 2017-12-05 | Advanced Micro Devices, Inc. | Metal track cutting in standard cell layouts |
US11347925B2 (en) | 2017-05-01 | 2022-05-31 | Advanced Micro Devices, Inc. | Power grid architecture and optimization with EUV lithography |
US11211330B2 (en) | 2017-05-01 | 2021-12-28 | Advanced Micro Devices, Inc. | Standard cell layout architectures and drawing styles for 5nm and beyond |
US10878158B2 (en) | 2018-07-16 | 2020-12-29 | Taiwan Semiconductor Manufacturing Company, Ltd. | Semiconductor device including cell region having more similar cell densities in different height rows, and method and system for generating layout diagram of same |
US10796061B1 (en) | 2019-08-29 | 2020-10-06 | Advanced Micro Devices, Inc. | Standard cell and power grid architectures with EUV lithography |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3408747A1 (en) * | 1983-03-11 | 1984-09-27 | Rca Corp., New York, N.Y. | UNIVERSALLY APPLICABLE ARRANGEMENT OF COMPONENTS FOR VARIABLE CIRCUIT |
EP0408060A2 (en) * | 1989-07-14 | 1991-01-16 | Hitachi, Ltd. | Semiconductor integrated circuit device and logic correcting method of the same |
EP0681329A2 (en) * | 1994-05-01 | 1995-11-08 | Quick Technologies Ltd. | A customizable logic array device |
Family Cites Families (35)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE279387C (en) | ||||
US4197555A (en) | 1975-12-29 | 1980-04-08 | Fujitsu Limited | Semiconductor device |
US4161662A (en) | 1976-01-22 | 1979-07-17 | Motorola, Inc. | Standardized digital logic chip |
US4870302A (en) | 1984-03-12 | 1989-09-26 | Xilinx, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
USRE34363E (en) | 1984-03-12 | 1993-08-31 | Xilinx, Inc. | Configurable electrical circuit having configurable logic elements and configurable interconnects |
US4642487A (en) | 1984-09-26 | 1987-02-10 | Xilinx, Inc. | Special interconnect for configurable logic array |
US4682201A (en) | 1984-10-19 | 1987-07-21 | California Devices, Inc. | Gate array cell |
US5545904A (en) | 1986-01-17 | 1996-08-13 | Quick Technologies Ltd. | Personalizable gate array devices |
IL86162A (en) | 1988-04-25 | 1991-11-21 | Zvi Orbach | Customizable semiconductor devices |
US5679967A (en) * | 1985-01-20 | 1997-10-21 | Chip Express (Israel) Ltd. | Customizable three metal layer gate array devices |
JPS61241964A (en) * | 1985-04-19 | 1986-10-28 | Hitachi Ltd | Semiconductor device |
US5172014A (en) | 1986-09-19 | 1992-12-15 | Actel Corporation | Programmable interconnect architecture |
US4758745B1 (en) | 1986-09-19 | 1994-11-15 | Actel Corp | User programmable integrated circuit interconnect architecture and test method |
JPS63102342A (en) | 1986-10-20 | 1988-05-07 | Mitsubishi Electric Corp | Wiring structure of semiconductor integrated circuit device |
US4745084A (en) | 1986-11-12 | 1988-05-17 | Vlsi Technology, Inc. | Method of making a customized semiconductor integrated device |
IL82113A (en) | 1987-04-05 | 1992-08-18 | Zvi Orbach | Fabrication of customized integrated circuits |
US4843034A (en) | 1987-06-12 | 1989-06-27 | Massachusetts Institute Of Technology | Fabrication of interlayer conductive paths in integrated circuits |
US4851892A (en) * | 1987-09-08 | 1989-07-25 | Motorola, Inc. | Standard cell array having fake gate for isolating devices from supply voltages |
US5023701A (en) | 1988-03-31 | 1991-06-11 | Advanced Micro Devices, Inc. | Gate array structure and process to allow optioning at second metal mask only |
US5084404A (en) | 1988-03-31 | 1992-01-28 | Advanced Micro Devices | Gate array structure and process to allow optioning at second metal mask only |
JPH01266742A (en) | 1988-04-18 | 1989-10-24 | Seiko Epson Corp | Master slice semiconductor integrated circuit cell |
EP0650196A2 (en) | 1988-04-22 | 1995-04-26 | Fujitsu Limited | Semiconductor integrated circuit device and method of producing the same using master slice approach |
US5016080A (en) | 1988-10-07 | 1991-05-14 | Exar Corporation | Programmable die size continuous array |
DE69103915T2 (en) | 1990-01-25 | 1995-05-11 | Applied Materials Inc | Electrostatic clamp and method. |
JPH03283663A (en) | 1990-03-30 | 1991-12-13 | Nec Corp | Manufacture of semiconductor integrated circuit device |
US5073729A (en) | 1990-06-22 | 1991-12-17 | Actel Corporation | Segmented routing architecture |
JPH04152567A (en) | 1990-10-16 | 1992-05-26 | Mitsubishi Electric Corp | Master slice lsi |
JPH05136125A (en) * | 1991-11-14 | 1993-06-01 | Hitachi Ltd | Clock wiring and semiconductor integrated circuit device having clock wiring |
US5206184A (en) | 1991-11-15 | 1993-04-27 | Sequoia Semiconductor, Inc. | Method of making single layer personalization |
US5343058A (en) | 1991-11-18 | 1994-08-30 | Vlsi Technology, Inc. | Gate array bases with flexible routing |
US5404033A (en) | 1992-08-20 | 1995-04-04 | Swift Microelectronics Corporation | Application specific integrated circuit and placement and routing software with non-customizable first metal layer and vias and customizable second metal grid pattern |
JP3289736B2 (en) | 1992-08-26 | 2002-06-10 | 直 柴田 | Semiconductor integrated circuit |
US5338970A (en) * | 1993-03-24 | 1994-08-16 | Intergraph Corporation | Multi-layered integrated circuit package with improved high frequency performance |
JP3488735B2 (en) * | 1994-03-03 | 2004-01-19 | 三菱電機株式会社 | Semiconductor device |
IL111708A (en) | 1994-11-21 | 1998-03-10 | Chip Express Israel Ltd | Mapping of gate arrays |
-
1997
- 1997-11-10 US US08/966,946 patent/US6242767B1/en not_active Expired - Lifetime
-
1998
- 1998-10-29 WO PCT/US1998/022985 patent/WO1999025023A1/en active Application Filing
- 1998-10-29 EP EP98957421A patent/EP1029355A1/en not_active Withdrawn
- 1998-10-29 JP JP2000519925A patent/JP4562908B2/en not_active Expired - Lifetime
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3408747A1 (en) * | 1983-03-11 | 1984-09-27 | Rca Corp., New York, N.Y. | UNIVERSALLY APPLICABLE ARRANGEMENT OF COMPONENTS FOR VARIABLE CIRCUIT |
EP0408060A2 (en) * | 1989-07-14 | 1991-01-16 | Hitachi, Ltd. | Semiconductor integrated circuit device and logic correcting method of the same |
EP0681329A2 (en) * | 1994-05-01 | 1995-11-08 | Quick Technologies Ltd. | A customizable logic array device |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7047514B2 (en) | 2001-04-04 | 2006-05-16 | Nec Electronics Corporation | Semi-custom-made semiconductor integrated circuit device, method for customization and method for redesign |
US7523436B2 (en) | 2001-04-04 | 2009-04-21 | Nec Electronics Corporation | Semi-custom-made semiconductor integrated circuit device, method for customization and method for redesign |
US6853019B2 (en) | 2002-05-17 | 2005-02-08 | Nec Electronics Corporation | Semiconductor device and manufacturing method for the same |
Also Published As
Publication number | Publication date |
---|---|
US6242767B1 (en) | 2001-06-05 |
WO1999025023B1 (en) | 1999-07-01 |
JP4562908B2 (en) | 2010-10-13 |
EP1029355A1 (en) | 2000-08-23 |
JP2001523048A (en) | 2001-11-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US6242767B1 (en) | Asic routing architecture | |
US6613611B1 (en) | ASIC routing architecture with variable number of custom masks | |
US6838713B1 (en) | Dual-height cell with variable width power rail architecture | |
EP3229270A1 (en) | Integrated circuit power distribution network | |
US5742086A (en) | Hexagonal DRAM array | |
US4612618A (en) | Hierarchical, computerized design of integrated circuits | |
US5889329A (en) | Tri-directional interconnect architecture for SRAM | |
US6404226B1 (en) | Integrated circuit with standard cell logic and spare gates | |
US5811863A (en) | Transistors having dynamically adjustable characteristics | |
US5872380A (en) | Hexagonal sense cell architecture | |
EP0203025B1 (en) | Gate array with reduced isolation | |
EP0683524B1 (en) | Base cell for BiCMOS and CMOS gate arrays | |
CA1206624A (en) | Variable geometry automated universal array | |
EP0469728A1 (en) | Programmable interconnect architecture | |
US4851892A (en) | Standard cell array having fake gate for isolating devices from supply voltages | |
US6306744B1 (en) | Filter capacitor construction | |
US5796299A (en) | Integrated circuit array including I/O cells and power supply cells | |
US6885043B2 (en) | ASIC routing architecture | |
EP1548538A2 (en) | Integrated circuit, and design and manufacture thereof | |
US5270592A (en) | Clock supply circuit layout in a circuit area | |
US5206184A (en) | Method of making single layer personalization | |
JPH09293844A (en) | High density gate array cell structure and manufacture thereof | |
US11677401B2 (en) | 3D integrated count | |
EP0135019B1 (en) | Interconnection of elements on integrated cirrcuit substrate | |
US5834821A (en) | Triangular semiconductor "AND" gate device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
AK | Designated states |
Kind code of ref document: A1 Designated state(s): JP |
|
AL | Designated countries for regional patents |
Kind code of ref document: A1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
AK | Designated states |
Kind code of ref document: B1 Designated state(s): JP |
|
AL | Designated countries for regional patents |
Kind code of ref document: B1 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
ENP | Entry into the national phase |
Ref country code: JP Ref document number: 2000 519925 Kind code of ref document: A Format of ref document f/p: F |
|
WWE | Wipo information: entry into national phase |
Ref document number: 1998957421 Country of ref document: EP |
|
WWP | Wipo information: published in national office |
Ref document number: 1998957421 Country of ref document: EP |