WO1999026292A2 - Semiconductor device of sic with insulating layer and a refractory metal nitride layer - Google Patents
Semiconductor device of sic with insulating layer and a refractory metal nitride layer Download PDFInfo
- Publication number
- WO1999026292A2 WO1999026292A2 PCT/SE1998/002049 SE9802049W WO9926292A2 WO 1999026292 A2 WO1999026292 A2 WO 1999026292A2 SE 9802049 W SE9802049 W SE 9802049W WO 9926292 A2 WO9926292 A2 WO 9926292A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- layer
- sic
- semiconductor device
- sub
- metal nitride
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 150000004767 nitrides Chemical class 0.000 title claims abstract description 22
- 239000003870 refractory metal Substances 0.000 title claims abstract description 19
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims abstract description 22
- 229910052681 coesite Inorganic materials 0.000 claims abstract description 20
- 229910052906 cristobalite Inorganic materials 0.000 claims abstract description 20
- 229910052682 stishovite Inorganic materials 0.000 claims abstract description 20
- 229910052905 tridymite Inorganic materials 0.000 claims abstract description 20
- 239000002184 metal Substances 0.000 claims abstract description 13
- 229910052581 Si3N4 Inorganic materials 0.000 claims abstract description 10
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 15
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 238000006243 chemical reaction Methods 0.000 description 9
- 108091006146 Channels Proteins 0.000 description 8
- 230000007246 mechanism Effects 0.000 description 6
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 238000009792 diffusion process Methods 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 108010075750 P-Type Calcium Channels Proteins 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 238000000137 annealing Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 230000015556 catabolic process Effects 0.000 description 1
- 238000006731 degradation reaction Methods 0.000 description 1
- 230000001627 detrimental effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000002474 experimental method Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 230000007774 longterm Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 230000009257 reactivity Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
- H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
- H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/16—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only elements of Group IV of the Periodic System
- H01L29/1608—Silicon carbide
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
- H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
- H01L29/51—Insulating materials associated therewith
- H01L29/518—Insulating materials associated therewith the insulating material containing nitrogen, e.g. nitride, oxynitride, nitrogen-doped material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Definitions
- the present invention relates to a semiconductor device comprising at least one semiconductor layer of SiC and a layer of a refractory metal nitride separated by an insulating layer being at least next to the SiC layer of Si0 2 .
- SiC silicon carbide
- SiC has a high thermal stability, so that it will have a stable function at much higher temperatures than Si, namely well up to 1000K.
- semiconductor device of SiC it is necessary to anneal the layer next to a contact at comparatively high temperatures, namely at least 800 °C when this layer has a very high doping concentration and otherwise even higher, for in this way forming a high density of interface defects next to the contact layer and by that an ohmic contact.
- Refractory metal is here defined as a metal having a low reactivity at high temperatures.
- refractory metal nitrides such as oN, TaN and particularly TiN would be well suited for forming such metal layers, especially for forming the gate contact of a gate controlled semiconductor device of SiC, and this particular application will hereinafter be discussed in order to illuminate but not in any way restrict the invention and the problems to be solved thereby.
- the object of the present invention is to provide a semiconductor device of the type defined in the introduction being able to operate at the high temperatures possible by the properties of SiC itself and enabling an ohmic contact anneal at the high temperatures needed for a satisfying result without any introduction of instability mechanisms due to reactions of the refractory metal nitride with other elements.
- This object is obtained according to the invention by making the insulating layer of such a device of two sub layers, namely a first sub layer of Si0 2 next to the SiC layer and a second sub layer of Si 3 N 4 located between the first sub layer and the metal nitride layer.
- the insulating layer of Si 3 N 4 between the Si0 2 layer and the refractory metal nitride layer will efficiently prevent the interface reaction of Si0 2 with the metal nitride. This has especially been demonstrated for TiN as refractory metal nitride, and it has been found that ohmic contact anneal may with such an additional layer as the second sub layer be carried out up to 800°C without introducing any instability mechanisms due to interface reactions.
- this additional layer is made of a material having one element, nitrogen, in common with the metal nitride located on one side thereof and the other element, Si, in common with the Si0 2 layer located on the other side thereof, has turned out to limit possible reactions at the interfaces between said second sub layer and the first sub layer on one hand and the second sub layer and the refractory metal nitride layer on the other.
- said second sub layer of Si 3 N 4 is thin with respect to the first sub layer of Si0 2 . It has turned out that a thin Si 3 N 4 layer will be enough for obtaining the results aimed at, namely to prevent interface reactions contributing to instability mechanisms from occurring, and such a thin additional layer is very advantageous in gate controlled devices when said refractory metal nitride is used as a gate contact, since it will not contribute to the capacitance of the device or to the threshold voltage to be applied on the gate contact for forming a conducting inversion channel at the interface between the Si0 2 layer and the SiC layer and by that not influencing the charge mobility of such a channel.
- the thickness of the second sub layer is less than a third of the thickness of the first sub layer. Such a thickness will be enough for preventing said interface reactions resulting in instability mechanisms at the high temperatures in question.
- said metal nitride layer is made of TiN.
- TiN is very suitable as a refractory metal for semiconductor devices of SiC, in which it is desired to utilise the properties of SiC with respect to the stability at high temperatures, and it may now also be utilised without any adverse effects of the high temperatures upon the stability of the device in the region of said insulating layer.
- the semiconductor device is gate-controlled and the layer of a refractory metal nitride forms a gate contact of the device adapted to, upon applying a certain potential thereon, form a conducting inversion channel in said SiC layer at the interface between the SiC layer and the first sub layer of Si0 2 .
- said semiconductor device is a MOSFET and an IGBT, respectively.
- the MOS structure of such devices will in this way have a stable gate metallization allowing stable operation at high temperatures. Further advantages and advantageous characteristics of the invention appear from the description following below.
- Fig 1 is a very schematic cross-sectioned view of a part of a semiconductor device according to a preferred embodiment of the invention.
- Fig 2 is a sectioned view in a smaller scale of a semiconductor device according to a preferred embodiment of the invention in the form of a MOSFET.
- FIG. 1 A portion of a MOSFET made of SiC according to a preferred embodiment of the invention is illustrated in Fig 1. How- ever, it should be noted that the relative dimensions of the layers and the regions of this portion of this device and this device shown in Fig 2 have only been chosen for the sake of clearness of the drawing.
- This device comprises a drain 1, a highly doped n-type substrate layer 2 on top thereof and a n-type low-doped drift layer 3 on top of the substrate layer.
- the device also has a low-doped p-type channel region layer 4 and a highly doped n-type source region layer 5 preferably obtained by ion implantation and diffusion into the layer 3.
- a source contact 6 of metal is applied on the source region layer 5.
- the layers 2-5 are made of SiC.
- the device also has an insulating layer 7 on top of the channel region layer 4 and a gate contact 8 located on top of the insulating layer 7 and extending laterally over at least the entire width of the channel region layer 4 so as to create a conductxng inversion channel at the interface between the channel region layer 4 and the insulating layer 7 for electron transport between the source region layer 5 and the drift layer 3 upon applying a positive voltage of a sufficient level on the gate 8.
- this device is annealed at a comparatively high temperature, at least in the range of 800°C, for forming a good ohmic contact between the source region layer 5 and the source metal 6 by forming a high density of interface defects therethrough.
- the gate contact is here made of a refractory metal nitride, namely TiN. It is illustrated in Fig 1 how the insulating layer 7 is made of two sub layers, namely a first sub layer
- This layer 10 of Si 3 N 4 located on top of the first sub layer between this and the gate layer 8.
- This layer 10 of Si 3 N 4 is compara- tively thin, so that it will not contribute to the capacitance or to the threshold of the MOSFET so designed. However, it will prevent any interface reaction of Si0 2 with TiN to form Ti0 2 that has been identified as a contributing instability mechanism in such devices having the entire insulating layer made of Si0 2 in operation at temperatures above 600°C and through high temperature ohmic contact anneal .
- this structure will withstand anneal- ing temperatures at least as high as 800°C without any such detrimental interface reactions. However, at considerably higher temperatures an intermixing of Si 3 N 4 and TiN may occur, so that Ti may then react with Si0 2 for forming Ti0 2 and introducing instabilities.
- TiN may have different phases, such as Ti 2 N, Ti 3 N 4 etc, and the Ti-richer phases will fail at a lower temperature than the stoichiometric phase TiN.
- the invention also comprises bipolar semiconductor devices, such as an IGBT. It is also conceivable to have the layers oppositely doped, accordingly n instead of p and conversely, for obtaining a hole conduc- tion.
- the invention is applicable to any semiconductor device having at least one layer of SiC in which a metal is deposited on an insulating layer located on top of the SiC layer.
- the number of layers mentioned in the claims is a minimum number, and it is within the scope of the invention to arrange further layers in the devices or dividing any layer into several layers by selective doping of different regions thereof.
Abstract
A semiconductor device comprises at least one semiconductor layer (4) of SiC and a layer (8) of a refractory metal nitride separated by an insulating layer (7) being at least next to the SiC layer of SiO2. The insulating layer comprises two sub layers, namely a first sub layer (9) of SiO2 next to the SiC layer and a second sub layer (10) of Si3N4 located between the first sub layer and the metal nitride layer.
Description
SEMICONDUCTOR DEVICE OF SiC WITH INSULATING LAYER AND A REFRACTORY METAL NITRIDE LAYER
TECHNICAL FIELD OF THE INVENTION AND PRIOR ART
The present invention relates to a semiconductor device comprising at least one semiconductor layer of SiC and a layer of a refractory metal nitride separated by an insulating layer being at least next to the SiC layer of Si02.
It is well known that semiconductor devices fabricated from SiC are in principle able to operate at very high temperatures, since SiC has a high thermal stability, so that it will have a stable function at much higher temperatures than Si, namely well up to 1000K. In addition, for semiconductor device of SiC it is necessary to anneal the layer next to a contact at comparatively high temperatures, namely at least 800 °C when this layer has a very high doping concentration and otherwise even higher, for in this way forming a high density of interface defects next to the contact layer and by that an ohmic contact. The need of such a high temperature anneal requires the use of a refractory metal in devices where a metal layer has to be placed on the SiC layer with an insulating layer therebetween, such as a gate con- tact in gate controlled devices as MOSFETs and IGBTs or field rings for reducing the electric field at the edges of a semiconductor device. "Refractory metal" is here defined as a metal having a low reactivity at high temperatures.
It has been found that refractory metal nitrides, such as oN, TaN and particularly TiN would be well suited for
forming such metal layers, especially for forming the gate contact of a gate controlled semiconductor device of SiC, and this particular application will hereinafter be discussed in order to illuminate but not in any way restrict the invention and the problems to be solved thereby.
As already mentioned, it has previously been recognised that a possible gate contact could be formed using deposited TiN, and this has been disclosed in for instance EP 0 697 714. Besides the fact that TiN is a refractory metal, it is also an efficient diffusion barrier which should limit extrinsic degradation. However, experiments have shown that although a stable gate contact may be formed using TiN on Si02, this appears only be stable up to 600°C. This is for the reason mentioned above not stable for the high temperatures necessary for ohmic contact anneals and unfortunately neither sufficiently stable for long term high temperature operation of such a semiconductor device. This is due to the fact that Ti is very reactive with respect to oxygen, and it has been identified that there will be an interface reaction of Si02 with TiN to form Ti02, which has been identified as a contributing instability mechanism. This problem may also be there for the other refractory metal nitrides that may be considered.
SUMMARY OF THE INVENTION
The object of the present invention is to provide a semiconductor device of the type defined in the introduction being able to operate at the high temperatures possible by the properties of SiC itself and enabling an ohmic contact anneal at the high temperatures needed for a satisfying result without any introduction of instability mechanisms due to reactions of the refractory metal nitride with other elements.
This object is obtained according to the invention by making the insulating layer of such a device of two sub layers, namely a first sub layer of Si02 next to the SiC layer and a second sub layer of Si3N4 located between the first sub layer and the metal nitride layer.
The insulating layer of Si3N4 between the Si02 layer and the refractory metal nitride layer will efficiently prevent the interface reaction of Si02 with the metal nitride. This has especially been demonstrated for TiN as refractory metal nitride, and it has been found that ohmic contact anneal may with such an additional layer as the second sub layer be carried out up to 800°C without introducing any instability mechanisms due to interface reactions. The fact that this additional layer is made of a material having one element, nitrogen, in common with the metal nitride located on one side thereof and the other element, Si, in common with the Si02 layer located on the other side thereof, has turned out to limit possible reactions at the interfaces between said second sub layer and the first sub layer on one hand and the second sub layer and the refractory metal nitride layer on the other.
According to a preferred embodiment of the invention said second sub layer of Si3N4 is thin with respect to the first sub layer of Si02. It has turned out that a thin Si3N4 layer will be enough for obtaining the results aimed at, namely to prevent interface reactions contributing to instability mechanisms from occurring, and such a thin additional layer is very advantageous in gate controlled devices when said refractory metal nitride is used as a gate contact, since it will not contribute to the capacitance of the device or to the threshold voltage to be applied on the gate contact for forming a conducting inversion channel at the interface between the Si02 layer and the SiC layer and by that not influencing the charge mobility of such a channel.
According to another preferred embodiment of the invention the thickness of the second sub layer is less than a third of the thickness of the first sub layer. Such a thickness will be enough for preventing said interface reactions resulting in instability mechanisms at the high temperatures in question.
According to another preferred embodiment of the invention said metal nitride layer is made of TiN. As already mentioned, it has turned out that TiN is very suitable as a refractory metal for semiconductor devices of SiC, in which it is desired to utilise the properties of SiC with respect to the stability at high temperatures, and it may now also be utilised without any adverse effects of the high temperatures upon the stability of the device in the region of said insulating layer.
According to another preferred embodiment of the invention the semiconductor device is gate-controlled and the layer of a refractory metal nitride forms a gate contact of the device adapted to, upon applying a certain potential thereon, form a conducting inversion channel in said SiC layer at the interface between the SiC layer and the first sub layer of Si02. This is a very preferred embodiment of the invention, since the advantages of better operation stability and a higher mobility in operation at high temperatures compared to prior art gate-controlled semiconductor devices are significant.
According to other preferred embodiments of the invention said semiconductor device is a MOSFET and an IGBT, respectively. The MOS structure of such devices will in this way have a stable gate metallization allowing stable operation at high temperatures.
Further advantages and advantageous characteristics of the invention appear from the description following below.
BRIEF DESCRIPTION OF THE DRAWING
With reference to the appended drawing, below follows a specific description of a preferred embodiment of the invention cited as an example.
In the drawing:
Fig 1 is a very schematic cross-sectioned view of a part of a semiconductor device according to a preferred embodiment of the invention, and
Fig 2 is a sectioned view in a smaller scale of a semiconductor device according to a preferred embodiment of the invention in the form of a MOSFET.
DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT OF THE INVENTION
A portion of a MOSFET made of SiC according to a preferred embodiment of the invention is illustrated in Fig 1. How- ever, it should be noted that the relative dimensions of the layers and the regions of this portion of this device and this device shown in Fig 2 have only been chosen for the sake of clearness of the drawing. This device comprises a drain 1, a highly doped n-type substrate layer 2 on top thereof and a n-type low-doped drift layer 3 on top of the substrate layer. The device also has a low-doped p-type channel region layer 4 and a highly doped n-type source region layer 5 preferably obtained by ion implantation and diffusion into the layer 3. A source contact 6 of metal is applied on the source region layer 5. The layers 2-5 are made of SiC.
The device also has an insulating layer 7 on top of the channel region layer 4 and a gate contact 8 located on top of the insulating layer 7 and extending laterally over at least the entire width of the channel region layer 4 so as to create a conductxng inversion channel at the interface between the channel region layer 4 and the insulating layer 7 for electron transport between the source region layer 5 and the drift layer 3 upon applying a positive voltage of a sufficient level on the gate 8.
It is important that this device is annealed at a comparatively high temperature, at least in the range of 800°C, for forming a good ohmic contact between the source region layer 5 and the source metal 6 by forming a high density of interface defects therethrough.
The gate contact is here made of a refractory metal nitride, namely TiN. It is illustrated in Fig 1 how the insulating layer 7 is made of two sub layers, namely a first sub layer
9 of Si02 next to the channel region layer 4 formed by thermal oxidation of the SiC layer, and a second sub layer
10 of Si3N4 located on top of the first sub layer between this and the gate layer 8. This layer 10 of Si3N4 is compara- tively thin, so that it will not contribute to the capacitance or to the threshold of the MOSFET so designed. However, it will prevent any interface reaction of Si02 with TiN to form Ti02 that has been identified as a contributing instability mechanism in such devices having the entire insulating layer made of Si02 in operation at temperatures above 600°C and through high temperature ohmic contact anneal .
It has been found that this structure will withstand anneal- ing temperatures at least as high as 800°C without any such detrimental interface reactions. However, at considerably
higher temperatures an intermixing of Si3N4 and TiN may occur, so that Ti may then react with Si02 for forming Ti02 and introducing instabilities.
It is pointed out that when we speak about TiN we do also include the fact that TiN may have different phases, such as Ti2N, Ti3N4 etc, and the Ti-richer phases will fail at a lower temperature than the stoichiometric phase TiN.
The invention is not in any way restricted to the preferred embodiment described above, but many possibilities to modifications thereof would be apparent to a man with ordinary skill in the art without departing from the basic idea of the invention as defined in the appended claims.
As already stated, the invention also comprises bipolar semiconductor devices, such as an IGBT. It is also conceivable to have the layers oppositely doped, accordingly n instead of p and conversely, for obtaining a hole conduc- tion.
The invention is applicable to any semiconductor device having at least one layer of SiC in which a metal is deposited on an insulating layer located on top of the SiC layer.
The number of layers mentioned in the claims is a minimum number, and it is within the scope of the invention to arrange further layers in the devices or dividing any layer into several layers by selective doping of different regions thereof.
Claims
1. A semiconductor device comprising at least one semiconductor layer ( 4 ) of SiC and a layer ( 8 ) of a refractory metal nitride separated by an insulating layer ( 7 ) being at least next to the SiC layer of Si02, characterized in that the insulating layer comprises two sub layers, namely a first sub layer ( 9 ) of Si02 next to the SiC layer and a second sub layer ( 10 ) of Si3N4 located between the first sub layer and the metal nitride layer.
2. A semiconductor device according to claim 1, characterized in that said second sub layer (10) of Si3N4 is thin with respect to the first sub layer (9) of Si02.
3. A semiconductor device according to claim 1 or 2, characterized in that the thickness of the second sub layer (10) is less than a third of the thickness of the first sub layer (9).
4. A semiconductor device according to any of claims 1-3, characterized in that said metal nitride layer ( 8 ) is made of TiN.
5. A semiconductor device according to any of claims 1-4, characterized in that it is gate-controlled and the layer ( 8 ) of a refractory metal nitride forms a gate contact of the device adapted to, upon applying a certain potential thereon, form a conducting inversion channel in said SiC layer (4) at the interface between the SiC layer and the first sub layer (9) of Si02.
6. A semiconductor device according to claim 5, characterized in that it is a MOSFET.
7. A semiconductor device according to claim 5 , characterized in that it is an IGBT.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| EP98956065A EP1029357A2 (en) | 1997-11-13 | 1998-11-13 | Semiconductor device of sic with insulating layer and a refractory metal nitride layer |
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE9704150-3 | 1997-11-13 | ||
| SE9704150A SE9704150D0 (en) | 1997-11-13 | 1997-11-13 | Semiconductor device of SiC with insulating layer a refractory metal nitride layer |
| US08/972,253 US6025608A (en) | 1997-11-13 | 1997-11-18 | Semiconductor device of SiC with insulating layer and a refractory metal nitride layer |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| WO1999026292A2 true WO1999026292A2 (en) | 1999-05-27 |
| WO1999026292A3 WO1999026292A3 (en) | 1999-07-29 |
Family
ID=26663126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| PCT/SE1998/002049 WO1999026292A2 (en) | 1997-11-13 | 1998-11-13 | Semiconductor device of sic with insulating layer and a refractory metal nitride layer |
Country Status (3)
| Country | Link |
|---|---|
| US (1) | US6025608A (en) |
| SE (1) | SE9704150D0 (en) |
| WO (1) | WO1999026292A2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001033704A1 (en) * | 1999-11-02 | 2001-05-10 | Abb Research Limited | HIGH VOLTAGE APPARATUS INCLUDING CONVERTER WITH SiC SEMICONDUCTORS |
| US8821961B2 (en) | 2004-10-13 | 2014-09-02 | Commissariat A L'energie Atomique | MgO-based coating for electrically insulating semiconductive substrates and production method thereof |
Families Citing this family (43)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6246076B1 (en) * | 1998-08-28 | 2001-06-12 | Cree, Inc. | Layered dielectric on silicon carbide semiconductor structures |
| US6972436B2 (en) * | 1998-08-28 | 2005-12-06 | Cree, Inc. | High voltage, high temperature capacitor and interconnection structures |
| US6767843B2 (en) | 2000-10-03 | 2004-07-27 | Cree, Inc. | Method of N2O growth of an oxide layer on a silicon carbide layer |
| US6610366B2 (en) | 2000-10-03 | 2003-08-26 | Cree, Inc. | Method of N2O annealing an oxide layer on a silicon carbide layer |
| US7067176B2 (en) | 2000-10-03 | 2006-06-27 | Cree, Inc. | Method of fabricating an oxide layer on a silicon carbide layer utilizing an anneal in a hydrogen environment |
| US6956238B2 (en) | 2000-10-03 | 2005-10-18 | Cree, Inc. | Silicon carbide power metal-oxide semiconductor field effect transistors having a shorting channel and methods of fabricating silicon carbide metal-oxide semiconductor field effect transistors having a shorting channel |
| US6528373B2 (en) * | 2001-02-12 | 2003-03-04 | Cree, Inc. | Layered dielectric on silicon carbide semiconductor structures |
| CN1599961A (en) * | 2001-11-30 | 2005-03-23 | 松下电器产业株式会社 | Semiconductor device and production method therefor |
| US7022378B2 (en) * | 2002-08-30 | 2006-04-04 | Cree, Inc. | Nitrogen passivation of interface states in SiO2/SiC structures |
| US7221010B2 (en) | 2002-12-20 | 2007-05-22 | Cree, Inc. | Vertical JFET limited silicon carbide power metal-oxide semiconductor field effect transistors |
| US6979863B2 (en) * | 2003-04-24 | 2005-12-27 | Cree, Inc. | Silicon carbide MOSFETs with integrated antiparallel junction barrier Schottky free wheeling diodes and methods of fabricating the same |
| US7074643B2 (en) * | 2003-04-24 | 2006-07-11 | Cree, Inc. | Silicon carbide power devices with self-aligned source and well regions and methods of fabricating same |
| US7118970B2 (en) * | 2004-06-22 | 2006-10-10 | Cree, Inc. | Methods of fabricating silicon carbide devices with hybrid well regions |
| US7414268B2 (en) | 2005-05-18 | 2008-08-19 | Cree, Inc. | High voltage silicon carbide MOS-bipolar devices having bi-directional blocking capabilities |
| US20060261346A1 (en) * | 2005-05-18 | 2006-11-23 | Sei-Hyung Ryu | High voltage silicon carbide devices having bi-directional blocking capabilities and methods of fabricating the same |
| US7615801B2 (en) * | 2005-05-18 | 2009-11-10 | Cree, Inc. | High voltage silicon carbide devices having bi-directional blocking capabilities |
| US7391057B2 (en) * | 2005-05-18 | 2008-06-24 | Cree, Inc. | High voltage silicon carbide devices having bi-directional blocking capabilities |
| US7528040B2 (en) | 2005-05-24 | 2009-05-05 | Cree, Inc. | Methods of fabricating silicon carbide devices having smooth channels |
| US7727904B2 (en) * | 2005-09-16 | 2010-06-01 | Cree, Inc. | Methods of forming SiC MOSFETs with high inversion layer mobility |
| US8432012B2 (en) | 2006-08-01 | 2013-04-30 | Cree, Inc. | Semiconductor devices including schottky diodes having overlapping doped regions and methods of fabricating same |
| US7728402B2 (en) * | 2006-08-01 | 2010-06-01 | Cree, Inc. | Semiconductor devices including schottky diodes with controlled breakdown |
| US8710510B2 (en) * | 2006-08-17 | 2014-04-29 | Cree, Inc. | High power insulated gate bipolar transistors |
| US8835987B2 (en) | 2007-02-27 | 2014-09-16 | Cree, Inc. | Insulated gate bipolar transistors including current suppressing layers |
| US8232558B2 (en) | 2008-05-21 | 2012-07-31 | Cree, Inc. | Junction barrier Schottky diodes with current surge capability |
| US8288220B2 (en) * | 2009-03-27 | 2012-10-16 | Cree, Inc. | Methods of forming semiconductor devices including epitaxial layers and related structures |
| US8294507B2 (en) | 2009-05-08 | 2012-10-23 | Cree, Inc. | Wide bandgap bipolar turn-off thyristor having non-negative temperature coefficient and related control circuits |
| US8629509B2 (en) * | 2009-06-02 | 2014-01-14 | Cree, Inc. | High voltage insulated gate bipolar transistors with minority carrier diverter |
| US8193848B2 (en) | 2009-06-02 | 2012-06-05 | Cree, Inc. | Power switching devices having controllable surge current capabilities |
| US8541787B2 (en) * | 2009-07-15 | 2013-09-24 | Cree, Inc. | High breakdown voltage wide band-gap MOS-gated bipolar junction transistors with avalanche capability |
| US8354690B2 (en) | 2009-08-31 | 2013-01-15 | Cree, Inc. | Solid-state pinch off thyristor circuits |
| US9117739B2 (en) | 2010-03-08 | 2015-08-25 | Cree, Inc. | Semiconductor devices with heterojunction barrier regions and methods of fabricating same |
| US8415671B2 (en) | 2010-04-16 | 2013-04-09 | Cree, Inc. | Wide band-gap MOSFETs having a heterojunction under gate trenches thereof and related methods of forming such devices |
| US9029945B2 (en) | 2011-05-06 | 2015-05-12 | Cree, Inc. | Field effect transistor devices with low source resistance |
| US9142662B2 (en) | 2011-05-06 | 2015-09-22 | Cree, Inc. | Field effect transistor devices with low source resistance |
| US9984894B2 (en) | 2011-08-03 | 2018-05-29 | Cree, Inc. | Forming SiC MOSFETs with high channel mobility by treating the oxide interface with cesium ions |
| US9640617B2 (en) | 2011-09-11 | 2017-05-02 | Cree, Inc. | High performance power module |
| US8664665B2 (en) | 2011-09-11 | 2014-03-04 | Cree, Inc. | Schottky diode employing recesses for elements of junction barrier array |
| US9373617B2 (en) | 2011-09-11 | 2016-06-21 | Cree, Inc. | High current, low switching loss SiC power module |
| US8618582B2 (en) | 2011-09-11 | 2013-12-31 | Cree, Inc. | Edge termination structure employing recesses for edge termination elements |
| US8680587B2 (en) | 2011-09-11 | 2014-03-25 | Cree, Inc. | Schottky diode |
| JP2014531752A (en) | 2011-09-11 | 2014-11-27 | クリー インコーポレイテッドＣｒｅｅ Ｉｎｃ． | High current density power module with transistors having improved layout |
| US20150255362A1 (en) | 2014-03-07 | 2015-09-10 | Infineon Technologies Ag | Semiconductor Device with a Passivation Layer and Method for Producing Thereof |
| US11238340B1 (en) * | 2016-12-21 | 2022-02-01 | Facebook Technologies, Llc | Predictive eyetracking using recurrent neural networks |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4935804A (en) * | 1984-03-19 | 1990-06-19 | Fujitsu Limited | Semiconductor device |
| WO1995022838A1 (en) * | 1994-02-18 | 1995-08-24 | Telefonaktiebolaget Lm Ericsson | Electromigration resistant metallization structures for microcircuit interconnections with rf-reactively sputtered titanium tungsten and gold |
| US5597744A (en) * | 1994-06-07 | 1997-01-28 | Mitsubishi Materials Corporation | Method of producing a silicon carbide semiconductor device |
| US5739579A (en) * | 1992-06-29 | 1998-04-14 | Intel Corporation | Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections |
Family Cites Families (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5216264A (en) * | 1989-06-07 | 1993-06-01 | Sharp Kabushiki Kaisha | Silicon carbide MOS type field-effect transistor with at least one of the source and drain regions is formed by the use of a schottky contact |
| JP2509713B2 (en) * | 1989-10-18 | 1996-06-26 | シャープ株式会社 | Silicon carbide semiconductor device and manufacturing method thereof |
| KR960009013A (en) * | 1994-08-18 | 1996-03-22 | 김광호 | Titanium nitride (TiN) gate electrode formation method |
| US5742076A (en) * | 1996-06-05 | 1998-04-21 | North Carolina State University | Silicon carbide switching devices having near ideal breakdown voltage capability and ultralow on-state resistance |
-
1997
- 1997-11-13 SE SE9704150A patent/SE9704150D0/en unknown
- 1997-11-18 US US08/972,253 patent/US6025608A/en not_active Expired - Lifetime
-
1998
- 1998-11-13 WO PCT/SE1998/002049 patent/WO1999026292A2/en not_active Application Discontinuation
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4935804A (en) * | 1984-03-19 | 1990-06-19 | Fujitsu Limited | Semiconductor device |
| US5739579A (en) * | 1992-06-29 | 1998-04-14 | Intel Corporation | Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections |
| WO1995022838A1 (en) * | 1994-02-18 | 1995-08-24 | Telefonaktiebolaget Lm Ericsson | Electromigration resistant metallization structures for microcircuit interconnections with rf-reactively sputtered titanium tungsten and gold |
| US5597744A (en) * | 1994-06-07 | 1997-01-28 | Mitsubishi Materials Corporation | Method of producing a silicon carbide semiconductor device |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2001033704A1 (en) * | 1999-11-02 | 2001-05-10 | Abb Research Limited | HIGH VOLTAGE APPARATUS INCLUDING CONVERTER WITH SiC SEMICONDUCTORS |
| US8821961B2 (en) | 2004-10-13 | 2014-09-02 | Commissariat A L'energie Atomique | MgO-based coating for electrically insulating semiconductive substrates and production method thereof |
Also Published As
| Publication number | Publication date |
|---|---|
| SE9704150D0 (en) | 1997-11-13 |
| US6025608A (en) | 2000-02-15 |
| WO1999026292A3 (en) | 1999-07-29 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US6025608A (en) | Semiconductor device of SiC with insulating layer and a refractory metal nitride layer | |
| US5956578A (en) | Method of fabricating vertical FET with Schottky diode | |
| US5917203A (en) | Lateral gate vertical drift region transistor | |
| US7598576B2 (en) | Environmentally robust passivation structures for high-voltage silicon carbide semiconductor devices | |
| US5710455A (en) | Lateral MOSFET with modified field plates and damage areas | |
| KR100270796B1 (en) | Process for manufacture of mos gated device with selef aligned cells | |
| US5119153A (en) | Small cell low contact resistance rugged power field effect devices and method of fabrication | |
| WO2011027540A1 (en) | Semiconductor element and method for manufacturing same | |
| US6787872B2 (en) | Lateral conduction superjunction semiconductor device | |
| US20070267672A1 (en) | Semiconductor device and method for manufacturing same | |
| JPH0799312A (en) | Semiconductor device and its manufacturing process | |
| CN102576723A (en) | Semiconductor device and process for production thereof | |
| CA2340653A1 (en) | Layered dielectric on silicon carbide semiconductor structures | |
| US6552363B2 (en) | Polysilicon FET built on silicon carbide diode substrate | |
| JP6267514B2 (en) | Semiconductor devices with high performance channels | |
| US5917204A (en) | Insulated gate bipolar transistor with reduced electric fields | |
| US20200161442A1 (en) | Systems and methods for in-situ doped semiconductor gate electrodes for wide bandgap semiconductor power devices | |
| US5234851A (en) | Small cell, low contact assistance rugged power field effect devices and method of fabrication | |
| US6570218B1 (en) | MOSFET with a buried gate | |
| US5780878A (en) | Lateral gate, vertical drift region transistor | |
| EP1029357A2 (en) | Semiconductor device of sic with insulating layer and a refractory metal nitride layer | |
| EP4008025B1 (en) | Silicon carbide transistor device | |
| US11222955B2 (en) | Semiconductor power devices having gate dielectric layers with improved breakdown characteristics and methods of forming such devices | |
| EP1908118B1 (en) | Method for producing a semiconductor device | |
| US11682709B2 (en) | Interface layer control methods for semiconductor power devices and semiconductor devices formed thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| AK | Designated states |
Kind code of ref document: A2 Designated state(s): JP US |
|
| AL | Designated countries for regional patents |
Kind code of ref document: A2 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
| DFPE | Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101) | ||
| 121 | Ep: the epo has been informed by wipo that ep was designated in this application | ||
| AK | Designated states |
Kind code of ref document: A3 Designated state(s): JP US |
|
| AL | Designated countries for regional patents |
Kind code of ref document: A3 Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE |
|
| WWE | Wipo information: entry into national phase |
Ref document number: 1998956065 Country of ref document: EP |
|
| WWP | Wipo information: published in national office |
Ref document number: 1998956065 Country of ref document: EP |
|
| WWW | Wipo information: withdrawn in national office |
Ref document number: 1998956065 Country of ref document: EP |