WO1999031718A1 - Method for high temperature etching of patterned layers using an organic mask stack - Google Patents
Method for high temperature etching of patterned layers using an organic mask stack Download PDFInfo
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- WO1999031718A1 WO1999031718A1 PCT/US1998/025699 US9825699W WO9931718A1 WO 1999031718 A1 WO1999031718 A1 WO 1999031718A1 US 9825699 W US9825699 W US 9825699W WO 9931718 A1 WO9931718 A1 WO 9931718A1
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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Definitions
- the present invention pertains to a method for patterned etching of materials such as copper, platinum, indium, ruthenium, tungsten, and barium strontium titanate, which generally requires higher temperature stability of the stack of masking materials used during the patterned etching.
- the stack of masking materials is designed to minimize the amount of masking material residue and sidewall deposits remaining on feature surfaces after etching.
- Figures 1A - I E show a schematic cross-sectional view of a typical plasma etch stack useful at temperatures in excess of about 150 C as it progresses through a se ⁇ es of steps including the etching of a feature layer
- This etch stack is of the kind known and used p ⁇ or to the present invention
- Figure 1 A shows a complete etch stack, including Substrate 102.
- ARC layer 108 which is typically a metal-containing compound and which enables better imaging of an overlying patterning layer 1 10
- Pattern masking layer 110 which is typically a layer of silicon dioxide or similar inorganic matenal which can withstand the high temperatures encountered dunng etching of conductive layer 106, and which can be patterned and used as a mask dunng such etching And, photoresist layer 112 which is typically
- Figure IB shows the stack descnbed in Figure 1A, where the pattern in photoresist layer 112 has been transferred to pattern masking layer 1 10, using a standard plasma etching technique.
- masking layer 110 compnses a silicon-containing matenal, such as silicon dioxide
- the etch plasma typically compnses a fluonne- generating species.
- the plasma selectivity is for the silicon dioxide over the photoresist mate ⁇ al
- Figure 1C shows the next step in the process of etching conductive layer 106, w here the photoresist layer 1 12 has been stnpped from the surface of pattern masking layer 1 10
- This st ⁇ pping procedure may be a wet chemical removal or may be a plasma etch which is selective for the photoresist layer 1 12 over the pattern masking layer 110
- St ⁇ pping of photoresist layer 1 12 is earned out for two reasons
- the organic-based photoresist materials typically used for layer 1 12 would melt or become distorted in shape at the temperatures commonly reached dunng the etching of conducts e layer 106 This could lead to distortion of the pattern which is transferred to conductive layer 106
- polymenc species generated due to the exposure of the surface of photoresist layer 1 12 to the etchant plasma tend to contaminate adjacent surfaces dunng the etching of conductive layer 106, thereby decreasing the etch rate of conductive layer 106
- Zdebel et al. mention the need to remove the photoresist mate ⁇ al p ⁇ or to etching of underlying layers, to avoid contamination of underlying surfaces with the photoresist mate ⁇ al dunng etching of such underlying layers.
- David Keller descnbes the use of an ozone plasma for the purpose of dry etch removal of a photoresist mask from the surface of an oxide hard mask in U S. Patent No 5,346,586, issued September 13, 1994 Mr. Keller also mentions that it is easier to etch selectively to a gate oxide when there is no photoresist present dunng a polysihcon gate oxide etch step
- Figure ID shows the next step in the etching process, where the desired pattern has been transferred through ARC layer 108, conductive layer 106, and bamer layer 104 Typically all of these layers are metal compnsmg layers, and a halogen containing plasma can be used to etch the pattern through all three layers
- the problem is the removal of the residual silicon dioxide hard masking mate ⁇ al and the removal of residue deposits of the silicon dioxide masking mate ⁇ al from adjacent surfaces.
- the residual hard masking mate ⁇ al is present as residual masking layer 110, and the residue deposits as 114 on the surface of the patterned conductive layer 106 and the surface of substrate 102
- deposit 1 14 can trap residual chemical etch reactants under deposit 1 14 and against the surface of patterned conductive layer 106. leading to subsequent corrosion of conductive layer 106. That corrosion is shown on Figure ID as 1 16.
- a non-planar surface 120 is produced.
- a non-planar surface creates a number of problems in construction of a multi-conductive- layered device, where additional patterned conductive layers (not shown) are constructed over the surface 120 of dielect ⁇ c layer 118.
- the present disclosure pertains to a method of patterning a semiconductor device feature which provides for the easy removal of any residual masking layer which remains after completion of a pattern etching process.
- the method provides for a multi-layered masking structure which includes a layer of high-temperature organic-based masking mate ⁇ al overlaid by either a layer of a high-temperature inorganic masking mate ⁇ al which can be patterned to provide an inorganic hard mask, or by a layer of high- temperature imageable organic masking mate ⁇ al which can be patterned to provide an organic hard mask.
- the hard masking material is used to transfer a pattern to the high- temperature organic-based masking matenal, and then the hard masking mate ⁇ al is removed.
- the high-temperature organic-based masking matenal is used to transfer the pattern to an underlying semiconductor device feature.
- the high-temperature organic-based masking mate ⁇ al can be removed from the surface of the patterned semiconductor device feature in a manner which reduces or avoids contamination of the patterned feature surface.
- the first patterning system uses a multi-layered masking structure which includes a layer of high-temperature organic-based masking material overlaid by a layer of a high- temperature inorganic masking material, which is further overlaid by a layer of a patterning photoresist.
- the patterning method is as follows. a) The layer of photoresist material is imaged and developed into a pattern using techniques known in the art, to produce a patterned mask which can be used to transfer the desired pattern throughout the multi-layered masking structure and eventually through at least one device feature layer as well. b) The patterned photoresist is used to transfer the pattern through i) a layer of high-temperature inorganic masking material; and ii) a layer of high-temperature organic-based masking material. Preferably the pattern transfer through the layer of high-temperature organic- based masking material is via an anisotropic plasma etch technique so that this material is not undercut by the pattern transfer process.
- the layer of high temperature inorganic masking material may be removed at this time using a plasma etch technique or a wet etch technique designed to minimize any etching of the organic-based masking mate ⁇ al.
- the high temperature inorganic masking material is of a thickness such that it will be automatically removed dunng etching of a feature layer (step e).
- the pattern is then transferred from the high-temperature organic-based masking layer through at least one feature layer underlying the high-temperature organic- based masking material.
- Any high-temperature organic-based masking material remaining after feature layer patterning is then easily removed using a plasma etch technique.
- a plasma etch technique When the etched feature layer would be corroded or oxidized by an oxygen-based plasma, a hydrogen- based plasma etch technique is recommended.
- the removal of organic-based masking material may be by a wet stripping technique using a solvent known in the art to be advantageous in the passivation of the surface of the patterned feature layer.
- step a) Since there is no residual photoresist material remaining from step a) present during etching of the feature layer, there is no layer which is likely to melt or distort in shape during transfer of the pattern from the high-temperature organic-based masking material to an underlying device feature layer.
- the high-temperature organic-based masking layer is easily removed, there need be no residual masking layer present in the device structure to affect device performance or to cause planarization difficulties.
- the high-temperature organic-based masking layer is formed from ⁇ -C and ⁇ -FC films deposited using CVD techniques. Examples of starting materials used to form such films include CH 4 , C,H 2 , CF 4 , C 2 F 6 , C 4 F 8 , NF 3 , and combinations thereof; there are, of course, numbers of other carbon-containing precursor materials which can also be used.
- the second patterning system is different from the first patterning system in that it uses a high-temperature pattern-imaging layer rather than a more standard photoresist imaging layer.
- the high-temperature pattern-imaging layer is stable at temperatures ranging from about 150 °C to about 500 C C. compared with photoresist materials which are generally stable at about 150 ⁇ C or lower.
- the high-temperature pattern- imaging layer is a plasma-polymerized material, such as plasma polymerized methyl si lane (PPMS),which may be imaged by deep UV and which is plasma-developable.
- PPMS plasma polymerized methyl si lane
- a layer of high-temperature imageable material is imaged and developed into a pattern using techniques known in the art, to produce a patterned mask which can be used to transfer the desired pattern through the high-temperature organic-based masking material and eventually through at least one device feature layer.
- the pattern is transferred through the underlying layer of high-temperature organic-based masking material.
- the pattern is transferred via an anisotropic etch technique, whereby the high-temperature organic-based masking material is not undercut by the pattern transfer step.
- the pattern is then transferred from the multi-layered structure formed in steps a) and b) through at least one feature layer underlying the high-temperature organic- based masking material.
- the pattern is transferred using an anisotropic etching technique so that any high-temperature imageable material which might remain from step b) is removed during this pattern transfer step.
- an anisotropic etching technique reduces or avoids the possibility of undercutting the high- temperature organic-based material layer during the pattern transfer to the underlying device feature layer.
- Any residual high-temperature organic-based masking material which remains after pattern transfer is then easily removed using a plasma etch technique.
- a hydrogen-based plasma etch technique is recommended. Since there is no low temperature residual photoresist material used during this process, there is no layer which is likely to melt or distort in shape during transfer of the pattern from the high-temperature organic masking material to an underlying device feature layer.
- the high-temperature imageable material is preferably of the kind which can be produced using a silane-based starting material or TEOS-based (tetra-ethyl-ortho-silicate - based) chemistry, although one skilled in the art may select from other materials known in the art.
- TEOS-based tetra-ethyl-ortho-silicate - based
- the high-temperature organic-based masking material is preferably chosen from materials which can be easily removed by plasma etch techniques or by using a solvent known in the art to be advantageous in the passivation of the surface of the patterned feature layer. Examples of such materials are provided above with reference to the first patterning system.
- the at least one device feature layer which is to be patterned includes a copper layer
- that copper layer is preferably pattern etched using either an enhanced physical bombardment technique or a plasma etching technique which generates sufficient hydrogen to protect the copper surface during patterning.
- the most economical method of performing the etch techniques described above utilizes a combination of different plasmas wherein the different etchant gases used to create each plasma are sufficiently compatible that all of the etching steps can be carried out in individual (separate) steps in the same etch chamber, if desired.
- One skilled in the art can select from the various known plasma etchants to obtain the best economies of function which will provide etched features meeting dimensional and surface stability requirements.
- FIGS 1 A through IE show a schematic of the cross-sectional view of a prior art multilayered structure useful in plasma etching (a plasma etch stack), as the etch stack progresses through a series of process steps.
- This etch stack is generally used for etching of a device feature conductive material layer.
- Figure 2 A shows a schematic of the cross-sectional view of a first preferred embodiment plasma etch stack of the present invention.
- Figures 2B through 2G show the changes in the etch stack as it progresses through the method steps of the present invention.
- Figure 3 A shows a schematic of the cross-sectional view of a second preferred embodiment plasma etch stack of the present invention.
- Figures 3B through 3G show the changes in the etch stack as it progresses through the method steps of the present invention.
- Figure 4 is a schematic of a process chamber and auxiliary apparatus of the kind which can be used to carry out the plasma etching steps described herein.
- a semiconductor includes a variety of different materials which are known to have the behavioral characteristics of a semiconductor
- reference to a “plasma” includes a gas or gas reactants activated by an RF glow discharge
- reference to "a conductive material” includes aluminum, aluminum alloys, copper, copper alloys, platinum, platinum alloys, indium, indium alloys, rubidium, ruthenium, ruthenium oxide, combinations thereof, and other conductive mate ⁇ als which would be suitable in the application desc ⁇ bed.
- ⁇ -C refers to high temperature amorphous carbon-compnsing mate ⁇ als which are typically produced by CVD in a plasma chamber.
- ⁇ -FC refers to high temperature fluorocarbon materials which are typically produced by CVD in a plasma chamber.
- aluminum includes alloys of aluminum of the kind typically used in the semiconductor industry. Such alloys include aluminum-copper alloys, and aluminum-copper-silicon alloys, for example. Typically such alloys of aluminum comp ⁇ se about 0.5 % copper.
- anisotropic etching refers to etching which does not proceed in all directions at the same rate. If etching proceeds exclusively in one direction (e.g. only vertically), the etching process is said to be completely anisotropic.
- bias power refers to the power used to control ion bombardment energy and the directionality of ions toward a substrate.
- copper refers to copper and alloys thereof, wherein the copper content of the alloy is at least 80 atomic % copper.
- the alloy may comprise more than two elemental components.
- feature refers to metal lines and openings on a substrate, and other structures used to form a semiconductor device.
- hydrogen-based plasma refers to a plasma having a sufficiently high hydrogen content to reduce the corrosion of the exterior surfaces of etched features by incident reactive species which are present due to etching of adjacent surfaces.
- a preferred example of a hydrogen-based plasma is described in co-pending application Serial No. 08/911,878, filed August 13, 1997.
- a hydrogen-based plasma in addition to a source of hydrogen, will include other additives comprising fluonne, or chlorine, or oxygen, or nitrogen, or carbon, or a combination thereof, by way of example and not by way of limitation.
- ion bombardment refers to physical bombardment by ions (and other excited species of atoms which are present with the ions) to remove atoms from a surface, where physical momentum transfer is used to achieve the atom removal.
- isotropic etching refers to an etching process where etching can proceed in all directions at the same rate.
- oxygen-based plasma refers to a plasma which is rich in oxygen content either in neutral or charged form.
- the plasma may include additives comprising nitrogen, or hydrogen, or chlorine, or fluorine, or carbon, by way of example and not by way of limitation. Additives such as CF 4 , CH 4 and NH 3 are commonly used.
- plasma refers to a partially ionized gas containing an equal number of positive and negative charges, as well as some other number of non-ionized gas particles.
- plasma-polymerized methysilane refers to a new deep UV resist material which is deposited from a low power RF plasma discharge in methylsilane at room temperature. This material possesses an amorphous organosilicon hydride network structure. While initially opaque in the deep UV (i.e. 248 nm), a typical 0.25 micron thick film undergoes efficient photooxidation with bleaching to form glass-like siloxane network material.
- source power refers to the power used to generate ions and neutrals whether directly in an etching chamber or remotely as in the case of a microwave plasma generator.
- substrate includes semiconductor materials, glass, ceramics, polymeric materials, and other materials of use in the semiconductor industry.
- AN APPARATUS FOR PRACTICING THE INVENTION The preferred embodiment etch processes described herein were carried out in a Centura® Integrated Processing System available from Applied Materials, Inc. of Santa Clara, California. The system is shown and described in United States Patent No. 5,186,718, the disclosure of which is hereby incorporated by reference.
- This equipment included a Decoupled Plasma Source (DPS) of the kind described by Yan Ye et al. at the Proceedings of the Eleventh International Symposium of Plasma Processing, May 7, 1996 and as published in the Electrochemical Society Proceedings, Volume 96-12, pp. 222 - 233 ( 1996).
- DPS Decoupled Plasma Source
- the plasma processing chamber enables the processing of an 8 inch (200 mm) diameter silicon wafer.
- FIG. 4 A schematic of the processing chamber is shown in Figure 4 which shows an etching process chamber 410, which is constructed to include at least one inductive coil antenna segment 412 positioned exterior to the etch process chamber 410 and connected to a radio frequency (RF) power generator 418.
- RF radio frequency
- Interior to the process chamber is a substrate 414 support pedestal 416 which is connected to an RF frequency power generator 422 through an impedance matching network 424, and a conductive chamber wall 430 which serves as the electrical ground 434 for the offset bias which accumulates on the substrate 414 as a result of the RF power applied to the substrate support pedestal 416 .
- the semiconductor substrate 414 is placed on the support pedestal 416 and gaseous components are fed into the process chamber through entry ports 426.
- a plasma is ignited in process chamber 410 using techniques well known in the industry.
- Pressure interior to the etch process chamber 410 is controlled using a vacuum pump (not shown) and a throttle valve 427 connected to a process chamber gas exit line 428.
- the temperature on the surface of the etch chamber walls is controlled using liquid- containing conduits (not shown) which are located in the walls of the etch chamber 410.
- the surface of the etching chamber 410 walls was maintained at about 80 °C using the cooling conduits previously described.
- the substrate support platen provides for backside heating or cooling of the substrate.
- Figures 2A - 2G illustrate the first preferred embodiment etch stack of the present invention as it progresses through the method steps of the present invention.
- Figure 2 A shows the complete etch stack, including: Substrate 212, which was a dielectric layer of silicon dioxide approximately 1.000 A thick overlying a silicon wafer surface (not shown).
- a bar ⁇ er layer 214, of tantalum nitride approximately 500 A thick was deposited over substrate 212.
- a layer 216 of copper approximately 8,000 A thick was deposited over barrier layer 214.
- a layer 220 of a high-temperature organic-based pattern masking material comprising ⁇ - FC was deposited over tantalum nitride layer 218 using a high density plasma CVD technique, to produce a layer approximately 8,000 A thick.
- a silicon dioxide pattern masking layer 222 approximately 1,000 A thick, which served as a high-temperature inorganic masking material was applied over the high-temperature ⁇ -FC layer 220.
- a photoresist imaging layer 224, of I - line stepper material (any of these materials which are commonly used in the art are acceptable) approximately 10,000 A thick was applied over the surface of high-temperature inorganic masking material layer 222.
- I - line photoresist imaging layer 224 has already been patterned to provide the feature shape desired to be transferred to the silicon dioxide pattern masking layer 222 and high-temperature organic-based masking layer 220.
- the thickness of photoresist imaging layer 224 is designed so that it is nearly totally consumed during transfer of the pattern through the high-temperature inorganic masking layer 222 and high-temperature organic-based masking layer 224.
- Figure 2B shows the plasma etching stack described in Figure 2A, where the pattern in photoresist imaging layer 224 has been transferred through the high temperature silicon dioxide inorganic pattern masking layer 222 and through the ⁇ -FC- comprising layer 220, to reach the upper surface of tantalum nitride barrier layer 218.
- This pattern transfer was accomplished using an oxygen-based plasma in the Centura® Integrated Processing System previously desc ⁇ bed.
- the plasma feed gas to the process chamber was about 100 seem of argon and 30 seem of CHF,.
- the substrate temperature during etching was about 20 ⁇ C, with the process chamber walls at about 80 °C.
- the process chamber pressure during etching was about 10 mT.
- the source power to the plasma inducing coil was about 1800 W @ 2 MHz and the bias power to the substrate support platen was about 300 W ( ⁇ 13.56 MHz.
- a plasma was ignited using techniques standard in the art, and the time period required for pattern transfer through silicon dioxide layer 222 was approximately 15 seconds.
- the plasma feed gas to the process chamber was 100 seem of O 2 , and 10 seem of N 2 .
- the substrate temperature during etching was about 20 °C, with the process chamber walls at about 80 °C.
- the process chamber pressure during etching was about 10 mT.
- the source power to the plasma inducing coil was about 1000 W @ 2 MHz and the bias power to the substrate support platen was about 250 W @ 13.56 MHz.
- the time period required for pattern transfer through ⁇ -FC layer 220 was approximately 80 seconds.
- Figure 2C shows the plasma etching stack described in Figure 2B, after removal of residual photoresist imaging layer 224.
- Residual photoresist imaging layer 224 was removed using an O 2 / N 2 plasma.
- the plasma feed gas to the process chamber was 100 seem of O 2 and 10 seem of N 2 .
- the substrate temperature during etching was about 20 °C, with the process chamber walls at about 80 °C.
- the process chamber pressure during etching was about 10 mT.
- the source power to the plasma inducing coil was about 1,000 W @ 2 MHz and the bias power to the substrate support platen was about 250 W @ 13.56 MHz.
- a plasma was ignited using techniques standard in the art, and the time period required for the removal of the residual photoresist material was about 20 seconds.
- the underlying layer 222 of silicon dioxide was used as an etch stop over high-temperature organic-based layer 220, while tantalum nitride barrier layer 218 was used as the etch stop protecting copper layer 216.
- the plasma and process conditions described above provided anisotropic stripping of photoresist imaging layer 224, so that high-temperature ⁇ -FC masking layer 220 would not be undercut during the removal of residual photoresist imaging layer 224.
- any oxidizing plasma can be used to remove most photoresist materials.
- Figure 2D shows an optional step in which the layer 222 of silicon dioxide may be removed.
- feature layer 216 comprises a metal (copper)
- this layer will be automatically removed during the patterning of feature layer 216.
- Figure 2E shows the plasma etching stack after transfer of the pattern through tantalum nitride barrier layer 218, copper layer 216, and tantalum nitride barrier layer 214 to the upper surface of silicon dioxide dielectric layer 212.
- This etching of the conductive copper layer 216 and accompanying barrier layers 218 and 214 was accomplished using a feed gas to the process chamber of 70 seem of HC1, 50 seem of N 2 , and 5 seem of BC1 3 .
- the substrate temperature during etching was about 250 °C, with the process chamber walls at about 80 °C.
- the process chamber pressure during etching was about 20 mT.
- the source power to the plasma inducing coil was about 1,500 W @ 2 MHz and the bias power to the substrate support platen was about 600 W @ 13.56 MHz.
- the end point of etch through tantalum nitride barrier layer 214 was measured by optical monitoring using a sensor measuring at a wavelength of about 3,590 A.
- the time period required for pattern transfer through the tantalum nitride barrier layer 218, copper layer 216, and tantalum nitride barrier layer 214 was about 150 seconds.
- a hydrogen-based etch chemistry was used during patterning of the copper feature layer 216 to avoid corrosion of the copper. Use of a conventional oxygen and fluorine based chemistry may induce oxidation/corrosion.
- ⁇ -FC layer 220 Depending on the relative thicknesses of layers ⁇ -FC layer 220, tantalum nitride 218, copper layer 216, and tantalum nitride layer 214 and the etching conditions used, there should be enough of the ⁇ -FC layer 220 remaining at the end of the etch process to provide CD (critical dimension) control. Therefore, a separate process is needed to remove the remaining portion of this ⁇ -FC layer.
- the process for stripping the ⁇ -FC layer may be earned out in the feature patterning etch chamber or in a downstream plasma chamber
- Figure 2F shows the patterned feature layer 216 with accompanying bamer layers 214 and 218.
- the ⁇ -FC laver 220 is removed via anisotropic st ⁇ pping using a hydrogen based chemistry of the kind desc ⁇ bed above or a wet st ⁇ pping process using a solvent which assists in the passivation of the etched copper feature surface
- an anisotropic dry st ⁇ pping technique was used, wherein the feed gas to the process chamber was 100 seem of H 2
- the substrate temperature dunng etching was about 45 °C, with the process chamber walls at about 80 °C
- the process chamber pressure dunng etching was about 10 mT
- the source power to the plasma inducing coil was about 1 ,000 W @ 2 MHz and the bias power to the substrate support platen was about 200 W @ 13 56 MHz.
- the time pe ⁇ od required for st ⁇ pping of the remaining portion of the ⁇ -FC layer 220 was about 120
- Figure 2G shows the application of a plananzation layer 230 of a low dielect ⁇ c constant mate ⁇ al such as an ⁇ -C or an ⁇ -FC over patterned tantalum nit ⁇ de layer 218, copper layer 216, tantalum nitnde layer 214, and silicon dioxide substrate 212.
- the plananzation layer exhibited a truly planar surface, rather than the non-planar surface 120 observed for the pnor art plananzation layer illustrated in Figure IE.
- the ⁇ -C or an ⁇ -FC is applied using a vapor deposition technique known in the art, although spm-on techniques, for example, are also acceptable
- high-temperature inorganic masking matenals other than silicon oxide can be used as the capping layer overlying the high- temperature orgamc-compnsing masking matenal.
- high-temperature organic-based masking matenals other than ⁇ -FC such as ⁇ -C, polyimide, parylene, and teflon, for example, can be used.
- Anti-reflective/barner layer matenals other than tantalum nitnde such as silicon oxymtnde, tantalum, titanium nit ⁇ de, tungsten titanate, and tungsten nitnde may also be used.
- the method is not limited to the etching of device features which utilize copper as the conductive material. Other conductive materials such as tungsten, platinum, silver, gold, iridium. and ruthenium, for example can be used as well.
- Figures 3 A - 3G illustrate the second preferred embodiment etch stack of the present invention and its progression through the method steps of the present invention.
- Figure 3 A shows the complete etch stack, including: Substrate 312, which was a dielectric layer of silicon dioxide approximately 10,000 A thick overlying a silicon wafer surface (not shown).
- a barrier layer 314, of tantalum nitride approximately 500 A thick was deposited over substrate 312.
- a layer 316 of copper approximately 8,000 A thick was deposited over barrier layer 314.
- a layer 218 of tantalum nitride about 500 A thick was deposited over copper layer 216.
- a layer 220 of a high-temperature organic-based pattern masking material comprising ⁇ -FC was deposited over titanium nitride layer 218 using a high density plasma CVD technique, to produce a layer approximately 8,000 A thick.
- a layer 322 of plasma polymerized methylsilane (PPMS) was deposited from a low power RF plasma discharge in methylsilane at room temperature, to produce a layer approximately 1 ,000 A thick.
- the PPMS layer was exposed to deep UV with bleaching to produce a glass-like siloxane pattern 324 within PPMS layer 322, as shown in Figure 3B.
- Figure 3C illustrates the pattern development of the PPMS high temperature imaging layer 324, which was developed using chlorine plasma etching by techniques known in the art (as described by T.W. Weidman et al., Journal of Photopolymer Science and Technology, Volume 8, Number 4, 679 - 686 (1995)).
- the underlying ⁇ -FC layer 320 was etched using an oxygen-based plasma in the manner described above with reference to Figure 2B, where ⁇ -FC layer 220 was patterned.
- the time period required for pattern transfer through ⁇ -FC layer 320 was approximately 80 seconds.
- the oxygen-based plasma chemistry was chosen so that the patterned silicon dioxide 324 formed from the high- temperature imageable mate ⁇ al (PPMS) layer 322 and tantalum nit ⁇ de bamer layer 318 would not be attacked dunng etching of ⁇ -FC layer 320
- the oxygen-based etch conditions referenced above provided anisotropic etch conditions so that undercutting of the ⁇ -FC layer 320 dunng pattern development was avoided
- Figure 3E shows the transfer of the pattern through tantalum nitnde bamer layer 318, copper layer 316, and tantalum nitnde bamer layer 314 to the upper surface of silicon dioxide dielectnc layer 312 This etching of the conductive copper layer 316 and accompanying bamer layers 318 and 314 was accomplished using the method desc ⁇ bed with reference to Figure 2E
- ⁇ -FC layer 320 Depending on the relative thicknesses of layers ⁇ -FC layer 320, tantalum nit ⁇ de 318, copper layer 316, and tantalum nitnde layer 314 and the etching conditions used, there should be enough of the ⁇ -FC layer 320 remaimng at the end of the etch process to provide CD (c ⁇ tical dimension) control Therefore, a separate process is needed to remove the remaining portion of this ⁇ -FC layer The process for st ⁇ pping the ⁇ -FC layer may be earned out in the feature patterning etch chamber or in a downstream plasma chamber.
- Figure 3F shows the patterned feature layer 316 with accompanying bamer layers 318 and 314, after removal of the remaimng portion of the ⁇ -FC layer 320
- the ⁇ -FC layer 320 is removed via anisotropic st ⁇ pping using a hydrogen based chemistry of the kind descnbed above or a wet st ⁇ pping process using a solvent which assists in the passivation of the etched copper feature surface
- an anisotropic dry stnpping technique as descnbed with reference to Figure 2F was used
- Figure 3G shows the application of a plananzation layer 328 of a low dielectnc constant matenal such as an ⁇ -C or an ⁇ -FC over the patterned tantalum nitnde layer 318, copper layer 316, tantalum nit ⁇ de layer 314, and silicon dioxide substrate 312
- the plananzation layer exhibited a truly planar surface, rather than the non-planar surface 120 observed for the pnor art plananzation layer illustrated in Figure 1 E
- the ⁇ -C or an ⁇ -FC is applied using a vapor deposition technique known in the art, although spin-on techniques, for example, are also acceptable
- high-temperature imageable masking mate ⁇ als other than PMMS can be used as the layer for pattern transfer to the high- temperature orgamc-compnsing masking mate ⁇ al
- high-temperature organic-based masking mate ⁇ als, ARC matenals, bamer layer mate ⁇ als, and conductive mate ⁇ als can be used.
- Application Senal No. 08/891,410 discloses that copper can be pattern etched at acceptable rates and with selectivity over adjacent matenals using an etch process which utilizes a solely physical basis such as ion bombardment, without the need for a chemically based etch component.
- a first preferred enhanced physical bombardment technique requires an increase in ion density and/or an increase in ion energy of ionized species which stnke the substrate surface.
- An increase in ion density is preferably achieved by placing a device inside the etch chamber above the substrate surface, which device enables an increase m the number of lomzed particles st ⁇ kmg the substrate surface.
- An example of such a device is an inductive coil which is used to increase the number of ionized species or to maintain the number of lomzed species supplied by another source so that an increased number of lomzed species are available to stnke the substrate surface.
- a second preferred method for increasing the number of ionized species is to feed into the process chamber a microwave-generated plasma produced outside of the chamber. It is also possible to increase the number of ionized species by increasing the RF power to an external inductively coupled coil or to increase the DC power to a capacitively coupled source for ion species generation. However, these latter t o techniques are less preferred methods for increasing ion density, since the copper (and alloy metal(s)) atoms generated during etching affect the performance of an external coil and since capacitively coupled species generation is not very efficient.
- ion energy it is meant the energy of the ion at the time it strikes the substrate surface.
- a second preferred enhanced physical bombardment technique is increasing (to the limit that the substrate is detrimentally affected) the ion energy.
- Ion energy may be increased by increasing an offset bias on the substrate which attracts the ionized species toward the substrate. This is typically done by increasing the RF power to a platen on which the substrate sets. The effectiveness of an increase in the bias power is dependent upon the RF frequency and the ratio of the bias grounding area to the surface area of the substrate. Ion energy is further increased by operating the etch process chamber at a lower pressure.
- a third enhanced physical bombardment technique is a pulsing of the ion density or the ion energy.
- One preferred means of pulsing the ion energy is to pulse the power to the device which produces the ion species or which is used to increase or maintain the number of ionized species available to strike the substrate surface.
- Such pulsing is preferably applied to a device located internally within the process chamber.
- the pulsing may be of the feed rate of an externally-generated plasma into the process chamber. Less preferably, the pulsing may be applied to an external inductively coupled source for plasma generation or to a capacitively coupled source for plasma generation.
- An even more preferred means of pulsing the ion energy is by pulsing the power to the offset bias source which is applied to the substrate. Pulsing of the ion energy reduces the possibility that an excited copper ion leaving the copper surface during etching will reattach to the copper surface in an adjacent location.
- the pressure in the process vessel may also be pulsed as a means of pulsing the ion energy.
- the fourth enhanced physical bombardment technique is the use of thermal phoresis.
- Thermal phoresis occurs when the temperature of the substrate surface is higher than the temperature of the etch chamber surfaces (walls), whereby particles dislodged from the higher temperature substrate surface are attracted toward the colder chamber surfaces.
- the concentration of the chemically reactive ion component is sufficiently low that the etching is earned out in a physical bombardment dominated etch regime
- this combination technique is earned out at temperatures above about 150 °C and at pressures below about 50 mT
- the copper removal rate is not limited solely to the rate of formation of the volatile compounds and the ability of a low process chamber pressure to facilitate removal of such volatile compounds
- the pressure in the process chamber can be adjusted, to permit increased ion bombardment.
- the preferred chemically reactive ion species is a halogen-comp ⁇ sing species or compound having a low molecular weight, such as Cl : , HC1, BCl j , HBr, CHF 3 , CF 4 , S ⁇ Cl 4 , and combinations thereof.
- Cl halogen-comp ⁇ sing species or compound having a low molecular weight
- the chlo ⁇ ne-comp ⁇ sing components present in the feed gases to the etch chamber should be no greater than 30 volume % of the gases fed into the etch chamber dunng the patterned copper etch.
- a passivatmg agent such as N 2 , NH 3 , and CH 4 may be used m combination with the chemically reactive ion species
- the content of copendmg application Senal No. 08/ 891,410 is hereby incorporated by reference in its entirety
- Application Senal No. 08/ 911,878 descnbes an alternative copper etching technology which employs HC1 and HBr chemistnes in a manner which protects copper from corrosion dunng the etching process
- copper can be pattern etched in the presence of HC1 or HBr while providing the desired feature dimension and mteg ⁇ ty if the surface of the copper feature being etched is properly protected dunng etching
- hydrogen is applied to that surface.
- Hydrogen is adsorbed on the copper exte ⁇ or surface and may be absorbed into the extenor surface of the copper, so that it is available to react with species which would otherwise penetrate that exte ⁇ or surface and react with the copper inte ⁇ or to that surface
- Sufficient hydrogen must be applied to the exterior surface of the etched portion of the copper feature to prevent incident reactive species present due to etching of adjacent feature surfaces from penetrating the previously etched feature exterior surface.
- any plasma feed gas component comprising hydrogen which is capable of generating sufficient amounts of hydrogen
- the most preferred embodiment of the invention provides for the use of a component which contains both hydrogen and halogen.
- Preferred examples are hydrogen chloride (HCl) and/or hydrogen bromide (HBr), which are used as the principal source of the reactive species for etching copper. Dissociation of the HCl and/or HBr provides large amounts of hydrogen for protection of etched copper surfaces, thereby preventing penetration by reactive species adjacent the etched surface.
- Additional hydrogen gas may be added to the plasma feed gas which comprises the HCl and/or HBr when the reactive species density in the etch process chamber is particularly high.
- the hydrogen-releasing, halogen-comprising plasma feed gas component may be used as an additive (producing less than 40 % of the plasma-generated reactive species) in combination with other plasma etching species.
- the HCl or HBr accounts for at least 40 %, and more preferably at least 50 %, of the reactive species generated by the plasma.
- Other reactive species may be used for purposes of feature surface passivation during etching or for purposes of feature surface protection after completion or near the completion of feature surface etching.
- the species added for surface passivation or surface protection during etching of the copper feature preferably make up 30 % or less, or more preferably make up 10 % or less of the plasma-generated reactive species.
- additional gases which may be added to the plasma feed gas include CH 4 , CH 3 F, BC1 3 , N 2 NH 3 , SiCl 4 CC1 4 , and CHF 3 .
- Plasma feed gases may include additional inert (non-reactive with copper) gases such as argon, helium, or xenon, to enhance the ionization, or dissociation, or to dilute the reactive species.
- additional inert (non-reactive with copper) gases such as argon, helium, or xenon, to enhance the ionization, or dissociation, or to dilute the reactive species.
- the critical feature is the availability of hydrogen at the feature surface during the etching process.
- the content of U.S. Application Serial No. 08/911,878 is hereby incorporated by reference in its entirety.
- the above described preferred embodiments are not intended to limit the scope of the present invention, as one skilled in the art can, in view of the present disclosure expand such embodiments to correspond with the subject matter
Abstract
Description
Claims
Priority Applications (6)
Application Number | Priority Date | Filing Date | Title |
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KR1020007006422A KR20010033061A (en) | 1997-12-12 | 1998-12-04 | Method for high temperature etching of patterned layers using an organic mask stack |
EP98961897A EP1038310A1 (en) | 1997-12-12 | 1998-12-04 | Method for high temperature etching of patterned layers using an organic mask stack |
JP2000539519A JP2002509353A (en) | 1997-12-12 | 1998-12-04 | High-temperature etching method of pattern layer using organic mask laminate |
KR1020017004916A KR20010085939A (en) | 1997-12-12 | 1999-10-08 | Method of etching patterned layers useful as masking during subsequent etching or for damascene structures |
JP2000577705A JP2003526897A (en) | 1998-10-19 | 1999-10-08 | Method of etching a patterned layer useful as masking during subsequent etching or useful for damascene structures |
PCT/US1999/023597 WO2000024048A1 (en) | 1998-10-19 | 1999-10-08 | Method of etching patterned layers useful as masking during subsequent etching or for damascene structures |
Applications Claiming Priority (2)
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US08/991,219 US6143476A (en) | 1997-12-12 | 1997-12-12 | Method for high temperature etching of patterned layers using an organic mask stack |
US08/991,219 | 1997-12-12 |
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WO1999031718A1 true WO1999031718A1 (en) | 1999-06-24 |
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PCT/US1998/025699 WO1999031718A1 (en) | 1997-12-12 | 1998-12-04 | Method for high temperature etching of patterned layers using an organic mask stack |
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US (2) | US6143476A (en) |
EP (1) | EP1038310A1 (en) |
JP (1) | JP2002509353A (en) |
KR (2) | KR20010033061A (en) |
WO (1) | WO1999031718A1 (en) |
Cited By (4)
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---|---|---|---|---|
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US6368514B1 (en) * | 1999-09-01 | 2002-04-09 | Luminous Intent, Inc. | Method and apparatus for batch processed capacitors using masking techniques |
US20050158666A1 (en) * | 1999-10-15 | 2005-07-21 | Taiwan Semiconductor Manufacturing Company, Ltd. | Lateral etch inhibited multiple etch method for etching material etchable with oxygen containing plasma |
US6268287B1 (en) * | 1999-10-15 | 2001-07-31 | Taiwan Semiconductor Manufacturing Company | Polymerless metal hard mask etching |
US20050022839A1 (en) * | 1999-10-20 | 2005-02-03 | Savas Stephen E. | Systems and methods for photoresist strip and residue treatment in integrated circuit manufacturing |
US6541367B1 (en) | 2000-01-18 | 2003-04-01 | Applied Materials, Inc. | Very low dielectric constant plasma-enhanced CVD films |
US6440860B1 (en) * | 2000-01-18 | 2002-08-27 | Micron Technology, Inc. | Semiconductor processing methods of transferring patterns from patterned photoresists to materials, and structures comprising silicon nitride |
US6573030B1 (en) | 2000-02-17 | 2003-06-03 | Applied Materials, Inc. | Method for depositing an amorphous carbon layer |
US6391790B1 (en) | 2000-05-22 | 2002-05-21 | Applied Materials, Inc. | Method and apparatus for etching photomasks |
US7115523B2 (en) | 2000-05-22 | 2006-10-03 | Applied Materials, Inc. | Method and apparatus for etching photomasks |
JP3403373B2 (en) * | 2000-05-26 | 2003-05-06 | 松下電器産業株式会社 | Method for etching organic film, method for manufacturing semiconductor device, and method for forming pattern |
JP2002194547A (en) * | 2000-06-08 | 2002-07-10 | Applied Materials Inc | Method of depositing amorphous carbon layer |
US6440864B1 (en) * | 2000-06-30 | 2002-08-27 | Applied Materials Inc. | Substrate cleaning process |
US6426304B1 (en) * | 2000-06-30 | 2002-07-30 | Lam Research Corporation | Post etch photoresist strip with hydrogen for organosilicate glass low-κ etch applications |
DE10037957C1 (en) * | 2000-07-27 | 2002-02-28 | Infineon Technologies Ag | Process for the anisotropic dry etching of organic anti-reflection layers |
US6455431B1 (en) * | 2000-08-01 | 2002-09-24 | Applied Materials Inc. | NH3 plasma descumming and resist stripping in semiconductor applications |
US6465366B1 (en) * | 2000-09-12 | 2002-10-15 | Applied Materials, Inc. | Dual frequency plasma enhanced chemical vapor deposition of silicon carbide layers |
US6657284B1 (en) | 2000-12-01 | 2003-12-02 | Taiwan Semiconductor Manufacturing Co., Ltd. | Graded dielectric layer and method for fabrication thereof |
US6743732B1 (en) * | 2001-01-26 | 2004-06-01 | Taiwan Semiconductor Manufacturing Company | Organic low K dielectric etch with NH3 chemistry |
US6294457B1 (en) * | 2001-02-01 | 2001-09-25 | Taiwan Semiconductor Manufacturing Company | Optimized IMD scheme for using organic low-k material as IMD layer |
US6429121B1 (en) * | 2001-02-07 | 2002-08-06 | Advanced Micro Devices, Inc. | Method of fabricating dual damascene with silicon carbide via mask/ARC |
US6620733B2 (en) * | 2001-02-12 | 2003-09-16 | Lam Research Corporation | Use of hydrocarbon addition for the elimination of micromasking during etching of organic low-k dielectrics |
US6777344B2 (en) | 2001-02-12 | 2004-08-17 | Lam Research Corporation | Post-etch photoresist strip with O2 and NH3 for organosilicate glass low-K dielectric etch applications |
US6841483B2 (en) * | 2001-02-12 | 2005-01-11 | Lam Research Corporation | Unique process chemistry for etching organic low-k materials |
US6893969B2 (en) * | 2001-02-12 | 2005-05-17 | Lam Research Corporation | Use of ammonia for etching organic low-k dielectrics |
US6465343B1 (en) * | 2001-02-28 | 2002-10-15 | Advanced Micro Devices, Inc. | Method for forming backend interconnect with copper etching and ultra low-k dielectric materials |
US6670278B2 (en) | 2001-03-30 | 2003-12-30 | Lam Research Corporation | Method of plasma etching of silicon carbide |
US6630407B2 (en) | 2001-03-30 | 2003-10-07 | Lam Research Corporation | Plasma etching of organic antireflective coating |
US20020155693A1 (en) * | 2001-04-23 | 2002-10-24 | Chartered Semiconductor Manufacturing Ltd. | Method to form self-aligned anti-via interconnects |
US6503845B1 (en) | 2001-05-01 | 2003-01-07 | Applied Materials Inc. | Method of etching a tantalum nitride layer in a high density plasma |
US6559001B2 (en) | 2001-05-30 | 2003-05-06 | International Business Machines Corporation | Methods of patterning a multi-layer film stack and forming a lower electrode of a capacitor |
KR100531419B1 (en) | 2001-06-12 | 2005-11-28 | 주식회사 하이닉스반도체 | semiconductor device and method for fabricating the same |
US20020192944A1 (en) * | 2001-06-13 | 2002-12-19 | Sonderman Thomas J. | Method and apparatus for controlling a thickness of a copper film |
US20030003374A1 (en) * | 2001-06-15 | 2003-01-02 | Applied Materials, Inc. | Etch process for photolithographic reticle manufacturing with improved etch bias |
KR100825130B1 (en) * | 2001-07-06 | 2008-04-24 | 어플라이드 머티어리얼스, 인코포레이티드 | Method of reducing particulates in a plasma etch chamber during a metal etching process |
CN1277293C (en) * | 2001-07-10 | 2006-09-27 | 东京毅力科创株式会社 | Dry etching method |
US7183201B2 (en) * | 2001-07-23 | 2007-02-27 | Applied Materials, Inc. | Selective etching of organosilicate films over silicon oxide stop etch layers |
US6541380B2 (en) * | 2001-07-24 | 2003-04-01 | Applied Materials Inc. | Plasma etching process for metals and metal oxides, including metals and metal oxides inert to oxidation |
US6548416B2 (en) * | 2001-07-24 | 2003-04-15 | Axcelis Technolgoies, Inc. | Plasma ashing process |
US7085616B2 (en) | 2001-07-27 | 2006-08-01 | Applied Materials, Inc. | Atomic layer deposition apparatus |
US6709875B2 (en) | 2001-08-08 | 2004-03-23 | Agilent Technologies, Inc. | Contamination control for embedded ferroelectric device fabrication processes |
WO2003021659A1 (en) | 2001-09-04 | 2003-03-13 | Applied Materials, Inc. | Methods and apparatus for etching metal layers on substrates |
KR100685947B1 (en) * | 2001-09-08 | 2007-02-23 | 엘지.필립스 엘시디 주식회사 | Method For Fabricating Liquid Crystal Display Device |
DE10309711A1 (en) * | 2001-09-14 | 2004-09-16 | Robert Bosch Gmbh | Method for etching structures in an etching body with a plasma |
JP3739325B2 (en) * | 2001-09-20 | 2006-01-25 | 株式会社日立製作所 | Etching method of organic insulating film |
US6605549B2 (en) | 2001-09-29 | 2003-08-12 | Intel Corporation | Method for improving nucleation and adhesion of CVD and ALD films deposited onto low-dielectric-constant dielectrics |
US6649531B2 (en) | 2001-11-26 | 2003-11-18 | International Business Machines Corporation | Process for forming a damascene structure |
US20030134499A1 (en) * | 2002-01-15 | 2003-07-17 | International Business Machines Corporation | Bilayer HDP CVD / PE CVD cap in advanced BEOL interconnect structures and method thereof |
US6737747B2 (en) * | 2002-01-15 | 2004-05-18 | International Business Machines Corporation | Advanced BEOL interconnect structures with low-k PE CVD cap layer and method thereof |
US6869880B2 (en) * | 2002-01-24 | 2005-03-22 | Applied Materials, Inc. | In situ application of etch back for improved deposition into high-aspect-ratio features |
JP2003282535A (en) * | 2002-03-20 | 2003-10-03 | Sanyo Electric Co Ltd | Method of manufacturing semiconductor |
US6541397B1 (en) | 2002-03-29 | 2003-04-01 | Applied Materials, Inc. | Removable amorphous carbon CMP stop |
WO2003089990A2 (en) * | 2002-04-19 | 2003-10-30 | Applied Materials, Inc. | Process for etching photomasks |
KR20040012451A (en) * | 2002-05-14 | 2004-02-11 | 어플라이드 머티어리얼스, 인코포레이티드 | Methods for etching photolithographic reticles |
US6764949B2 (en) * | 2002-07-31 | 2004-07-20 | Advanced Micro Devices, Inc. | Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication |
KR100464430B1 (en) * | 2002-08-20 | 2005-01-03 | 삼성전자주식회사 | Method of etching aluminum layer using hard mask and metalization method for semiconductor device |
DE10240099A1 (en) * | 2002-08-30 | 2004-03-11 | Infineon Technologies Ag | Production of a semiconductor structure comprises preparing a semiconductor substrate, providing a lower first, a middle second and an upper third mask layer on a surface of the substrate, and further processing |
US20040063008A1 (en) * | 2002-09-26 | 2004-04-01 | Advanced Micro Devices, Inc. | Post etch overlay metrology to avoid absorbing layers preventing measurements |
US6797552B1 (en) * | 2002-11-19 | 2004-09-28 | Advanced Micro Devices, Inc. | Method for defect reduction and enhanced control over critical dimensions and profiles in semiconductor devices |
US7344991B2 (en) | 2002-12-23 | 2008-03-18 | Tokyo Electron Limited | Method and apparatus for multilayer photoresist dry development |
US6802945B2 (en) * | 2003-01-06 | 2004-10-12 | Megic Corporation | Method of metal sputtering for integrated circuit metal routing |
US7253115B2 (en) * | 2003-02-06 | 2007-08-07 | Applied Materials, Inc. | Dual damascene etch processes |
KR100493048B1 (en) * | 2003-02-13 | 2005-06-02 | 삼성전자주식회사 | Method for forming wire line and interconnecting contacts by using multi-layered hard mask |
US6960413B2 (en) * | 2003-03-21 | 2005-11-01 | Applied Materials, Inc. | Multi-step process for etching photomasks |
WO2004095551A1 (en) * | 2003-03-31 | 2004-11-04 | Tokyo Electron Limited | Method and apparatus for multilayer photoresist dry development |
US7077973B2 (en) * | 2003-04-18 | 2006-07-18 | Applied Materials, Inc. | Methods for substrate orientation |
US6764927B1 (en) * | 2003-04-24 | 2004-07-20 | Taiwan Semiconductor Manufacturing Co., Ltd | Chemical vapor deposition (CVD) method employing wetting pre-treatment |
US20040229470A1 (en) * | 2003-05-14 | 2004-11-18 | Applied Materials, Inc. | Method for etching an aluminum layer using an amorphous carbon mask |
US8101025B2 (en) * | 2003-05-27 | 2012-01-24 | Applied Materials, Inc. | Method for controlling corrosion of a substrate |
US7521000B2 (en) * | 2003-08-28 | 2009-04-21 | Applied Materials, Inc. | Process for etching photomasks |
US7799685B2 (en) * | 2003-10-13 | 2010-09-21 | Mattson Technology, Inc. | System and method for removal of photoresist in transistor fabrication for integrated circuit manufacturing |
KR100562985B1 (en) * | 2003-12-30 | 2006-03-23 | 주식회사 하이닉스반도체 | Method of forming metal wiring in flash memory device |
US7064078B2 (en) * | 2004-01-30 | 2006-06-20 | Applied Materials | Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme |
JP2005277375A (en) * | 2004-02-27 | 2005-10-06 | Nec Electronics Corp | Semiconductor device manufacturing method |
WO2005087974A2 (en) * | 2004-03-05 | 2005-09-22 | Applied Materials, Inc. | Cvd processes for the deposition of amorphous carbon films |
US7638440B2 (en) * | 2004-03-12 | 2009-12-29 | Applied Materials, Inc. | Method of depositing an amorphous carbon film for etch hardmask application |
US7079740B2 (en) * | 2004-03-12 | 2006-07-18 | Applied Materials, Inc. | Use of amorphous carbon film as a hardmask in the fabrication of optical waveguides |
US20050199585A1 (en) * | 2004-03-12 | 2005-09-15 | Applied Materials, Inc. | Method of depositing an amorphous carbon film for metal etch hardmask application |
US6931991B1 (en) * | 2004-03-31 | 2005-08-23 | Matsushita Electric Industrial Co., Ltd. | System for and method of manufacturing gravure printing plates |
US7122489B2 (en) * | 2004-05-12 | 2006-10-17 | Matsushita Electric Industrial Co., Ltd. | Manufacturing method of composite sheet material using ultrafast laser pulses |
KR100598105B1 (en) * | 2004-06-17 | 2006-07-07 | 삼성전자주식회사 | Method of forming semiconductor patterns |
US7148142B1 (en) * | 2004-06-23 | 2006-12-12 | Advanced Micro Devices, Inc. | System and method for imprint lithography to facilitate dual damascene integration in a single imprint act |
US20070193602A1 (en) * | 2004-07-12 | 2007-08-23 | Savas Stephen E | Systems and Methods for Photoresist Strip and Residue Treatment in Integrated Circuit Manufacturing |
US20060019099A1 (en) * | 2004-07-20 | 2006-01-26 | General Electric Company | Method for making multilayer film, sheet and articles therefrom |
US7208420B1 (en) * | 2004-07-22 | 2007-04-24 | Lam Research Corporation | Method for selectively etching an aluminum containing layer |
US20060021971A1 (en) * | 2004-07-30 | 2006-02-02 | Kevin Pears | Method for plasma treatment of a carbon layer |
US7586097B2 (en) | 2006-01-05 | 2009-09-08 | Virgin Islands Microsystems, Inc. | Switching micro-resonant structures using at least one director |
US7791290B2 (en) | 2005-09-30 | 2010-09-07 | Virgin Islands Microsystems, Inc. | Ultra-small resonating charged particle beam modulator |
US20070034518A1 (en) * | 2005-08-15 | 2007-02-15 | Virgin Islands Microsystems, Inc. | Method of patterning ultra-small structures |
US20060035173A1 (en) * | 2004-08-13 | 2006-02-16 | Mark Davidson | Patterning thin metal films by dry reactive ion etching |
US7626179B2 (en) | 2005-09-30 | 2009-12-01 | Virgin Island Microsystems, Inc. | Electron beam induced resonance |
JP2006086500A (en) * | 2004-08-18 | 2006-03-30 | Toshiba Corp | Method for manufacturing semiconductor device |
US7151040B2 (en) * | 2004-08-31 | 2006-12-19 | Micron Technology, Inc. | Methods for increasing photo alignment margins |
US7910288B2 (en) | 2004-09-01 | 2011-03-22 | Micron Technology, Inc. | Mask material conversion |
US7655387B2 (en) | 2004-09-02 | 2010-02-02 | Micron Technology, Inc. | Method to align mask patterns |
US7115525B2 (en) * | 2004-09-02 | 2006-10-03 | Micron Technology, Inc. | Method for integrated circuit fabrication using pitch multiplication |
KR100759418B1 (en) * | 2004-10-11 | 2007-09-20 | 삼성전자주식회사 | Method for measuring alignment while fabricating semiconductor |
US7138717B2 (en) * | 2004-12-01 | 2006-11-21 | International Business Machines Corporation | HDP-based ILD capping layer |
US8293430B2 (en) * | 2005-01-27 | 2012-10-23 | Applied Materials, Inc. | Method for etching a molybdenum layer suitable for photomask fabrication |
US7829243B2 (en) | 2005-01-27 | 2010-11-09 | Applied Materials, Inc. | Method for plasma etching a chromium layer suitable for photomask fabrication |
US7390746B2 (en) * | 2005-03-15 | 2008-06-24 | Micron Technology, Inc. | Multiple deposition for integration of spacers in pitch multiplication process |
US7253118B2 (en) * | 2005-03-15 | 2007-08-07 | Micron Technology, Inc. | Pitch reduced patterns relative to photolithography features |
US7611944B2 (en) | 2005-03-28 | 2009-11-03 | Micron Technology, Inc. | Integrated circuit fabrication |
WO2006107942A1 (en) * | 2005-04-05 | 2006-10-12 | Analog Devices, Inc. | Vapor hf etch process mask and method |
KR100669560B1 (en) * | 2005-05-16 | 2007-01-15 | 주식회사 하이닉스반도체 | Method for forming interconnect of semiconductor device |
US7429536B2 (en) | 2005-05-23 | 2008-09-30 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7560390B2 (en) | 2005-06-02 | 2009-07-14 | Micron Technology, Inc. | Multiple spacer steps for pitch multiplication |
US7396781B2 (en) | 2005-06-09 | 2008-07-08 | Micron Technology, Inc. | Method and apparatus for adjusting feature size and position |
US7413981B2 (en) | 2005-07-29 | 2008-08-19 | Micron Technology, Inc. | Pitch doubled circuit layout |
JP2007053220A (en) * | 2005-08-18 | 2007-03-01 | Oki Electric Ind Co Ltd | Manufacturing method of semiconductor device |
US8123968B2 (en) | 2005-08-25 | 2012-02-28 | Round Rock Research, Llc | Multiple deposition for integration of spacers in pitch multiplication process |
US7816262B2 (en) | 2005-08-30 | 2010-10-19 | Micron Technology, Inc. | Method and algorithm for random half pitched interconnect layout with constant spacing |
US7829262B2 (en) | 2005-08-31 | 2010-11-09 | Micron Technology, Inc. | Method of forming pitch multipled contacts |
US7759197B2 (en) | 2005-09-01 | 2010-07-20 | Micron Technology, Inc. | Method of forming isolated features using pitch multiplication |
US7776744B2 (en) | 2005-09-01 | 2010-08-17 | Micron Technology, Inc. | Pitch multiplication spacers and methods of forming the same |
US7572572B2 (en) | 2005-09-01 | 2009-08-11 | Micron Technology, Inc. | Methods for forming arrays of small, closely spaced features |
US7393789B2 (en) | 2005-09-01 | 2008-07-01 | Micron Technology, Inc. | Protective coating for planarization |
WO2007064358A2 (en) * | 2005-09-30 | 2007-06-07 | Virgin Islands Microsystems, Inc. | Structures and methods for coupling energy from an electromagnetic wave |
US7557025B2 (en) * | 2005-11-04 | 2009-07-07 | United Microelectronics Corp. | Method of etching a dielectric layer to form a contact hole and a via hole and damascene method |
US7470920B2 (en) * | 2006-01-05 | 2008-12-30 | Virgin Islands Microsystems, Inc. | Resonant structure-based display |
US20070152781A1 (en) * | 2006-01-05 | 2007-07-05 | Virgin Islands Microsystems, Inc. | Switching micro-resonant structures by modulating a beam of charged particles |
JP4693642B2 (en) * | 2006-01-30 | 2011-06-01 | 株式会社東芝 | Semiconductor device manufacturing method and cleaning apparatus |
US7282776B2 (en) * | 2006-02-09 | 2007-10-16 | Virgin Islands Microsystems, Inc. | Method and structure for coupling two microcircuits |
US20070196792A1 (en) * | 2006-02-21 | 2007-08-23 | Johnson Jason K | Prefabricated Dental Crowns |
US20090286205A1 (en) * | 2006-02-21 | 2009-11-19 | Johnson Jason K | Prefabricated Dental Crowns |
US20070200071A1 (en) * | 2006-02-28 | 2007-08-30 | Virgin Islands Microsystems, Inc. | Coupling output from a micro resonator to a plasmon transmission line |
US7443358B2 (en) * | 2006-02-28 | 2008-10-28 | Virgin Island Microsystems, Inc. | Integrated filter in antenna-based detector |
US7842558B2 (en) | 2006-03-02 | 2010-11-30 | Micron Technology, Inc. | Masking process for simultaneously patterning separate regions |
US7476933B2 (en) | 2006-03-02 | 2009-01-13 | Micron Technology, Inc. | Vertical gated access transistor |
US7902074B2 (en) | 2006-04-07 | 2011-03-08 | Micron Technology, Inc. | Simplified pitch doubling process flow |
US8003310B2 (en) | 2006-04-24 | 2011-08-23 | Micron Technology, Inc. | Masking techniques and templates for dense semiconductor fabrication |
US7488685B2 (en) | 2006-04-25 | 2009-02-10 | Micron Technology, Inc. | Process for improving critical dimension uniformity of integrated circuit arrays |
US7492868B2 (en) * | 2006-04-26 | 2009-02-17 | Virgin Islands Microsystems, Inc. | Source of x-rays |
US7876793B2 (en) | 2006-04-26 | 2011-01-25 | Virgin Islands Microsystems, Inc. | Micro free electron laser (FEL) |
US7646991B2 (en) | 2006-04-26 | 2010-01-12 | Virgin Island Microsystems, Inc. | Selectable frequency EMR emitter |
US7436177B2 (en) * | 2006-05-05 | 2008-10-14 | Virgin Islands Microsystems, Inc. | SEM test apparatus |
US7728702B2 (en) | 2006-05-05 | 2010-06-01 | Virgin Islands Microsystems, Inc. | Shielding of integrated circuit package with high-permeability magnetic material |
US7986113B2 (en) | 2006-05-05 | 2011-07-26 | Virgin Islands Microsystems, Inc. | Selectable frequency light emitter |
US7746532B2 (en) | 2006-05-05 | 2010-06-29 | Virgin Island Microsystems, Inc. | Electro-optical switching system and method |
US20070258675A1 (en) * | 2006-05-05 | 2007-11-08 | Virgin Islands Microsystems, Inc. | Multiplexed optical communication between chips on a multi-chip module |
US7718977B2 (en) * | 2006-05-05 | 2010-05-18 | Virgin Island Microsystems, Inc. | Stray charged particle removal device |
US7342441B2 (en) * | 2006-05-05 | 2008-03-11 | Virgin Islands Microsystems, Inc. | Heterodyne receiver array using resonant structures |
US7656094B2 (en) * | 2006-05-05 | 2010-02-02 | Virgin Islands Microsystems, Inc. | Electron accelerator for ultra-small resonant structures |
US8188431B2 (en) | 2006-05-05 | 2012-05-29 | Jonathan Gorrell | Integration of vacuum microelectronic device with integrated circuit |
US7728397B2 (en) * | 2006-05-05 | 2010-06-01 | Virgin Islands Microsystems, Inc. | Coupled nano-resonating energy emitting structures |
US20070258492A1 (en) * | 2006-05-05 | 2007-11-08 | Virgin Islands Microsystems, Inc. | Light-emitting resonant structure driving raman laser |
US7442940B2 (en) * | 2006-05-05 | 2008-10-28 | Virgin Island Microsystems, Inc. | Focal plane array incorporating ultra-small resonant structures |
US7359589B2 (en) * | 2006-05-05 | 2008-04-15 | Virgin Islands Microsystems, Inc. | Coupling electromagnetic wave through microcircuit |
US7476907B2 (en) * | 2006-05-05 | 2009-01-13 | Virgin Island Microsystems, Inc. | Plated multi-faceted reflector |
US7732786B2 (en) | 2006-05-05 | 2010-06-08 | Virgin Islands Microsystems, Inc. | Coupling energy in a plasmon wave to an electron beam |
US7741934B2 (en) | 2006-05-05 | 2010-06-22 | Virgin Islands Microsystems, Inc. | Coupling a signal through a window |
US20070258720A1 (en) * | 2006-05-05 | 2007-11-08 | Virgin Islands Microsystems, Inc. | Inter-chip optical communication |
US7723698B2 (en) * | 2006-05-05 | 2010-05-25 | Virgin Islands Microsystems, Inc. | Top metal layer shield for ultra-small resonant structures |
US7710040B2 (en) | 2006-05-05 | 2010-05-04 | Virgin Islands Microsystems, Inc. | Single layer construction for ultra small devices |
US7443577B2 (en) * | 2006-05-05 | 2008-10-28 | Virgin Islands Microsystems, Inc. | Reflecting filtering cover |
US7679067B2 (en) | 2006-05-26 | 2010-03-16 | Virgin Island Microsystems, Inc. | Receiver array using shared electron beam |
US20070274365A1 (en) * | 2006-05-26 | 2007-11-29 | Virgin Islands Microsystems, Inc. | Periodically complex resonant structures |
US7795149B2 (en) * | 2006-06-01 | 2010-09-14 | Micron Technology, Inc. | Masking techniques and contact imprint reticles for dense semiconductor fabrication |
US7723009B2 (en) | 2006-06-02 | 2010-05-25 | Micron Technology, Inc. | Topography based patterning |
US20070286954A1 (en) * | 2006-06-13 | 2007-12-13 | Applied Materials, Inc. | Methods for low temperature deposition of an amorphous carbon layer |
US7655934B2 (en) * | 2006-06-28 | 2010-02-02 | Virgin Island Microsystems, Inc. | Data on light bulb |
CN100570485C (en) * | 2006-07-07 | 2009-12-16 | 中国科学院半导体研究所 | Two-dimensional nanostructure deep etching method |
US7611980B2 (en) | 2006-08-30 | 2009-11-03 | Micron Technology, Inc. | Single spacer process for multiplying pitch by a factor greater than two and related intermediate IC structures |
US7666578B2 (en) | 2006-09-14 | 2010-02-23 | Micron Technology, Inc. | Efficient pitch multiplication process |
US7450794B2 (en) * | 2006-09-19 | 2008-11-11 | Virgin Islands Microsystems, Inc. | Microcircuit using electromagnetic wave routing |
KR100944846B1 (en) * | 2006-10-30 | 2010-03-04 | 어플라이드 머티어리얼스, 인코포레이티드 | Mask etch process |
US7659513B2 (en) | 2006-12-20 | 2010-02-09 | Virgin Islands Microsystems, Inc. | Low terahertz source and detector |
US20080242072A1 (en) * | 2007-03-26 | 2008-10-02 | Texas Instruments Incorporated | Plasma dry etch process for metal-containing gates |
US20080254233A1 (en) * | 2007-04-10 | 2008-10-16 | Kwangduk Douglas Lee | Plasma-induced charge damage control for plasma enhanced chemical vapor deposition processes |
US7923373B2 (en) | 2007-06-04 | 2011-04-12 | Micron Technology, Inc. | Pitch multiplication using self-assembling materials |
US7990336B2 (en) | 2007-06-19 | 2011-08-02 | Virgin Islands Microsystems, Inc. | Microwave coupled excitation of solid state resonant arrays |
US8563229B2 (en) | 2007-07-31 | 2013-10-22 | Micron Technology, Inc. | Process of semiconductor fabrication with mask overlay on pitch multiplied features and associated structures |
US20090093128A1 (en) * | 2007-10-08 | 2009-04-09 | Martin Jay Seamons | Methods for high temperature deposition of an amorphous carbon layer |
US7791053B2 (en) | 2007-10-10 | 2010-09-07 | Virgin Islands Microsystems, Inc. | Depressed anode with plasmon-enabled devices such as ultra-small resonant structures |
US7737039B2 (en) | 2007-11-01 | 2010-06-15 | Micron Technology, Inc. | Spacer process for on pitch contacts and related structures |
US7659208B2 (en) | 2007-12-06 | 2010-02-09 | Micron Technology, Inc | Method for forming high density patterns |
US7790531B2 (en) | 2007-12-18 | 2010-09-07 | Micron Technology, Inc. | Methods for isolating portions of a loop of pitch-multiplied material and related structures |
US7795073B2 (en) | 2008-02-01 | 2010-09-14 | Hynix Semiconductor Inc. | Method for manufacturing stack package using through-electrodes |
KR101013556B1 (en) * | 2008-02-01 | 2011-02-14 | 주식회사 하이닉스반도체 | Method for fabricating stack package |
US8030218B2 (en) * | 2008-03-21 | 2011-10-04 | Micron Technology, Inc. | Method for selectively modifying spacing between pitch multiplied structures |
US20090269923A1 (en) * | 2008-04-25 | 2009-10-29 | Lee Sang M | Adhesion and electromigration improvement between dielectric and conductive layers |
US8076208B2 (en) | 2008-07-03 | 2011-12-13 | Micron Technology, Inc. | Method for forming transistor with high breakdown voltage using pitch multiplication technique |
US8492282B2 (en) | 2008-11-24 | 2013-07-23 | Micron Technology, Inc. | Methods of forming a masking pattern for integrated circuits |
US9324576B2 (en) | 2010-05-27 | 2016-04-26 | Applied Materials, Inc. | Selective etch for silicon films |
US8741778B2 (en) | 2010-12-14 | 2014-06-03 | Applied Materials, Inc. | Uniform dry etch in two stages |
US10283321B2 (en) | 2011-01-18 | 2019-05-07 | Applied Materials, Inc. | Semiconductor processing system and methods using capacitively coupled plasma |
US8771539B2 (en) | 2011-02-22 | 2014-07-08 | Applied Materials, Inc. | Remotely-excited fluorine and water vapor etch |
US9293319B2 (en) | 2011-03-09 | 2016-03-22 | Micron Technology, Inc. | Removal of metal |
US8999856B2 (en) | 2011-03-14 | 2015-04-07 | Applied Materials, Inc. | Methods for etch of sin films |
US9064815B2 (en) | 2011-03-14 | 2015-06-23 | Applied Materials, Inc. | Methods for etch of metal and metal-oxide films |
US9653327B2 (en) | 2011-05-12 | 2017-05-16 | Applied Materials, Inc. | Methods of removing a material layer from a substrate using water vapor treatment |
US8771536B2 (en) * | 2011-08-01 | 2014-07-08 | Applied Materials, Inc. | Dry-etch for silicon-and-carbon-containing films |
US8679982B2 (en) | 2011-08-26 | 2014-03-25 | Applied Materials, Inc. | Selective suppression of dry-etch rate of materials containing both silicon and oxygen |
US8679983B2 (en) | 2011-09-01 | 2014-03-25 | Applied Materials, Inc. | Selective suppression of dry-etch rate of materials containing both silicon and nitrogen |
US8927390B2 (en) | 2011-09-26 | 2015-01-06 | Applied Materials, Inc. | Intrench profile |
US8808563B2 (en) | 2011-10-07 | 2014-08-19 | Applied Materials, Inc. | Selective etch of silicon by way of metastable hydrogen termination |
WO2013070436A1 (en) | 2011-11-08 | 2013-05-16 | Applied Materials, Inc. | Methods of reducing substrate dislocation during gapfill processing |
US9267739B2 (en) | 2012-07-18 | 2016-02-23 | Applied Materials, Inc. | Pedestal with multi-zone temperature control and multiple purge capabilities |
US9373517B2 (en) | 2012-08-02 | 2016-06-21 | Applied Materials, Inc. | Semiconductor processing with DC assisted RF power for improved control |
US9034770B2 (en) | 2012-09-17 | 2015-05-19 | Applied Materials, Inc. | Differential silicon oxide etch |
US9023734B2 (en) | 2012-09-18 | 2015-05-05 | Applied Materials, Inc. | Radical-component oxide etch |
US9390937B2 (en) | 2012-09-20 | 2016-07-12 | Applied Materials, Inc. | Silicon-carbon-nitride selective etch |
US9132436B2 (en) | 2012-09-21 | 2015-09-15 | Applied Materials, Inc. | Chemical control features in wafer process equipment |
US8765574B2 (en) | 2012-11-09 | 2014-07-01 | Applied Materials, Inc. | Dry etch process |
US8969212B2 (en) | 2012-11-20 | 2015-03-03 | Applied Materials, Inc. | Dry-etch selectivity |
US9064816B2 (en) | 2012-11-30 | 2015-06-23 | Applied Materials, Inc. | Dry-etch for selective oxidation removal |
US8980763B2 (en) | 2012-11-30 | 2015-03-17 | Applied Materials, Inc. | Dry-etch for selective tungsten removal |
US9111877B2 (en) | 2012-12-18 | 2015-08-18 | Applied Materials, Inc. | Non-local plasma oxide etch |
US8921234B2 (en) | 2012-12-21 | 2014-12-30 | Applied Materials, Inc. | Selective titanium nitride etching |
US10256079B2 (en) | 2013-02-08 | 2019-04-09 | Applied Materials, Inc. | Semiconductor processing systems having multiple plasma configurations |
US9362130B2 (en) | 2013-03-01 | 2016-06-07 | Applied Materials, Inc. | Enhanced etching processes using remote plasma sources |
JP6041709B2 (en) * | 2013-03-05 | 2016-12-14 | 東京エレクトロン株式会社 | Method for etching a metal layer |
US9040422B2 (en) | 2013-03-05 | 2015-05-26 | Applied Materials, Inc. | Selective titanium nitride removal |
US8801952B1 (en) | 2013-03-07 | 2014-08-12 | Applied Materials, Inc. | Conformal oxide dry etch |
US10170282B2 (en) | 2013-03-08 | 2019-01-01 | Applied Materials, Inc. | Insulated semiconductor faceplate designs |
US20140271097A1 (en) | 2013-03-15 | 2014-09-18 | Applied Materials, Inc. | Processing systems and methods for halide scavenging |
US8895449B1 (en) | 2013-05-16 | 2014-11-25 | Applied Materials, Inc. | Delicate dry clean |
US9114438B2 (en) | 2013-05-21 | 2015-08-25 | Applied Materials, Inc. | Copper residue chamber clean |
US9493879B2 (en) | 2013-07-12 | 2016-11-15 | Applied Materials, Inc. | Selective sputtering for pattern transfer |
US9773648B2 (en) | 2013-08-30 | 2017-09-26 | Applied Materials, Inc. | Dual discharge modes operation for remote plasma |
US8956980B1 (en) | 2013-09-16 | 2015-02-17 | Applied Materials, Inc. | Selective etch of silicon nitride |
US8951429B1 (en) | 2013-10-29 | 2015-02-10 | Applied Materials, Inc. | Tungsten oxide processing |
US9236265B2 (en) | 2013-11-04 | 2016-01-12 | Applied Materials, Inc. | Silicon germanium processing |
US9576809B2 (en) | 2013-11-04 | 2017-02-21 | Applied Materials, Inc. | Etch suppression with germanium |
US9520303B2 (en) | 2013-11-12 | 2016-12-13 | Applied Materials, Inc. | Aluminum selective etch |
US9245762B2 (en) | 2013-12-02 | 2016-01-26 | Applied Materials, Inc. | Procedure for etch rate consistency |
US9117855B2 (en) | 2013-12-04 | 2015-08-25 | Applied Materials, Inc. | Polarity control for remote plasma |
US9263278B2 (en) | 2013-12-17 | 2016-02-16 | Applied Materials, Inc. | Dopant etch selectivity control |
US9287095B2 (en) | 2013-12-17 | 2016-03-15 | Applied Materials, Inc. | Semiconductor system assemblies and methods of operation |
US9190293B2 (en) | 2013-12-18 | 2015-11-17 | Applied Materials, Inc. | Even tungsten etch for high aspect ratio trenches |
US9287134B2 (en) | 2014-01-17 | 2016-03-15 | Applied Materials, Inc. | Titanium oxide etch |
US9396989B2 (en) | 2014-01-27 | 2016-07-19 | Applied Materials, Inc. | Air gaps between copper lines |
US9293568B2 (en) | 2014-01-27 | 2016-03-22 | Applied Materials, Inc. | Method of fin patterning |
US9385028B2 (en) | 2014-02-03 | 2016-07-05 | Applied Materials, Inc. | Air gap process |
US9598907B2 (en) | 2014-02-28 | 2017-03-21 | Diamond Innovations Inc. | Modification of diamond feeds for improving polycrystalline diamond cutter |
US9499898B2 (en) | 2014-03-03 | 2016-11-22 | Applied Materials, Inc. | Layered thin film heater and method of fabrication |
KR101870491B1 (en) * | 2014-03-11 | 2018-06-22 | 도쿄엘렉트론가부시키가이샤 | Plasma processing appratus, substrate processing system, fabrication method of thin film transistor, and storage medium |
US9508561B2 (en) | 2014-03-11 | 2016-11-29 | Applied Materials, Inc. | Methods for forming interconnection structures in an integrated cluster system for semicondcutor applications |
US9299575B2 (en) | 2014-03-17 | 2016-03-29 | Applied Materials, Inc. | Gas-phase tungsten etch |
US9299538B2 (en) | 2014-03-20 | 2016-03-29 | Applied Materials, Inc. | Radial waveguide systems and methods for post-match control of microwaves |
US9299537B2 (en) | 2014-03-20 | 2016-03-29 | Applied Materials, Inc. | Radial waveguide systems and methods for post-match control of microwaves |
US9136273B1 (en) | 2014-03-21 | 2015-09-15 | Applied Materials, Inc. | Flash gate air gap |
US9903020B2 (en) | 2014-03-31 | 2018-02-27 | Applied Materials, Inc. | Generation of compact alumina passivation layers on aluminum plasma equipment components |
US9269590B2 (en) | 2014-04-07 | 2016-02-23 | Applied Materials, Inc. | Spacer formation |
US9309598B2 (en) | 2014-05-28 | 2016-04-12 | Applied Materials, Inc. | Oxide and metal removal |
US9847289B2 (en) | 2014-05-30 | 2017-12-19 | Applied Materials, Inc. | Protective via cap for improved interconnect performance |
US9406523B2 (en) | 2014-06-19 | 2016-08-02 | Applied Materials, Inc. | Highly selective doped oxide removal method |
US9378969B2 (en) | 2014-06-19 | 2016-06-28 | Applied Materials, Inc. | Low temperature gas-phase carbon removal |
US9425058B2 (en) | 2014-07-24 | 2016-08-23 | Applied Materials, Inc. | Simplified litho-etch-litho-etch process |
US9159606B1 (en) | 2014-07-31 | 2015-10-13 | Applied Materials, Inc. | Metal air gap |
US9378978B2 (en) | 2014-07-31 | 2016-06-28 | Applied Materials, Inc. | Integrated oxide recess and floating gate fin trimming |
US9496167B2 (en) | 2014-07-31 | 2016-11-15 | Applied Materials, Inc. | Integrated bit-line airgap formation and gate stack post clean |
US9165786B1 (en) | 2014-08-05 | 2015-10-20 | Applied Materials, Inc. | Integrated oxide and nitride recess for better channel contact in 3D architectures |
US9659753B2 (en) | 2014-08-07 | 2017-05-23 | Applied Materials, Inc. | Grooved insulator to reduce leakage current |
US9553102B2 (en) | 2014-08-19 | 2017-01-24 | Applied Materials, Inc. | Tungsten separation |
KR20230051311A (en) | 2014-09-12 | 2023-04-17 | 어플라이드 머티어리얼스, 인코포레이티드 | Controller for treatment of semiconductor processing equipment effluent |
US9355856B2 (en) | 2014-09-12 | 2016-05-31 | Applied Materials, Inc. | V trench dry etch |
US9355862B2 (en) | 2014-09-24 | 2016-05-31 | Applied Materials, Inc. | Fluorine-based hardmask removal |
US9368364B2 (en) | 2014-09-24 | 2016-06-14 | Applied Materials, Inc. | Silicon etch process with tunable selectivity to SiO2 and other materials |
US9613822B2 (en) | 2014-09-25 | 2017-04-04 | Applied Materials, Inc. | Oxide etch selectivity enhancement |
US9570320B2 (en) * | 2014-10-09 | 2017-02-14 | Lam Research Corporation | Method to etch copper barrier film |
US9355922B2 (en) | 2014-10-14 | 2016-05-31 | Applied Materials, Inc. | Systems and methods for internal surface conditioning in plasma processing equipment |
US9966240B2 (en) | 2014-10-14 | 2018-05-08 | Applied Materials, Inc. | Systems and methods for internal surface conditioning assessment in plasma processing equipment |
GB201420245D0 (en) * | 2014-11-14 | 2014-12-31 | Bae Systems Plc | Sensor manufacture |
US11637002B2 (en) | 2014-11-26 | 2023-04-25 | Applied Materials, Inc. | Methods and systems to enhance process uniformity |
US9299583B1 (en) | 2014-12-05 | 2016-03-29 | Applied Materials, Inc. | Aluminum oxide selective etch |
US10224210B2 (en) | 2014-12-09 | 2019-03-05 | Applied Materials, Inc. | Plasma processing system with direct outlet toroidal plasma source |
US10573496B2 (en) | 2014-12-09 | 2020-02-25 | Applied Materials, Inc. | Direct outlet toroidal plasma source |
US9502258B2 (en) | 2014-12-23 | 2016-11-22 | Applied Materials, Inc. | Anisotropic gap etch |
US9343272B1 (en) | 2015-01-08 | 2016-05-17 | Applied Materials, Inc. | Self-aligned process |
US11257693B2 (en) | 2015-01-09 | 2022-02-22 | Applied Materials, Inc. | Methods and systems to improve pedestal temperature control |
US9373522B1 (en) | 2015-01-22 | 2016-06-21 | Applied Mateials, Inc. | Titanium nitride removal |
US9449846B2 (en) | 2015-01-28 | 2016-09-20 | Applied Materials, Inc. | Vertical gate separation |
US9728437B2 (en) | 2015-02-03 | 2017-08-08 | Applied Materials, Inc. | High temperature chuck for plasma processing systems |
US20160225652A1 (en) | 2015-02-03 | 2016-08-04 | Applied Materials, Inc. | Low temperature chuck for plasma processing systems |
US9881805B2 (en) | 2015-03-02 | 2018-01-30 | Applied Materials, Inc. | Silicon selective removal |
US9741593B2 (en) | 2015-08-06 | 2017-08-22 | Applied Materials, Inc. | Thermal management systems and methods for wafer processing systems |
US9691645B2 (en) | 2015-08-06 | 2017-06-27 | Applied Materials, Inc. | Bolted wafer chuck thermal management systems and methods for wafer processing systems |
US9349605B1 (en) | 2015-08-07 | 2016-05-24 | Applied Materials, Inc. | Oxide etch selectivity systems and methods |
US10504700B2 (en) | 2015-08-27 | 2019-12-10 | Applied Materials, Inc. | Plasma etching systems and methods with secondary plasma injection |
US10504754B2 (en) | 2016-05-19 | 2019-12-10 | Applied Materials, Inc. | Systems and methods for improved semiconductor etching and component protection |
US10522371B2 (en) | 2016-05-19 | 2019-12-31 | Applied Materials, Inc. | Systems and methods for improved semiconductor etching and component protection |
US9865484B1 (en) | 2016-06-29 | 2018-01-09 | Applied Materials, Inc. | Selective etch using material modification and RF pulsing |
US10062575B2 (en) | 2016-09-09 | 2018-08-28 | Applied Materials, Inc. | Poly directional etch by oxidation |
US10629473B2 (en) | 2016-09-09 | 2020-04-21 | Applied Materials, Inc. | Footing removal for nitride spacer |
US9934942B1 (en) | 2016-10-04 | 2018-04-03 | Applied Materials, Inc. | Chamber with flow-through source |
US9721789B1 (en) | 2016-10-04 | 2017-08-01 | Applied Materials, Inc. | Saving ion-damaged spacers |
US10062585B2 (en) | 2016-10-04 | 2018-08-28 | Applied Materials, Inc. | Oxygen compatible plasma source |
US10546729B2 (en) | 2016-10-04 | 2020-01-28 | Applied Materials, Inc. | Dual-channel showerhead with improved profile |
US10062579B2 (en) | 2016-10-07 | 2018-08-28 | Applied Materials, Inc. | Selective SiN lateral recess |
US9947549B1 (en) | 2016-10-10 | 2018-04-17 | Applied Materials, Inc. | Cobalt-containing material removal |
US9768034B1 (en) | 2016-11-11 | 2017-09-19 | Applied Materials, Inc. | Removal methods for high aspect ratio structures |
US10163696B2 (en) | 2016-11-11 | 2018-12-25 | Applied Materials, Inc. | Selective cobalt removal for bottom up gapfill |
US10242908B2 (en) | 2016-11-14 | 2019-03-26 | Applied Materials, Inc. | Airgap formation with damage-free copper |
US10026621B2 (en) | 2016-11-14 | 2018-07-17 | Applied Materials, Inc. | SiN spacer profile patterning |
US10566206B2 (en) | 2016-12-27 | 2020-02-18 | Applied Materials, Inc. | Systems and methods for anisotropic material breakthrough |
US10403507B2 (en) | 2017-02-03 | 2019-09-03 | Applied Materials, Inc. | Shaped etch profile with oxidation |
US10431429B2 (en) | 2017-02-03 | 2019-10-01 | Applied Materials, Inc. | Systems and methods for radial and azimuthal control of plasma uniformity |
US10043684B1 (en) | 2017-02-06 | 2018-08-07 | Applied Materials, Inc. | Self-limiting atomic thermal etching systems and methods |
US10319739B2 (en) | 2017-02-08 | 2019-06-11 | Applied Materials, Inc. | Accommodating imperfectly aligned memory holes |
US10943834B2 (en) | 2017-03-13 | 2021-03-09 | Applied Materials, Inc. | Replacement contact process |
US10319649B2 (en) | 2017-04-11 | 2019-06-11 | Applied Materials, Inc. | Optical emission spectroscopy (OES) for remote plasma monitoring |
US11276559B2 (en) | 2017-05-17 | 2022-03-15 | Applied Materials, Inc. | Semiconductor processing chamber for multiple precursor flow |
US11276590B2 (en) | 2017-05-17 | 2022-03-15 | Applied Materials, Inc. | Multi-zone semiconductor substrate supports |
US10497579B2 (en) | 2017-05-31 | 2019-12-03 | Applied Materials, Inc. | Water-free etching methods |
US10049891B1 (en) | 2017-05-31 | 2018-08-14 | Applied Materials, Inc. | Selective in situ cobalt residue removal |
US10920320B2 (en) | 2017-06-16 | 2021-02-16 | Applied Materials, Inc. | Plasma health determination in semiconductor substrate processing reactors |
US10541246B2 (en) | 2017-06-26 | 2020-01-21 | Applied Materials, Inc. | 3D flash memory cells which discourage cross-cell electrical tunneling |
US10727080B2 (en) | 2017-07-07 | 2020-07-28 | Applied Materials, Inc. | Tantalum-containing material removal |
US10541184B2 (en) | 2017-07-11 | 2020-01-21 | Applied Materials, Inc. | Optical emission spectroscopic techniques for monitoring etching |
US10354889B2 (en) | 2017-07-17 | 2019-07-16 | Applied Materials, Inc. | Non-halogen etching of silicon-containing materials |
US10170336B1 (en) | 2017-08-04 | 2019-01-01 | Applied Materials, Inc. | Methods for anisotropic control of selective silicon removal |
US10043674B1 (en) | 2017-08-04 | 2018-08-07 | Applied Materials, Inc. | Germanium etching systems and methods |
US10297458B2 (en) | 2017-08-07 | 2019-05-21 | Applied Materials, Inc. | Process window widening using coated parts in plasma etch processes |
KR102403619B1 (en) * | 2017-09-18 | 2022-05-30 | 삼성전자주식회사 | Semiconductor device and method for manufacturing the same |
CN107422403B (en) * | 2017-09-21 | 2019-12-03 | 京东方科技集团股份有限公司 | For controlling the optical component and its manufacturing method of light exit direction |
US10128086B1 (en) | 2017-10-24 | 2018-11-13 | Applied Materials, Inc. | Silicon pretreatment for nitride removal |
US10283324B1 (en) | 2017-10-24 | 2019-05-07 | Applied Materials, Inc. | Oxygen treatment for nitride etching |
US10256112B1 (en) | 2017-12-08 | 2019-04-09 | Applied Materials, Inc. | Selective tungsten removal |
US10903054B2 (en) | 2017-12-19 | 2021-01-26 | Applied Materials, Inc. | Multi-zone gas distribution systems and methods |
US11328909B2 (en) | 2017-12-22 | 2022-05-10 | Applied Materials, Inc. | Chamber conditioning and removal processes |
US10854426B2 (en) | 2018-01-08 | 2020-12-01 | Applied Materials, Inc. | Metal recess for semiconductor structures |
US10964512B2 (en) | 2018-02-15 | 2021-03-30 | Applied Materials, Inc. | Semiconductor processing chamber multistage mixing apparatus and methods |
US10679870B2 (en) | 2018-02-15 | 2020-06-09 | Applied Materials, Inc. | Semiconductor processing chamber multistage mixing apparatus |
US10804106B2 (en) | 2018-02-21 | 2020-10-13 | International Business Machines Corporation | High temperature ultra-fast annealed soft mask for semiconductor devices |
TWI766433B (en) | 2018-02-28 | 2022-06-01 | 美商應用材料股份有限公司 | Systems and methods to form airgaps |
US10593560B2 (en) | 2018-03-01 | 2020-03-17 | Applied Materials, Inc. | Magnetic induction plasma source for semiconductor processes and equipment |
US10319600B1 (en) | 2018-03-12 | 2019-06-11 | Applied Materials, Inc. | Thermal silicon etch |
US10497573B2 (en) | 2018-03-13 | 2019-12-03 | Applied Materials, Inc. | Selective atomic layer etching of semiconductor materials |
US10573527B2 (en) | 2018-04-06 | 2020-02-25 | Applied Materials, Inc. | Gas-phase selective etching systems and methods |
US10490406B2 (en) | 2018-04-10 | 2019-11-26 | Appled Materials, Inc. | Systems and methods for material breakthrough |
US10699879B2 (en) | 2018-04-17 | 2020-06-30 | Applied Materials, Inc. | Two piece electrode assembly with gap for plasma control |
US10886137B2 (en) | 2018-04-30 | 2021-01-05 | Applied Materials, Inc. | Selective nitride removal |
US10755941B2 (en) | 2018-07-06 | 2020-08-25 | Applied Materials, Inc. | Self-limiting selective etching systems and methods |
US10872778B2 (en) | 2018-07-06 | 2020-12-22 | Applied Materials, Inc. | Systems and methods utilizing solid-phase etchants |
US10672642B2 (en) | 2018-07-24 | 2020-06-02 | Applied Materials, Inc. | Systems and methods for pedestal configuration |
US10892198B2 (en) | 2018-09-14 | 2021-01-12 | Applied Materials, Inc. | Systems and methods for improved performance in semiconductor processing |
US11049755B2 (en) | 2018-09-14 | 2021-06-29 | Applied Materials, Inc. | Semiconductor substrate supports with embedded RF shield |
US11062887B2 (en) | 2018-09-17 | 2021-07-13 | Applied Materials, Inc. | High temperature RF heater pedestals |
US11417534B2 (en) | 2018-09-21 | 2022-08-16 | Applied Materials, Inc. | Selective material removal |
US11682560B2 (en) | 2018-10-11 | 2023-06-20 | Applied Materials, Inc. | Systems and methods for hafnium-containing film removal |
US11121002B2 (en) | 2018-10-24 | 2021-09-14 | Applied Materials, Inc. | Systems and methods for etching metals and metal derivatives |
US11437242B2 (en) | 2018-11-27 | 2022-09-06 | Applied Materials, Inc. | Selective removal of silicon-containing materials |
US11721527B2 (en) | 2019-01-07 | 2023-08-08 | Applied Materials, Inc. | Processing chamber mixing systems |
US10920319B2 (en) | 2019-01-11 | 2021-02-16 | Applied Materials, Inc. | Ceramic showerheads with conductive electrodes |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4863557A (en) * | 1987-05-29 | 1989-09-05 | Yuuichi Kokaku | Pattern forming process and thin-film magnetic head formed by said process |
EP0531232A2 (en) * | 1991-08-26 | 1993-03-10 | Eastman Kodak Company | High durability mask for use in selective area, epitaxial regrowth of GaAs |
US5445710A (en) * | 1991-01-22 | 1995-08-29 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
US5578166A (en) * | 1993-05-17 | 1996-11-26 | Fujitsu Limited | Method of reactive ion etching of a thin copper film |
Family Cites Families (44)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4256534A (en) * | 1978-07-31 | 1981-03-17 | Bell Telephone Laboratories, Incorporated | Device fabrication by plasma etching |
US4447824A (en) * | 1980-08-18 | 1984-05-08 | International Business Machines Corporation | Planar multi-level metal process with built-in etch stop |
JPS5916978A (en) * | 1982-07-20 | 1984-01-28 | Tokyo Denshi Kagaku Kabushiki | Method for selectively etching metal coating |
US4440804A (en) * | 1982-08-02 | 1984-04-03 | Fairchild Camera & Instrument Corporation | Lift-off process for fabricating self-aligned contacts |
US4444618A (en) * | 1983-03-03 | 1984-04-24 | General Electric Company | Processes and gas mixtures for the reactive ion etching of aluminum and aluminum alloys |
DE3376186D1 (en) * | 1983-08-02 | 1988-05-05 | Ibm Deutschland | Dry-etching process and its use |
US4519872A (en) * | 1984-06-11 | 1985-05-28 | International Business Machines Corporation | Use of depolymerizable polymers in the fabrication of lift-off structure for multilevel metal processes |
ATE68912T1 (en) * | 1985-09-27 | 1991-11-15 | Unisys Corp | PROCEDURE FOR MAKING A TAPERED CONTACT OPENING IN POLYIMIDE. |
US5067002A (en) * | 1987-01-30 | 1991-11-19 | Motorola, Inc. | Integrated circuit structures having polycrystalline electrode contacts |
US4966865A (en) * | 1987-02-05 | 1990-10-30 | Texas Instruments Incorporated | Method for planarization of a semiconductor device prior to metallization |
US4753709A (en) * | 1987-02-05 | 1988-06-28 | Texas Instuments Incorporated | Method for etching contact vias in a semiconductor device |
US5110712A (en) * | 1987-06-12 | 1992-05-05 | Hewlett-Packard Company | Incorporation of dielectric layers in a semiconductor |
US5298112A (en) * | 1987-08-28 | 1994-03-29 | Kabushiki Kaisha Toshiba | Method for removing composite attached to material by dry etching |
JPH01234578A (en) * | 1988-03-16 | 1989-09-19 | Hitachi Ltd | Dry etching method for thin copper film |
JPH0787053B2 (en) * | 1989-02-06 | 1995-09-20 | 日本電信電話株式会社 | Copper thin film patterning method |
JP2732663B2 (en) * | 1989-05-10 | 1998-03-30 | 日本電信電話株式会社 | Copper thin film patterning method |
US5186718A (en) * | 1989-05-19 | 1993-02-16 | Applied Materials, Inc. | Staged-vacuum wafer processing system and method |
US5141817A (en) * | 1989-06-13 | 1992-08-25 | International Business Machines Corporation | Dielectric structures having embedded gap filling RIE etch stop polymeric materials of high thermal stability |
JPH0336723A (en) * | 1989-07-04 | 1991-02-18 | Fujitsu Ltd | Manufacture of semiconductor device and electronic cyclotron resonant etching device |
US5053105A (en) * | 1990-07-19 | 1991-10-01 | Micron Technology, Inc. | Process for creating an etch mask suitable for deep plasma etches employing self-aligned silicidation of a metal layer masked with a silicon dioxide template |
JP3077178B2 (en) * | 1990-08-11 | 2000-08-14 | ソニー株式会社 | Selective dry etching method for copper thin film |
JPH04173988A (en) * | 1990-11-02 | 1992-06-22 | Nissin Electric Co Ltd | Dry etching method |
JPH04187787A (en) * | 1990-11-20 | 1992-07-06 | Nisshin Hightech Kk | Dry etching method |
JPH04199821A (en) * | 1990-11-29 | 1992-07-21 | Nisshin Hightech Kk | Dry etching equipment |
JPH04199824A (en) * | 1990-11-29 | 1992-07-21 | Nisshin Hightech Kk | Method of dry etching |
US5183972A (en) * | 1991-02-04 | 1993-02-02 | Microelectronics And Computer Technology Corporation | Copper/epoxy structures |
DE4107006A1 (en) * | 1991-03-05 | 1992-09-10 | Siemens Ag | METHOD FOR ANISOTROPICALLY DRYING ALUMINUM OR BZW. ALUMINUM ALLOYS CONTAINING LADDER RAILINGS IN INTEGRATED SEMICONDUCTOR CIRCUITS |
JPH04329640A (en) * | 1991-05-01 | 1992-11-18 | Mitsubishi Electric Corp | Method of dry etching for wiring layer |
JPH04350939A (en) * | 1991-05-29 | 1992-12-04 | Sony Corp | Method of forming copper wiring |
JP3371143B2 (en) * | 1991-06-03 | 2003-01-27 | ソニー株式会社 | Dry etching method |
US5476753A (en) * | 1991-07-22 | 1995-12-19 | Matsushita Electric Industrial Co., Ltd. | Fine pattern forming method |
US5286344A (en) * | 1992-06-15 | 1994-02-15 | Micron Technology, Inc. | Process for selectively etching a layer of silicon dioxide on an underlying stop layer of silicon nitride |
DE4223887A1 (en) * | 1992-07-21 | 1994-01-27 | Basf Ag | Process for producing a polymer / metal or polymer / semiconductor composite |
JPH06151382A (en) * | 1992-11-11 | 1994-05-31 | Toshiba Corp | Dry etching method |
US5346586A (en) * | 1992-12-23 | 1994-09-13 | Micron Semiconductor, Inc. | Method for selectively etching polysilicon to gate oxide using an insitu ozone photoresist strip |
US5387556A (en) * | 1993-02-24 | 1995-02-07 | Applied Materials, Inc. | Etching aluminum and its alloys using HC1, C1-containing etchant and N.sub.2 |
JPH0758383A (en) * | 1993-08-16 | 1995-03-03 | Japan Atom Energy Res Inst | Low-temperature metal vapor laser |
JPH07161687A (en) * | 1993-12-03 | 1995-06-23 | Nissin Electric Co Ltd | Dry etching method and equipment |
JPH07201856A (en) * | 1993-12-28 | 1995-08-04 | Fujitsu Ltd | Method for forming copper wiring |
US5635423A (en) * | 1994-10-11 | 1997-06-03 | Advanced Micro Devices, Inc. | Simplified dual damascene process for multi-level metallization and interconnection structure |
US5550405A (en) * | 1994-12-21 | 1996-08-27 | Advanced Micro Devices, Incorporated | Processing techniques for achieving production-worthy, low dielectric, low interconnect resistance and high performance ICS |
US5559056A (en) * | 1995-01-13 | 1996-09-24 | National Semiconductor Corporation | Method and apparatus for capping metallization layer |
US5880018A (en) * | 1996-10-07 | 1999-03-09 | Motorola Inc. | Method for manufacturing a low dielectric constant inter-level integrated circuit structure |
JPH1191940A (en) * | 1997-09-24 | 1999-04-06 | Nissan Motor Co Ltd | Rotary table driving device and driving method |
-
1997
- 1997-12-12 US US08/991,219 patent/US6143476A/en not_active Expired - Fee Related
-
1998
- 1998-10-19 US US09/174,763 patent/US6080529A/en not_active Expired - Fee Related
- 1998-12-04 WO PCT/US1998/025699 patent/WO1999031718A1/en not_active Application Discontinuation
- 1998-12-04 EP EP98961897A patent/EP1038310A1/en not_active Withdrawn
- 1998-12-04 KR KR1020007006422A patent/KR20010033061A/en not_active Application Discontinuation
- 1998-12-04 JP JP2000539519A patent/JP2002509353A/en not_active Withdrawn
-
1999
- 1999-10-08 KR KR1020017004916A patent/KR20010085939A/en not_active Application Discontinuation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4863557A (en) * | 1987-05-29 | 1989-09-05 | Yuuichi Kokaku | Pattern forming process and thin-film magnetic head formed by said process |
US5445710A (en) * | 1991-01-22 | 1995-08-29 | Kabushiki Kaisha Toshiba | Method of manufacturing semiconductor device |
EP0531232A2 (en) * | 1991-08-26 | 1993-03-10 | Eastman Kodak Company | High durability mask for use in selective area, epitaxial regrowth of GaAs |
US5578166A (en) * | 1993-05-17 | 1996-11-26 | Fujitsu Limited | Method of reactive ion etching of a thin copper film |
Non-Patent Citations (1)
Title |
---|
JOUBERT O ET AL: "Application of Plasma Polymerized Methylsilane in an all dry resist process for 193 and 248 nm Lithography", MICROELECTRONIC ENGINEERING, vol. 30, no. 1, January 1996 (1996-01-01), pages 275-278, XP004003081 * |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2000049651A1 (en) * | 1999-02-17 | 2000-08-24 | Applied Materials, Inc. | Improved masking methods and etching sequences for patterning electrodes of high density ram capacitors |
EP1124254A2 (en) * | 2000-02-09 | 2001-08-16 | Infineon Technologies North America Corp. | Easy to remove hard mask layer for semiconductor device fabrication |
EP1124254A3 (en) * | 2000-02-09 | 2004-09-22 | Infineon Technologies North America Corp. | Easy to remove hard mask layer for semiconductor device fabrication |
WO2003007344A2 (en) * | 2001-07-13 | 2003-01-23 | Applied Materials, Inc. | Etch pattern definition using a cvd organic layer as an anti-reflection coating and hardmask |
WO2003007344A3 (en) * | 2001-07-13 | 2003-09-25 | Applied Materials Inc | Etch pattern definition using a cvd organic layer as an anti-reflection coating and hardmask |
US8048325B2 (en) | 2003-03-31 | 2011-11-01 | Tokyo Electron Limited | Method and apparatus for multilayer photoresist dry development |
Also Published As
Publication number | Publication date |
---|---|
EP1038310A1 (en) | 2000-09-27 |
KR20010085939A (en) | 2001-09-07 |
US6080529A (en) | 2000-06-27 |
KR20010033061A (en) | 2001-04-25 |
JP2002509353A (en) | 2002-03-26 |
US6143476A (en) | 2000-11-07 |
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