WO1999031874A1 - Three-sided buttable cmos image sensor - Google Patents

Three-sided buttable cmos image sensor Download PDF

Info

Publication number
WO1999031874A1
WO1999031874A1 PCT/US1998/026526 US9826526W WO9931874A1 WO 1999031874 A1 WO1999031874 A1 WO 1999031874A1 US 9826526 W US9826526 W US 9826526W WO 9931874 A1 WO9931874 A1 WO 9931874A1
Authority
WO
WIPO (PCT)
Prior art keywords
image sensor
edge
chip
edges
logic
Prior art date
Application number
PCT/US1998/026526
Other languages
French (fr)
Inventor
Eric R. Fossum
Original Assignee
Photobit Corporation
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Photobit Corporation filed Critical Photobit Corporation
Priority to AU18238/99A priority Critical patent/AU1823899A/en
Publication of WO1999031874A1 publication Critical patent/WO1999031874A1/en

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/024—Details of scanning heads ; Means for illuminating the original
    • H04N1/028—Details of scanning heads ; Means for illuminating the original for picture information pick-up
    • H04N1/02805—Details of scanning heads ; Means for illuminating the original for picture information pick-up with photodetectors arranged in a two-dimensional array
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
    • H01L27/144—Devices controlled by radiation
    • H01L27/146—Imager structures
    • H01L27/14601—Structural or functional details thereof
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/024—Details of scanning heads ; Means for illuminating the original
    • H04N1/028—Details of scanning heads ; Means for illuminating the original for picture information pick-up
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N1/00—Scanning, transmission or reproduction of documents or the like, e.g. facsimile transmission; Details thereof
    • H04N1/04—Scanning arrangements, i.e. arrangements for the displacement of active reading or reproducing elements relative to the original or reproducing medium, or vice versa
    • H04N1/19—Scanning arrangements, i.e. arrangements for the displacement of active reading or reproducing elements relative to the original or reproducing medium, or vice versa using multi-element arrays
    • H04N1/195—Scanning arrangements, i.e. arrangements for the displacement of active reading or reproducing elements relative to the original or reproducing medium, or vice versa using multi-element arrays the array comprising a two-dimensional array or a combination of two-dimensional arrays
    • H04N1/19584—Combination of arrays
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N23/00—Cameras or camera modules comprising electronic image sensors; Control thereof
    • H04N23/10—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from different wavelengths
    • H04N23/12—Cameras or camera modules comprising electronic image sensors; Control thereof for generating image signals from different wavelengths with one sensor only
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
    • H04N25/00—Circuitry of solid-state image sensors [SSIS]; Control thereof
    • H04N25/40—Extracting pixel data from image sensors by controlling scanning circuits, e.g. by modifying the number of pixels sampled or to be sampled
    • H04N25/41—Extracting pixel data from a plurality of image sensors simultaneously picking up an image, e.g. for increasing the field of view by combining the outputs of a plurality of sensors

Definitions

  • a common limit is, for example, 20 x 20 mm 2 .
  • Active pixel sensors have integrated amplifiers and other logic formed on the same substrate with the image sensor chip. This obviates certain problems that are associated with charge-coupled devices.
  • the typical active pixel sensor chip has logic along at least two edges of the chip. The other edges of the chip are typically formed with "guard rings" around the edge of the image sensor.
  • a large format image sensor is formed from multiple, smaller, sensor chips. These chips are preferably active pixel sensors that require logic on chip to be associated with the pixels of the image sensor.
  • control structure e.g., the row addressing mechanism
  • these parts were located along certain edges of the chip to avoid the otherwise need to run a large number of lines across the image sensor to the rows.
  • Other such structure can include a buffer to sample and hold results from the pixels, and other associated row structure.
  • Previous active pixel image sensors formed a continuous rectangle at some area on the chip. At least two of the other edges were masked by the support circuitry. The presently-disclosed system goes against this established teaching.
  • the chip driver circuitry is formed into the shape of two pixel pitches. The circuitry placed in a central, adjacent two columns in the image sensor. This leaves three sides of the sensor array being close to the edge of the chip, and hence buttable to other similar chips.
  • the multiple butted chip assembly is used to obtain a large format image.
  • the missing two pixels in the center of the array are interpolated from the neighboring sensor signals by using standard software.
  • Figure 1 shows a preferred embodiment with a plurality of butted chips
  • Figure 2 shows a close up of the butted area
  • Figure 3 shows the layout of the driver circuit.
  • FIG. 1 An image sensor of the preferred embodiment is shown in FIG. 1.
  • FIG. 1 shows six of the specially-configured image sensor chips butted against each other.
  • Each chip is preferably rectangular, although more generally, each of the chips needs to have a first set of parallel edges, and a second set of parallel edges.
  • Each of the chips has an image sensor portion and a control portion.
  • the control portion includes a centralized control portion 130 adjacent a blocked edge of the chip, and a row-local control portion 132.
  • the row-local control portion 132 runs up the center of the image sensor area 102, masking a central two pixels of the image sensor.
  • the image sensor portions 102 of the various separated chips are shown hatched in FIG. 1.
  • Each image sensor is surrounded by a guard ring 103 that protects the image sensor, and biases the image sensor portion as appropriate.
  • the guard ring is typically about 40 ⁇ m in size.
  • the adjacent image sensor areas abut against each other with a separation equal to two guard rings (e.g., 80 ⁇ m) , and the roughness space.
  • the distance between the adjacent image sensor areas is within 2-4 pixels. This distance between adjacent image sensor areas is preferably small enough that the missing pixels can be interpolated using standard missing pixel interpolation techniques. Preferably, the distance is less than 2 pixels.
  • image sensor area 102 also abuts against image sensor area 108 of chip 110. As can be seen, the image sensor areas of each of the chips abut against each other.
  • FIG. 2 shows a close up in the area 120.
  • the pixel columns 200 and 202 are located in the chip 100, as is the guard ring 103.
  • the pixel columns 204 and 206, and the guard ring 208, are located in the chip 106.
  • a small space 210 is located between the chips.
  • the image sensor should extend up to the edge, which means that no circuitry other than the guard ring is formed between the image sensor and the edge of the substrate. More preferably, the image sensor comes within 1 pixel pitch of the edge, thereby allowing interpolation to reconstruct any missing pixels.
  • the pixels 204 are those adjacent pixels 202 or separated by a space that is preferably less than one - two pixels wide.
  • the array of image sensors 99 therefore forms a system where each pixel is separated from each adjacent pixel in the adjacent image sensor by an amount that is small enough to allow interpolation of the missing space, to thereby obtain an uninterrupted image .
  • FIG. 3 shows a close up of the area 122 in FIG. 1.
  • the center two pixels of the image sensor include drivers 300, 302 for each of the pixel rows. These can be bit decoders to select the rows, or shift registers which select one row after another.
  • SRAM 304 stores temporary results, and also buffers the information as needed.
  • Connections 306 can couple commands to the row circuitry.
  • the overall chip driver 310 can be the same as conventional, including A/D converters for each column and the like.
  • Element 312 also preferably include a two- pixel interpolator that is used to interpolate for the missing pixels at areas 105 and 107. Pixel interpolation is well known in the art, and is described, for example, in US Patent no. 4,816,913. More preferably, the pixel interpolation is done in software.
  • the row support circuitry can be different in shape than the described system.
  • other modifications are contemplated and are also intended to be covered.
  • this system suggests the row-drivers being in the center of the image sensor, they could be off center in a location, for example, that is statistically less likely to matter in the final image. Center is preferred, since this equally spaces the pixel gaps between chips and in the chip center.

Abstract

An image sensor chip (100) is formed with the image sensor abutting up to three edges of the chip. Certain parts of the row logic (132) which are required to be adjacent to each of the rows are placed into the array (102), in place of certain pixels of the array. Those missing pixels are then interpolated.

Description

THREE-SIDED BUTT7ABLE CMOS IMAGE SENSOR
BACKGROUND Each chip producer, or "foundry", often has its own set of rules regarding the sizes of chips that can be made in that foundry. A common limit is, for example, 20 x 20 mm2. It is relatively difficult to form a large format image sensor, i.e., one larger than that. Active pixel sensors have integrated amplifiers and other logic formed on the same substrate with the image sensor chip. This obviates certain problems that are associated with charge-coupled devices. The typical active pixel sensor chip has logic along at least two edges of the chip. The other edges of the chip are typically formed with "guard rings" around the edge of the image sensor.
SUMMARY
According to this system as disclosed herein, a large format image sensor is formed from multiple, smaller, sensor chips. These chips are preferably active pixel sensors that require logic on chip to be associated with the pixels of the image sensor.
Certain parts of the control structure, e.g., the row addressing mechanism, needs to be individually associated with the rows of the image sensor. In a typical active pixel sensor, these parts were located along certain edges of the chip to avoid the otherwise need to run a large number of lines across the image sensor to the rows. Other such structure can include a buffer to sample and hold results from the pixels, and other associated row structure. Previous active pixel image sensors formed a continuous rectangle at some area on the chip. At least two of the other edges were masked by the support circuitry. The presently-disclosed system goes against this established teaching. The chip driver circuitry is formed into the shape of two pixel pitches. The circuitry placed in a central, adjacent two columns in the image sensor. This leaves three sides of the sensor array being close to the edge of the chip, and hence buttable to other similar chips. The multiple butted chip assembly is used to obtain a large format image.
The missing two pixels in the center of the array are interpolated from the neighboring sensor signals by using standard software.
BRIEF DESCRIPTION OF THE DRAWINGS
These and other aspects of the invention will now be described with reference to the attached drawings, in which: Figure 1 shows a preferred embodiment with a plurality of butted chips;
Figure 2 shows a close up of the butted area; Figure 3 shows the layout of the driver circuit.
DESCRIPTION OF THE PREFERRED EMBODIMENT An image sensor of the preferred embodiment is shown in FIG. 1.
FIG. 1 shows six of the specially-configured image sensor chips butted against each other. Each chip is preferably rectangular, although more generally, each of the chips needs to have a first set of parallel edges, and a second set of parallel edges. Each of the chips has an image sensor portion and a control portion. The control portion includes a centralized control portion 130 adjacent a blocked edge of the chip, and a row-local control portion 132. The row-local control portion 132 runs up the center of the image sensor area 102, masking a central two pixels of the image sensor. The image sensor portions 102 of the various separated chips are shown hatched in FIG. 1. Each image sensor is surrounded by a guard ring 103 that protects the image sensor, and biases the image sensor portion as appropriate. The guard ring is typically about 40 μm in size.
There can be a small space 107 between the two adjacent chips 106, 109 due to the roughness of the edges. The small space is typically of the order of μm. Hence, the adjacent image sensor areas abut against each other with a separation equal to two guard rings (e.g., 80 μm) , and the roughness space. If 40μm pixels are used, then the distance between the adjacent image sensor areas is within 2-4 pixels. This distance between adjacent image sensor areas is preferably small enough that the missing pixels can be interpolated using standard missing pixel interpolation techniques. Preferably, the distance is less than 2 pixels. Similarly, image sensor area 102 also abuts against image sensor area 108 of chip 110. As can be seen, the image sensor areas of each of the chips abut against each other.
FIG. 2 shows a close up in the area 120. The pixel columns 200 and 202 are located in the chip 100, as is the guard ring 103. The pixel columns 204 and 206, and the guard ring 208, are located in the chip 106. A small space 210 is located between the chips.
Generically, the image sensor should extend up to the edge, which means that no circuitry other than the guard ring is formed between the image sensor and the edge of the substrate. More preferably, the image sensor comes within 1 pixel pitch of the edge, thereby allowing interpolation to reconstruct any missing pixels.
Hence, the pixels 204 are those adjacent pixels 202 or separated by a space that is preferably less than one - two pixels wide. The array of image sensors 99 therefore forms a system where each pixel is separated from each adjacent pixel in the adjacent image sensor by an amount that is small enough to allow interpolation of the missing space, to thereby obtain an uninterrupted image .
FIG. 3 shows a close up of the area 122 in FIG. 1. The center two pixels of the image sensor include drivers 300, 302 for each of the pixel rows. These can be bit decoders to select the rows, or shift registers which select one row after another. SRAM 304 stores temporary results, and also buffers the information as needed. Connections 306 can couple commands to the row circuitry. The overall chip driver 310 can be the same as conventional, including A/D converters for each column and the like. Element 312 also preferably include a two- pixel interpolator that is used to interpolate for the missing pixels at areas 105 and 107. Pixel interpolation is well known in the art, and is described, for example, in US Patent no. 4,816,913. More preferably, the pixel interpolation is done in software.
Although only a few embodiments have been described in detail above, other embodiments are contemplated and are intended to be encompassed within the following claims. For example, the row support circuitry can be different in shape than the described system. In addition, other modifications are contemplated and are also intended to be covered. For example, while this system suggests the row-drivers being in the center of the image sensor, they could be off center in a location, for example, that is statistically less likely to matter in the final image. Center is preferred, since this equally spaces the pixel gaps between chips and in the chip center.

Claims

What is claimed is:
1. A CMOS image sensor circuit, comprising: a first CMOS image sensor substrate, said substrate having an image sensor portion arranged in an array of rows and columns, and image sensor logic on said substrate, said logic being electrically connected to said image sensor portion, said image sensor logic including row logic associated with each of said rows individually, and chip logic associated with parts of said image sensor other than said rows individually, said substrate formed to have at least a first set of parallel edges including a first edge and a second edge, and a second set of parallel edges, different than said first set of parallel edges, said second set of parallel edges including a third edge and a fourth edge, said image sensor extending between said first edge, said second edge, and said third edge, with no circuitry being located between said image sensor and any of said first, second or third edges, such that a first area adjacent said first edge of the chip includes first pixels of the image sensor, a second area adjacent said second edge of the chip includes image sensors, and a third area adjacent said third edge of the chip includes image sensors, said row logic being physically located inside said image sensor in place of a plurality of pixels of the array forming said image sensor.
2. A circuit as in claim 1 wherein said row logic is formed in place of two columns of the array forming the active pixel sensor.
3. A circuit as in claim 1 wherein said image sensor extends within two pixel pitches of first, second, and third edges of the chip .
4. A circuit as in claim 3 wherein said first and second edges are perpendicular to said third and fourth edges .
5. A circuit as in claim 1 further comprising an interpolation element, operating to interpolate pixels which would have impinged on areas of said image sensor portion.
6. A circuit as in claim 1 wherein said row logic is in the center of the plurality of pixels forming the image sensor.
7. A circuit as in claim 1 wherein the ends of the image sensor includes a guard ring.
8. A method of operating a large format image sensor, comprising: first obtaining an image sensor chip which has first and second edges where said image sensor comes within two pixel pitches of said first and second edges, and includes row selecting logic in place of a plurality of central pixels of the image sensor; abutting said image sensor chip against a similar image sensor chip of corresponding construction; and interpolating missing pixels caused by both said row select logic and by spaces between said image sensor chips .
PCT/US1998/026526 1997-12-16 1998-12-14 Three-sided buttable cmos image sensor WO1999031874A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU18238/99A AU1823899A (en) 1997-12-16 1998-12-14 Three-sided buttable cmos image sensor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US6970097P 1997-12-16 1997-12-16
US60/069,700 1997-12-16

Publications (1)

Publication Number Publication Date
WO1999031874A1 true WO1999031874A1 (en) 1999-06-24

Family

ID=22090663

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1998/026526 WO1999031874A1 (en) 1997-12-16 1998-12-14 Three-sided buttable cmos image sensor

Country Status (2)

Country Link
AU (1) AU1823899A (en)
WO (1) WO1999031874A1 (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1173007A2 (en) 2000-07-10 2002-01-16 Canon Kabushiki Kaisha Image pickup apparatus
EP1176808A3 (en) * 2000-07-27 2003-01-02 Canon Kabushiki Kaisha Image sensing apparatus
US6906332B2 (en) * 2001-08-30 2005-06-14 Canon Kabushiki Kaisha Image-sensor, image-sensing apparatus using the image sensor, and image-sensing system
US10680021B2 (en) 2017-05-12 2020-06-09 General Electric Company Active pixel sensor computed tomography (CT) detector and method of readout

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4668333A (en) * 1985-12-13 1987-05-26 Xerox Corporation Image sensor array for assembly with like arrays to form a longer array
US4698131A (en) * 1985-12-13 1987-10-06 Xerox Corporation Replaceable image sensor array
US5031032A (en) * 1990-03-30 1991-07-09 Xerox Corporation Color array for use in fabricating full width arrays
US5282057A (en) * 1990-04-23 1994-01-25 Xerox Corporation Bit-map image resolution converter

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4668333A (en) * 1985-12-13 1987-05-26 Xerox Corporation Image sensor array for assembly with like arrays to form a longer array
US4698131A (en) * 1985-12-13 1987-10-06 Xerox Corporation Replaceable image sensor array
US5031032A (en) * 1990-03-30 1991-07-09 Xerox Corporation Color array for use in fabricating full width arrays
US5282057A (en) * 1990-04-23 1994-01-25 Xerox Corporation Bit-map image resolution converter

Cited By (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1173007A3 (en) * 2000-07-10 2003-01-02 Canon Kabushiki Kaisha Image pickup apparatus
US6717151B2 (en) 2000-07-10 2004-04-06 Canon Kabushiki Kaisha Image pickup apparatus
EP1173007A2 (en) 2000-07-10 2002-01-16 Canon Kabushiki Kaisha Image pickup apparatus
EP2278791A3 (en) * 2000-07-10 2014-01-01 Canon Kabushiki Kaisha Image pickup apparatus
US7920195B2 (en) 2000-07-27 2011-04-05 Canon Kabushiki Kaisha Image sensing apparatus having an effective pixel area
EP1176808A3 (en) * 2000-07-27 2003-01-02 Canon Kabushiki Kaisha Image sensing apparatus
US7071980B2 (en) 2000-07-27 2006-07-04 Canon Kabushiki Kaisha Image sensing apparatus
US7630010B2 (en) 2000-07-27 2009-12-08 Canon Kabushiki Kaisha Image sensing apparatus having an adding circuit to provide a one-pixel signal from a plurality of photoelectric conversion sections
US7639295B2 (en) 2000-07-27 2009-12-29 Canon Kabushiki Kaisha Image sensing apparatus
US8531568B2 (en) 2000-07-27 2013-09-10 Canon Kabushiki Kaisha Image sensing apparatus with shielding for unit blocks of a common processing circuit of plural pixels
US6906332B2 (en) * 2001-08-30 2005-06-14 Canon Kabushiki Kaisha Image-sensor, image-sensing apparatus using the image sensor, and image-sensing system
US7847259B2 (en) 2001-08-30 2010-12-07 Canon Kabushiki Kaisha Image sensor, image-sensing apparatus using the image sensor, and image-sensing system
US7952077B2 (en) 2001-08-30 2011-05-31 Canon Kabushiki Kaisha Image sensor, image-sensing apparatus using the image sensor, and image-sensing system
US7842927B2 (en) 2001-08-30 2010-11-30 Canon Kabushiki Kaisha Image sensor, image-sensing apparatus using the image sensor, and image-sensing system
US7564037B2 (en) 2001-08-30 2009-07-21 Canon Kabushiki Kaisha Image sensor, image-sensing apparatus using the image sensor, and image-sensing system
US10680021B2 (en) 2017-05-12 2020-06-09 General Electric Company Active pixel sensor computed tomography (CT) detector and method of readout

Also Published As

Publication number Publication date
AU1823899A (en) 1999-07-05

Similar Documents

Publication Publication Date Title
US7009646B1 (en) Three-sided buttable CMOS image sensor
US5315412A (en) Multi-chip color image sensor with light-receiving windows arranged to provide sensor output signals corresponding to the gap between adjacent sensors
US7737390B2 (en) Horizontal row drivers for CMOS image sensor with tiling on three edges
US6560134B2 (en) Memory configuration with a central connection area
US5031032A (en) Color array for use in fabricating full width arrays
WO1999031870A3 (en) Spatially offset, row interpolated image sensor
US20040113151A1 (en) CMOS image sensor
WO1999031874A1 (en) Three-sided buttable cmos image sensor
EP0707343A2 (en) Structure and method for connecting to integrated circuitry
JPH0571137B2 (en)
JP2009529801A (en) Pixel array structure and method of CMOS image sensor
JPH0974172A (en) Semiconductor device
JPH0580831B2 (en)
JPS6038869A (en) Two-dimensional charge coupled device image sensor
US6151235A (en) Card type semiconductor memory device for storing analog image signals in separate analog memory card units
JP2005318544A (en) Cmos image sensor capable of high-speed processing of analog signal
US20040227161A1 (en) Semiconductor integrated circuit device and wiring arranging method thereof
JPH0666346B2 (en) Charge coupled device and driving method thereof
JP2633558B2 (en) Semiconductor device
JP2695508B2 (en) Color photoelectric conversion device
JPH03291046A (en) Multi-chip color image sensor
JPH03289855A (en) Multi-chip color image sensor
JPH10270934A (en) Electronic equipment
JP4226554B2 (en) Apparatus for parallel data processing and camera system comprising the apparatus
JPS61277251A (en) Image information inputting device

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A1

Designated state(s): AL AM AT AU AZ BA BB BG BR BY CA CH CN CU CZ DE DK EE ES FI GB GD GE GH GM HR HU ID IL IS JP KE KG KP KR KZ LC LK LR LS LT LU LV MD MG MK MN MW MX NO NZ PL PT RO RU SD SE SG SI SK SL TJ TM TR TT UA UG UZ VN YU ZW

AL Designated countries for regional patents

Kind code of ref document: A1

Designated state(s): GH GM KE LS MW SD SZ UG ZW AM AZ BY KG KZ MD RU TJ TM AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE BF BJ CF CG CI CM GA GN GW ML MR NE SN TD TG

121 Ep: the epo has been informed by wipo that ep was designated in this application
DFPE Request for preliminary examination filed prior to expiration of 19th month from priority date (pct application filed before 20040101)
NENP Non-entry into the national phase

Ref country code: KR

REG Reference to national code

Ref country code: DE

Ref legal event code: 8642

122 Ep: pct application non-entry in european phase