WO1999033104A1

WO1999033104A1 - Semiconductor memory, method for producing said semiconductor memory, and implantation mask

Info

Publication number: WO1999033104A1
Application number: PCT/DE1998/002853
Authority: WO
Inventors: Albrecht Kieslich; Elke Eckstein
Original assignee: Siemens Aktiengesellschaft
Priority date: 1997-12-18
Filing date: 1998-09-24
Publication date: 1999-07-01
Also published as: DE29722440U1

Abstract

According to the invention, the transistors of a semiconductor memory are connected to terminals in the cell field and on the periphery without using silicide. In order to obtain a sufficiently low resistance, an implantation into the S/D areas is carried out using an additional mask (Z). Said mask covers areas of the cells which are sensitive to damage in the area surrounding the cell node whilst leaving the other doped areas of the respective conductivity type free. In order to prevent implantation-related lattice distortions in the area of the memory electrode, the first doped area (6) of the designated selection transistor, which is connected to the electrode, is more weakly doped than the second doped area (7) of the selection transistor which is connected to the bit line.

Description

description

Semiconductor memory, manufacturing process for the semiconductor memory and implantation mask

The invention relates to a semiconductor memory in a semiconductor substrate with memory cells, each comprising a capacitor and a MOS selection transistor and in which the capacitor is designed as a trench capacitor, and a manufacturing method.

This storage concept for D.RAM memory devices is widespread and is described, for example, in EP-A 399 060, EP-A 543 158 or in US Pat. No. 5,360,758. The storage electrode is arranged in a trench in the semiconductor substrate, the common counter electrode is formed in a suitable manner by the semiconductor substrate. The trench wall is lined with a capacitor dielectric, and there may be a thickened oxide collar near the substrate surface. The associated selection transistor is arranged adjacent to the capacitor. A first doped region of the selection transistor must be connected in a suitable manner to the storage electrode; This can be done, among other things, by a direct side wall contact, a so-called surface strap or a buried strap. The second doped region of the selection transistor is connected to a bit line. The doped regions have the opposite conductivity to the substrate in which they are arranged. For the sake of simplicity, a p-channel selection transistor in an n-doped substrate is assumed below; the n-doped substrate can also be an epitaxial layer on a p-doped silicon substrate, for example. Of course, all versions can be transferred to a p-type substrate with an n-channel transistor. In another embodiment of this storage concept, the storage electrode is formed by a region of the substrate and the cell plate by a polysilicon structure arranged in the trench. It is also possible to accommodate both electrodes in the trench.

With such an arrangement, the lowest possible contact and sheet resistance of the doped regions of transistors in the substrate is important. This is achieved by covering the doped area with a silicide. For example, an approximately 25 μm thick TiSi layer is applied to the exposed silicon areas - the S / D areas of transistors in the cell field and in the periphery - in a complex and cost-intensive process. The contact and sheet resistance of the p- and n-diffusion areas are then determined by the conductivity of the suicide, the doping of the silicon plays a subordinate role.

After the formation of the TiSi, the temperature budget for further processing is severely limited. Specific problems such as contact problems, titanium spiking, "worm holes" are observed at a temperature of around 800 ° C., as is necessary in the further production process. These lead to loss of yield and lower reliability. Due to the limited temperature budget, there is also a problem A sufficient surface activation of dopants, the healing of implantation damage and the production of a dense (void-free) BPSG insulating layer is hardly possible. Another disadvantage when using TiSi is that organic cleaning agents such as Piranha (H ₂ S0 / 0 ₃ solution) cannot be used after contact hole etching due to the reactivity with TiSi.

If the silicide layer is removed to avoid these disadvantages left, you get no functional circuit due to the greatly increased resistances. A reduction in the resistances in a silicide-free arrangement cannot be achieved simply by increasing the S / D implantations. According to the prior art, the S / D areas of the p-

Channel transistors are equally implanted in the cell field and in the periphery using a mask (so-called p ⁺ mask, which covers n diffusion areas), common parameters of this boron implantation are a dose of approximately 10 ¹⁵ cm ^{~ 2} and an energy of 10keV . This implantation - and also an analog implantation of the n-channel transistors in the periphery - generally takes place after the trench capacitor and the gate have been completed. A higher implantation (ie higher dose) leads to greater damage to the substrate in the form of lattice defects. It is formed

Dislocation loops or similar crystal defects. This cannot be tolerated, in particular in the cell field in the vicinity of the first doped region and the trench, since the reliability of the memory, for example, due to an increased leakage current, which leads to a degradation of the retention time

(Holding time, i.e. mean time until the information is lost) is reduced. If, on the other hand, titanium silicide is used, the TiSi reduces the formation of implantation-induced dislocation loops due to the lower density compared to silicon. A silicide-free process with elevated

S / D implantations therefore do not provide a functional circuit.

The object of the present invention is therefore to provide a memory cell of this type which is easier to manufacture and which has the same or improved electrical reliability, and a simplified manufacturing method.

This object is achieved by the features of claims 1 and 8. Claim 17 is a particularly suitable auxiliary means specified to solve the task.

The invention is based on avoiding a silicide and at the same time only heavily doping the S / D regions in the vicinity of which damage to the substrate is not critical. As a result, S / D regions with a sufficiently low resistance are generated in the periphery and for the connection of the bit line in the cell field, but the damage-sensitive region in the cell field around the trench and a subsequent region of the first doped region of the selection transistor are less heavily doped, so that crystal defects are largely avoided here, or can be cured even with a low temperature budget. By dispensing with silicide, a higher temperature budget is also available for further process management, so that lattice defects can be cured better.

The stronger doping of the second doped region and the peripheral transistors is achieved by first performing a first implantation of all p regions and then a further implantation with an additional mask, which covers damage-sensitive areas - in particular the vicinity of the trench - and the second doped Leaves area open. The second doped region and the S / D regions of the peripheral transistors of the same conduction type are thus implanted more than the first doped region. The parameters of the first and the further implantation are selected such that lattice disturbances in the damage-sensitive area are minimized on the one hand and contact and layer resistances in the other areas are minimized on the other hand. The n-channel peripheral transistors are doped sufficiently high with a mask covering all p regions, so that a silicide assignment is not necessary.

The second endowed area and the S / D areas of the peripheral Ri transistors of the same conductivity type have a second dopant concentration which is in the range 10 ²⁰ to 10 ²¹ cm ^"3 (surface concentration after electrical activation). The first dopant concentration in the first doped region can be approximately 10 ¹⁸ -10 ²⁰ cm ^{" 3} (preferably 10 ¹⁸ cm ^"3 ).

Further details on implantation are described in the application “semiconductor memory and implantation mask” by the same applicant and with the same application date (inventor: A. Kieslich, E. Eckstein, D. Savignac), the content of which is referred to here.

In one embodiment, the selection transistor is designed as an LDD transistor. Then the first doped region can only be doped with the LDD implantation as the first implantation, while using the additional mask the second doped region and the p-channel peripheral transistors are subjected to a further implantation. It is also possible, after the first implantation (for example LDD implantation), to implant the p-doped areas first using a known method (covering the n-diffusion areas), but with a lower dose, and then using the additional mask to implant the second ( third) implantation, so that only the second region and the p-channel peripheral transistors are doped.

The additional mask covers at least the n-diffusion areas and the vicinity of the trench with the adjoining part of the first doped area and preferably — already because the resolution limit has been reached — the entire first doped area. As explained above, the additional mask can be used as a replacement mask for the previous p ⁺ mask or as an additional mask, depending on the boundary conditions. In the latter case, the preceding implantation or implantations are carried out in such a way that a lower dopant concentration and less damage in the substrate is achieved.

Since the additional mask leaves the p-channel transistors open in the periphery, their properties can be optimized without restrictions by the cell area. Areas not critical to damage (periphery, bit line contacts) can be doped significantly higher. p-contact and layer resistances can be optimized separately from the induction of critical crystal damage.

The reduction in the S / D implantation on the cell node also reduces the under-diffusion of the S / D implantation under the gate polysilicon of the active word line. This underdiffusion causes a further leak mechanism, which is referred to as "gate induced drain leakage" (GIDL) and is usually reduced by a thick spacer on the word line and a birds beak that is as pronounced as possible (oxidation of the gate oxide on the edge of the word line). The invention leads to the further advantage that this leak mechanism is greatly reduced by the smaller implantation of the first doped region, since the position of the p / n junction below the gate can be set independently of the transistor performance of the peripheral transistors For example, it is possible to use a thinner spacer at the gate, which simplifies the further process steps (for example, generating the surface strap).

Dispensing with the usual silicide layer (usually TiSi) is made possible by the higher doping of the p-regions mentioned, which is in the range from 10 ²⁰ to 10 ²¹ cm ^"3. With the help of the additional mask, the implantation of boron in the specified areas prevented, a boron implantation in the periphery with a dose of, for example, 2 x 10 ¹⁵ cm ^-2 be performed. The dose of the first implantation is of the order of 10 ¹⁴ cm ^{"2. In} addition to simplifying the process, a higher temperature budget is achieved so that, for example, defects can be healed better and a void-free BPSG than one due to a higher flow temperature (e.g. 1000 C) Insulation layer can be produced on the traistors.

The invention can be used analogously when the n and p conductivity are interchanged, that is to say in the case of a memory cell with an n-channel selection transistor. E.g. the further implantation then takes place with the additional mask in the second doped region of the n-channel selection transistor and in the n-channel peripheral transistors.

The invention is explained in more detail below on the basis of an exemplary embodiment which is illustrated in the figures. Show it

1 - 3: a top view (a) or a cross section (b and

3) through a semiconductor substrate, on which the manufacture of an embodiment is explained. The section in the parts of the figure b runs through the selection transistor in the cell field (Zf), and transistors in the periphery (Pe) are also shown.

4: A plan view of a semiconductor substrate with a partially finished D.RAM cell, in which an example of an additional mask is shown.

5: A comparison of the failure rates of memory cells (A) according to the invention and conventional memory cells

(B).

FIG la, b: In an n-doped semiconductor substrate 1 (with a p-doped substrate part 1 'in the periphery), a trench 2 is produced according to the known method, which trench insulated ten walls and accommodates a storage electrode 3 made of p-doped polysilicon. The active region of the selection transistor is arranged adjacent to the trench; non-active regions of the substrate surface are provided with an insulation region 4 (for example shallow trench isolation). In part b, the trench 2 lying behind the cutting line is shown in dashed lines. The substrate may be heavily doped near the trench or trench bottom to form a functional cell plate. After word lines 5 have been formed in the cell field (Zf) and in the periphery (Pe), an implantation with boron is carried out, in particular the usual boron implantation for producing LDD regions. The dose is of the order of 10 ¹² to 10 ¹⁴ cm ^"2 , the energy is approximately 8 to 20 keV. This implantation can be carried out using a mask which covers the n diffusion areas (shown on the right in FIG. 1b). However, a maskless implantation can also be carried out, in particular if the dose is at most 10 ¹³ cm ^"2 ; in the n diffusion areas, the boron implantation is later compensated for by a higher n implantation. After this first implantation, a first doped region 6 and a second doped region 7 are produced in the cell field, corresponding doped regions P6, P7 of a p-channel transistor are produced in the periphery. The dopant concentration of the p regions is approximately 10 ¹⁸ cm ^"3

2a, b: n diffusion regions N6, N7 are generated in the p-doped substrate part 1 '. Spacers are produced on the side walls of the gate, so that the gate 5 is completely encapsulated with insulation 8, 8 '.

Optionally (not shown), a second p-implantation can now be carried out using the known p ⁺ mask - that is, covering the n-diffusion areas - although the dose is lower than in previous methods. ren is selected (the p ⁺ mask corresponds to the mask shown in Fig. lb). It is thereby achieved that the dopant concentration is increased in particular in the first doped region 6, but no significant lattice disturbances occur yet.

Now an additional mask Z, for example a resist mask, is applied by a known method, covering at least the n-diffusion areas N6, N7 and the damage-sensitive areas of the memory cell, i.e. the trench and the adjoining part of the first doped area and the directly adjacent area of the Covers substrate. The second doped area and the p-areas in the periphery are not covered. In FIGS. 2 and 4, the additional mask Z covers a larger area and extends approximately to the middle of the word line. Depending on the layout of the memory cells in the cell array, the additional mask Z can consist, for example, of strips, the trench capacitors and the associated first doped regions being located below the strips, and the second doped regions being arranged in the gaps between the strips. A p-implantation is now carried out with the mask Z (dose about 2 × 10 ¹⁵ to 10 ¹⁶ cm ^"2 , energy 10 keV), the S / D regions P6, P7 of the p-channel transistors in the This further implantation is preferably adjusted so that after the boron diffusion the pn junction is at a comparable depth to the known process control, the transistor parameters (punch behavior, saturation currents, threshold voltage, etc.) remain unchanged.

The usually subsequent silicide complex (titanium

Sputtering, annealing, etching) is eliminated. By eliminating the suicide, a healing and activation step at a higher temperature and / or with a longer period of time is now possible

(eg 1050 ° C, 10 see), so that sufficiently low contact and layer resistances can be achieved. 3: The additional mask is removed and the memory cell is finished using known methods. In this exemplary embodiment, provision is made for the first doped region and the storage electrode to be connected using a so-called surface strap 9 made of p-silicon. The reduced implantation dose in the first doped area does not impair the electrical function, since the charge transport within the storage cell is ensured by the highly doped surface strap. The second doped region 7 is connected to a bit line 10. This takes place, for example, via a W contact pillar, the bit line being able to consist of an Al alloy. The p-channel transistor in the periphery is connected to interconnects P1, P12. The same applies to the n-channel transistor (Nil traces, N12).

FIG. 4: A top view of the cell array is shown, the bit line contacts (second doped region 7) being arranged in rows along a first direction. The remaining areas of the memory cells, in particular the trench capacitor and the first doped area of the selection transistor, are located between these rows. The additional mask Z in the cell field consists of strips which run essentially in the first direction and leave the bit line contacts 7 and an adjacent part of the insulation 8, 8 'surrounding the gate.

5: The number of defective memory cells of an IM DRAM (A) according to the invention and a conventional silicide-containing IM DRAM (B) is shown (mean values from 10,000 chips; the error bars indicate the 2%, 25%, 75 % and 98% value, the median is also given). The requirement for an error-free cell is a refresh time of at least 620 msec (long retention). It is a clear rather a decrease in defective cells due to reduced leakage currents at (A).

Claims

claims

1. semiconductor memory arrangement in a semiconductor substrate with memory cells, each comprising a trench capacitor and a MOS selection transistor,

- In which the selection transistor comprises two doped regions (6, 7) in the semiconductor substrate (1) and the first doped region (6) with a storage electrode (3) of the capacitor and the second doped region (7) connected to a bit line (10) is

- in which the first doped region (6) has a first dopant concentration at least in the vicinity of the storage electrode (3) and the second doped region (7) has a second dopant concentration, the first dopant concentration being lower than the second dopant concentration,

a transistor of the conductivity type of the selection transistor is arranged in the periphery, the doped regions of which have a dopant concentration in the region of the second dopant concentration,

- In which the doped regions of the selection transistor

(6,7) and the peripheral transistor (Pβ, P7) silicide-free with a connection (9, 10, Pll, P12).

2. The semiconductor memory device as claimed in claim 1, in which the entire first doped region (6) has the first dopant concentration.

3. Semiconductor memory arrangement according to one of claims 1 to 2, in which the storage electrode (3) is inside the trench

(2) is arranged.

4. Semiconductor memory arrangement according to Claim 3, in which the first doped region (6) and the storage electrode (3) are joined together on the substrate surface via a conductive structure (9). are connected.

5. Semiconductor memory arrangement according to one of Claims 1 to 4, in which the selection transistor (5, 6, 7) is designed as an LDD transistor and the dopant concentration in the first doped region (6) corresponds to the concentration of the LDD region.

6. Semiconductor memory arrangement according to one of Claims 1 to 5, in which transistors of the opposite conductivity type of the selection transistor are arranged in the periphery (Pe), in which the first and second doped regions (N6, N7) of these transistors are free of silicide with one connection (Nil, N12) are connected.

7. The semiconductor memory device as claimed in one of claims 1 to 6, in which the first dopant concentration is approximately 10 ¹⁸ cm ^"3 and the second dopant concentration is approximately 10 ²⁰ -10 ²¹ cm ^{" 3} .

8. Manufacturing method for a semiconductor memory arrangement according to one of claims 1 to 7 in a semiconductor substrate (1) of a first conductivity type with the following steps: - generating a trench capacitor (2) in the semiconductor substrate with a storage electrode (3), the trench (2) adjacent to an active area is arranged in a cell field (Zf) of the semiconductor substrate (1),

Application of a word line (5) isolated from the substrate, which runs over the active region in the cell field, and application of a word line (5) isolated from the substrate in the periphery of the arrangement,

Performing a first implantation with dopant atoms of a second conductivity type in the active region, so that a first and second doped region (6, 7) of the select transistor in the cell array and doped regions (P6, P7) of a transistor are formed in the periphery,

Performing another implantation with dopant atoms of the second conductivity type using an additional mask (Z) which covers the trench (2), the adjacent part of the first doped region (6) and the immediately surrounding region of the semiconductor substrate (1), and which leaves open the second doped region (7) in the cell array and the doped regions of the transistor (P6, P7) in the periphery,

- creating a contact (9) between the storage electrode (3) of the capacitor and the first doped region (6),

- Production of a bit line (10), which is connected to the second doped region (7) free of silicide, - Production of interconnects (Pll, P12), which are connected to the doped regions (P6, P7) of the transistor in the periphery, free of silicide are.

9. The method according to .Anspruch 8, in which the additional mask (Z) completely covers the first doped region (6).

10. The method according to any one of claims 8 to 9, wherein the first implantation is carried out without the use of an implantation mask.

11. The method as claimed in one of claims 8 to 10, in which an LDD region of the second doped region (7) is formed with the aid of the first implantation and insulating spacers (8) are formed on the side walls of the word line after the first implantation.

12. The method according to any one of claims 8 to 11, wherein the first implantation with a dose in the range 10 ¹² to 10 ¹⁴ cm ^"2 and an energy in the range 8 to 20 keV and the second implantation with an energy in the range 2 x 10 ¹⁵ to 10 ¹⁶ cm ^"2 and an energy of about 10 keV is carried out.

13. The method as claimed in one of claims 8 to 12, in which, after the first implantation, a second implantation with dopant atoms of the second conductivity type takes place in the first (6) and the second (7) doped region and the second implantation with a dose of less than 10 ¹⁵ cm ^" ^{2 is} performed.

14. The method according to any one of claims 8 to 13, wherein the contact between the storage electrode (3) and the first doped region (6) is produced with the aid of a polysilicon structure (9) which on the substrate surface or in the upper region of the trench ( 2) is arranged.

15. The method as claimed in one of claims 8 to 13, in which the contact between the storage electrode (3) and the first doped region (6) takes place directly via an opening in the side wall insulation of the trench.

16. The method as claimed in one of claims 8 to 15, in which a transistor of the opposite conductivity type of the selection transistor is produced in the periphery of the semiconductor arrangement and the doped regions thereof are connected to terminals (Nil, N12) without silicide.

17. Mask for the production of a semiconductor memory arrangement according to one of claims 1 to 7 for use in the method according to one of claims 8 to 16, the trench (2), the adjacent part of the first doped region (6) and the in the region of a memory cell covers the immediately surrounding area of the semiconductor substrate, and which leaves open the second doped region (7) and a peripheral transistor of the conductivity type of the selection transistor.

18. Mask according to Claim 17, which covers the entire first doped region (6).

19. Mask according to one of claims 17 or 18, which covers strip-shaped regions in the cell field of the semiconductor memory arrangement, the gaps between the strips being arranged above the second doped regions of memory cells.