WO1999039432B1 - Structure and method for super fet mixer having logic-gate generated fet square-wave switching signal - Google Patents

Structure and method for super fet mixer having logic-gate generated fet square-wave switching signal

Info

Publication number
WO1999039432B1
WO1999039432B1 PCT/US1999/001934 US9901934W WO9939432B1 WO 1999039432 B1 WO1999039432 B1 WO 1999039432B1 US 9901934 W US9901934 W US 9901934W WO 9939432 B1 WO9939432 B1 WO 9939432B1
Authority
WO
WIPO (PCT)
Prior art keywords
signal
mixer
input
frequency
output
Prior art date
Application number
PCT/US1999/001934
Other languages
French (fr)
Other versions
WO1999039432A1 (en
WO1999039432A9 (en
Inventor
Michael Wendell Vice
Charles Edward Dexter
Original Assignee
Watkins Johnson Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Watkins Johnson Co filed Critical Watkins Johnson Co
Priority to EP99903483A priority Critical patent/EP0972337B1/en
Priority to DE69938482T priority patent/DE69938482T2/en
Priority to JP53955199A priority patent/JP2001525148A/en
Priority to AU23491/99A priority patent/AU757574B2/en
Priority to CA002285557A priority patent/CA2285557C/en
Publication of WO1999039432A1 publication Critical patent/WO1999039432A1/en
Publication of WO1999039432B1 publication Critical patent/WO1999039432B1/en
Publication of WO1999039432A9 publication Critical patent/WO1999039432A9/en

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1441—Balanced arrangements with transistors using field-effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1408—Balanced arrangements with diodes
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1433—Balanced arrangements with transistors using bipolar transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1458—Double balanced arrangements, i.e. where both input signals are differential
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/14—Balanced arrangements
    • H03D7/1425—Balanced arrangements with transistors
    • H03D7/1466—Passive mixer arrangements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0001—Circuit elements of demodulators
    • H03D2200/0023—Balun circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D2200/00—Indexing scheme relating to details of demodulation or transference of modulation from one carrier to another covered by H03D
    • H03D2200/0041—Functional aspects of demodulators
    • H03D2200/0088—Reduction of intermodulation, nonlinearities, adjacent channel interference; intercept points of harmonics or intermodulation products
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D7/00—Transference of modulation from one carrier to another, e.g. frequency-changing
    • H03D7/12—Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes
    • H03D7/125—Transference of modulation from one carrier to another, e.g. frequency-changing by means of semiconductor devices having more than two electrodes with field effect transistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03D—DEMODULATION OR TRANSFERENCE OF MODULATION FROM ONE CARRIER TO ANOTHER
    • H03D9/00—Demodulation or transference of modulation of modulated electromagnetic waves
    • H03D9/06—Transference of modulation using distributed inductance and capacitance
    • H03D9/0658—Transference of modulation using distributed inductance and capacitance by means of semiconductor devices having more than two electrodes

Abstract

A mixer comprising a local oscillator input port for receiving an externally generated sinusoidal local oscillator signal at a local oscillator frequency. A phase splitter is coupled to said local oscillator input port for receiving said local oscillator signal and for generating first and second phase separated signals at said local oscillator frequency having a substantially 180 degree phase difference between each other. A voltage potential isolator generates first and second differential signal pairs at said local oscillator frequency respectively from said first and second phase split signals. A square wave signal generator generates first and second floating square waves respectively from said first and second differential signal pairs. Each square wave signal has a high slew rate leading and trailing signal edge such that one FET switches ON precisely when the other FET switches OFF. At least one frequency mixing device receives said first and second square wave signals and an input signal from an input port at an input frequency and generates an output signal at an output port at an output signal frequency. An input/output signal separator separates said output signal from said input signal and directs said output signal to an output port.

Claims

AMENDED CLAIMS[received by the International Bureau on 30 July 1999 (30.07.99); new claims 16-29 added; remaining claims unchanged (6 pages)]
1. A mixer comprising: a local oscillator input port for receiving an externally generated sinusoidal local oscillator signal at a local oscillator frequency; phase splitter means coupled to said local oscillator input port for receiving said local oscillator signal and for generating first and second phase separated signals at said local oscillator frequency and having substantially 180 degree phase difference between each other; voltage potential isolation means for generating first and second differential signal pairs at said local oscillator frequency respectively from said first and second phase split signals; square wave signal generation means for generating first and second floating square waves respectively from said first and second differential signal pairs, each said square wave signal having a high slew rate leading and trailing signal edge such that one FET switches ON precisely when the other FET switches OFF; at least one frequency mixing device receiving said first and second square wave signals and an input signal from an input port at an input frequency and generating an output signal at an output port at an output signal frequency; input/output signal separation means for separating said output signal from said input signal and for directing said output signal to an output port.
2. The mixer in Claim 1, wherein the square wave signal has a rise time of less than about 300 picoseconds and a fall time of less than 300 picoseconds
3. The mixer in Claim 1 , wherein said square wave signal generation means comprises a bi-stable circuit generating a substantially constant first amplitude output in response to receiving a first input having first input voltage amplitude in the range between SI and S2, and generating a second substantially constant voltage amplitude output different from said first voltage amplitude in response to receiving a second input having a second input voltage amplitude in the range between S3 and S4.
4. The mixer in Claim 3, wherein said bi-stable circuit comprises a logic gate having first and second output logic states.
5. The mixer in Claim 4, wherein said logic gate comprises an AND gate.
6. The mixer in Claim 5, wherein said logic gate is selected from the group of gates consisting of: AND, NAND, OR, NOR, XOR, XNOR, and combinations thereof
7. The mixer in Claim 5, wherein said frequency mixing devices comprise a plurality of GaAs FETs.
8. The mixer of Claim 6, wherein said logic gate can perform a complementary (180-degree) waveform, and wherein no splitting balun is needed.
9. The mixer of claim 1 , wherein said switching circuit comprises a plurality of FETs.
10. The mixer of claim 1 , wherein said switching circuit comprises two pairs of source-to-source serially connected FETs.
11. The mixer of claim 1 , wherein said input signal is a radio-frequency (RF) signal and said output signal is an intermediate-frequency (IF) signal.
12. The mixer in Claim 3, wherein said first input voltage amplitude is in the range between about -0.5 volts and +0.5 volts, and said second input voltage amplitude is in the range between about 3.5 volts and 6 volts.
13. The mixer of claim 1, wherein said input signal is an intermediate- frequency (IF) signal and said output signal is a radio-frequency (RF) signal.
14. In a mixer having at least one FET mixing element, a method for switching said FET mixing element between ON and OFF states; said method comprising the steps of: receiving a first substantially sinusoidal signal at a first frequency; coupling said first signal to a high-slew rate circuit to generate a substantially square-wave two-level output signal at said first frequency; coupling said substantially square wave output signal to said FET mixing element to drive said FET into an ON conduction state when said square wave output signal is at a first level and to drive said FET into an OFF conduction state when said square wave output signal is at a second level; said square wave output signal having a high slew rate minimizing the period of time said FET is in an intermediate conduction state, and thereby reducing distortion by said mixer.
15. The mixer in claim 1 , wherein said mixer is configured as a triple-balanced reflection mixer having a square-wave local oscillator regeneration circuit, regenerating a substantially square wave signal from a substantially sinusoidal local oscillator signal.
16. A mixer comprising: a local oscillator input port for receiving an externally generated sinusoidal local oscillator signal at a local oscillator frequency; a phase splitter circuit coupled to said local oscillator input port for receiving said local oscillator signal and for generating first and second phase separated signals at said local oscillator frequency and having substantially 180 degree phase difference between each other; voltage potential isolation means for generating first and second differential signal pairs at said local oscillator frequency respectively from said first and second phase split signals; a square wave signal generation circuit generating first and second floating square waves respectively from said first and second differential signal pairs, each said square wave signal having a high slew rate leading and trailing signal edge such that one FET switches ON precisely when the other FET switches OFF; said square wave signal generation circuit comprises a logic gate having first and second output logic states generating a substantially constant first amplitude output in response to receiving a first input having first input voltage amplitude in the range between S 1 and S2, and generating a second substantially constant voltage amplitude output different from said first voltage amplitude in response to receiving a second input having a second input voltage amplitude in the range between S3 and S4; at least one frequency mixing device receiving said first and second square wave signals and an input signal from an input port at an input frequency and generating an output signal at an output port at an output signal frequency; and input/output signal separation means for separating said output signal from said input signal and for directing said output signal to an output port.
17. The mixer in Claim 16, wherein the square wave signal has a rise time of less than about 300 picoseconds and a fall time of less than about 300 picoseconds
18. The mixer in Claim 17, wherein said logic gate comprises an AND gate.
19. The mixer in Claim 17, wherein said logic gate is selected from the group of gates consisting of: AND, NAND, OR, NOR, XOR, XNOR, and combinations thereof.
20. The mixer of Claim 19, wherein said logic gate can perform a complementary (180-degree) waveform, and wherein no splitting balun is needed.
21. A mixer circuit comprising: a phase splitter circuit receiving a local oscillator signal and generating first and second phase separated signals; a voltage potential isolation circuit generating first and second differential signal pairs at said local oscillator frequency respectively from said first and second phase split signals; a logic gate having first and second output logic states generating first and second floating square waves respectively from said first and second differential signal pairs, each said square wave signal having a high slew rate leading and trailing signal edge such that one FET switches ON precisely when the other FET switches OFF; at least one frequency mixing device receiving said first and second square wave signals and an input signal at an input frequency and generating an output signal at an output signal frequency; and a signal separation circuit for separating said output signal from said input signal and for directing said output signal to an output port.
22 . A mixer circuit as in claim 21 wherein: said logic gate having first and second output logic states generating a substantially constant first amplitude output in response to receiving a first input having first input voltage amplitude in the range between SI and S2, and generating a second substantially constant voltage amplitude output different from said first voltage amplitude in response to receiving a second input having a second input voltage amplitude in the range between S3 and S4.
23. The mixer in Claim 21, wherein the square wave signal has a rise time of less than about 300 picoseconds and a fall time of less than about 300 picoseconds
24. The mixer in Claim 21, wherein said logic gate comprises an AND gate.
25. The mixer in Claim 21 , wherein said logic gate is selected from the group of gates consisting of: AND, NAND, OR, NOR, XOR, XNOR, and combinations thereof.
26. The mixer of Claim 21, wherein said logic gate provides a complementary
(180-degree) waveform, and wherein no splitting balun is needed.
27. In a mixer having at least one mixing element, a method for switching said mixing element between ON and OFF states; said method comprising the steps of: receiving a low slew rate signal at a first frequency; coupling said low slew rate signal to a high-slew rate signal generation circuit and generating a high slew rate substantially two-level output signal at said first frequency; coupling said high slew rate output signal to said mixing element to drive said mixing element into an ON conduction state when said output signal is at a first level and to drive said mixing into an OFF conduction state when said output signal is at a second level; said high slew rate output signal having a high slew rate minimizing the period of time said mixing element is in an intermediate conduction state to reduce distortion produced by said mixer.
28. The method in Claim 27, wherein said mixing element comprises a FET and said high slew rate generation circuit comprises a logic gate.
29. The method in Claim 28, wherein said low slew rate signal is a signal having a substantially sinusoidal signal waveform; and said high slew rate signal is a signal having a substantially square wave signal waveform.
PCT/US1999/001934 1998-02-01 1999-01-29 Structure and method for super fet mixer having logic-gate generated fet square-wave switching signal WO1999039432A1 (en)

Priority Applications (5)

Application Number Priority Date Filing Date Title
EP99903483A EP0972337B1 (en) 1998-02-01 1999-01-29 Structure and method for super fet mixer having logic-gate generated fet square-wave switching signal
DE69938482T DE69938482T2 (en) 1998-02-01 1999-01-29 ARRANGEMENT AND METHOD FOR SUPER-FET MIXERS WITH LOGIC GATE GENERATED RECTANGULAR ACTION SWITCHES SIGNAL
JP53955199A JP2001525148A (en) 1998-02-01 1999-01-29 Structure and method of superfet mixer with logic gate generating fet square wave switching signal
AU23491/99A AU757574B2 (en) 1998-02-01 1999-01-29 Structure and method for super FET mixer having logic-gate generated FET square-wave switching signal
CA002285557A CA2285557C (en) 1998-02-01 1999-01-29 Structure and method for super fet mixer having logic-gate generated fet square-wave switching signal

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/017,455 US6144236A (en) 1998-02-01 1998-02-01 Structure and method for super FET mixer having logic-gate generated FET square-wave switching signal
US09/017,455 1998-02-01

Publications (3)

Publication Number Publication Date
WO1999039432A1 WO1999039432A1 (en) 1999-08-05
WO1999039432B1 true WO1999039432B1 (en) 1999-09-16
WO1999039432A9 WO1999039432A9 (en) 1999-10-28

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Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/001934 WO1999039432A1 (en) 1998-02-01 1999-01-29 Structure and method for super fet mixer having logic-gate generated fet square-wave switching signal

Country Status (8)

Country Link
US (1) US6144236A (en)
EP (1) EP0972337B1 (en)
JP (1) JP2001525148A (en)
AT (1) ATE392042T1 (en)
AU (1) AU757574B2 (en)
CA (1) CA2285557C (en)
DE (1) DE69938482T2 (en)
WO (1) WO1999039432A1 (en)

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Also Published As

Publication number Publication date
WO1999039432A1 (en) 1999-08-05
EP0972337A1 (en) 2000-01-19
DE69938482T2 (en) 2009-06-04
JP2001525148A (en) 2001-12-04
DE69938482D1 (en) 2008-05-21
EP0972337B1 (en) 2008-04-09
CA2285557C (en) 2005-12-06
CA2285557A1 (en) 1999-08-05
AU757574B2 (en) 2003-02-27
WO1999039432A9 (en) 1999-10-28
AU2349199A (en) 1999-08-16
ATE392042T1 (en) 2008-04-15
US6144236A (en) 2000-11-07

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