WO1999041774A3 - Method of manufacturing integrated circuits in which malfunctioning apparatuses are detected - Google Patents

Method of manufacturing integrated circuits in which malfunctioning apparatuses are detected Download PDF

Info

Publication number
WO1999041774A3
WO1999041774A3 PCT/IB1999/000157 IB9900157W WO9941774A3 WO 1999041774 A3 WO1999041774 A3 WO 1999041774A3 IB 9900157 W IB9900157 W IB 9900157W WO 9941774 A3 WO9941774 A3 WO 9941774A3
Authority
WO
WIPO (PCT)
Prior art keywords
defects
detected
apparatuses
malfunctioning
integrated circuits
Prior art date
Application number
PCT/IB1999/000157
Other languages
French (fr)
Other versions
WO1999041774A2 (en
Inventor
Venkat R Nagaswami
Gessel Johannes G Van
Wezep Dries A Van
Original Assignee
Koninkl Philips Electronics Nv
Philips Svenska Ab
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninkl Philips Electronics Nv, Philips Svenska Ab filed Critical Koninkl Philips Electronics Nv
Priority to DE69930102T priority Critical patent/DE69930102T2/en
Priority to EP99900602A priority patent/EP0972300B1/en
Priority to JP54124599A priority patent/JP2001522541A/en
Publication of WO1999041774A2 publication Critical patent/WO1999041774A2/en
Publication of WO1999041774A3 publication Critical patent/WO1999041774A3/en

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67242Apparatus for monitoring, sorting or marking
    • H01L21/67288Monitoring of warpage, curvature, damage, defects or the like
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L22/00Testing or measuring during manufacture or treatment; Reliability measurements, i.e. testing of parts without further processing to modify the parts as such; Structural arrangements therefor
    • H01L22/20Sequence of activities consisting of a plurality of measurements, corrections, marking or sorting steps

Abstract

Visible defects are detected on a process semiconductor wafer. Defects are classified according to appearance and an association is kept between classes and apparatuses. When the density of defects in a given class exceeds a control limit the associated apparatus is switched off-line. In an embodiment, the same wafer is inspected repeatedly, each time after different processing steps and information about the location of detected defects is kept. Defects which occur at a location where defects have already been detected in a previous inspection after an earlier processing step are eliminated from the density which is compared to the control limit.
PCT/IB1999/000157 1998-02-10 1999-01-28 Method of manufacturing integrated circuits in which malfunctioning apparatuses are detected WO1999041774A2 (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
DE69930102T DE69930102T2 (en) 1998-02-10 1999-01-28 METHOD FOR PRODUCING INTEGRATED CIRCUITS
EP99900602A EP0972300B1 (en) 1998-02-10 1999-01-28 Method of manufacturing integrated circuits
JP54124599A JP2001522541A (en) 1998-02-10 1999-01-28 Manufacturing method of integrated circuit

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP98200413.7 1998-02-10
EP98200413 1998-02-10

Publications (2)

Publication Number Publication Date
WO1999041774A2 WO1999041774A2 (en) 1999-08-19
WO1999041774A3 true WO1999041774A3 (en) 1999-10-28

Family

ID=8233378

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/IB1999/000157 WO1999041774A2 (en) 1998-02-10 1999-01-28 Method of manufacturing integrated circuits in which malfunctioning apparatuses are detected

Country Status (5)

Country Link
US (1) US6242270B1 (en)
EP (1) EP0972300B1 (en)
JP (1) JP2001522541A (en)
DE (1) DE69930102T2 (en)
WO (1) WO1999041774A2 (en)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6560504B1 (en) * 1999-09-29 2003-05-06 Advanced Micro Devices, Inc. Use of contamination-free manufacturing data in fault detection and classification as well as in run-to-run control
JP2002270667A (en) * 2001-03-12 2002-09-20 Sony Corp Semiconductor manufacturing method and apparatus
US6749720B2 (en) * 2001-03-21 2004-06-15 Owens Corning Fiberglas Technology, Inc. Wet-formed mat applications for cement backerboards
JP2003022945A (en) * 2001-07-06 2003-01-24 Mitsubishi Electric Corp Process management apparatus, process management method, and program for management of process
WO2003044852A2 (en) * 2001-10-19 2003-05-30 Auburn University Estimating reliability of components for testing and quality optimization
JP3699960B2 (en) * 2003-03-14 2005-09-28 株式会社東芝 Inspection recipe creation system, defect review system, inspection recipe creation method and defect review method
WO2005096688A1 (en) * 2004-04-02 2005-10-13 Original Solutions Inc. System and method for defect detection and process improvement for printed circuit board assemblies
US8108805B2 (en) * 2010-03-26 2012-01-31 Tokyo Electron Limited Simplified micro-bridging and roughness analysis
US9639774B2 (en) * 2012-12-07 2017-05-02 Taiwan Semiconductor Manufacturing Co., Ltd. Method for determining applicabilty of a processing device, a processing path and a processing pattern
US20220084856A1 (en) * 2019-03-06 2022-03-17 Hitachi High-Tech Corporation Defect Inspection Apparatus and Defect Inspection Program

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5537325A (en) * 1991-10-29 1996-07-16 Komatsu Electronic Metals Co., Ltd. Apparatus for and method of manufacturing semiconductor wafer
US5694325A (en) * 1990-08-14 1997-12-02 Kabushiki Kaisha Toshiba Semiconductor production system
US5862055A (en) * 1997-07-18 1999-01-19 Advanced Micro Devices, Inc. Automatic defect classification individual defect predicate value retention

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4144493A (en) * 1976-06-30 1979-03-13 International Business Machines Corporation Integrated circuit test structure
JPH05259015A (en) 1991-04-19 1993-10-08 Matsushita Electron Corp Manufacture of semiconductor device
US5544256A (en) * 1993-10-22 1996-08-06 International Business Machines Corporation Automated defect classification system
JPH07201946A (en) * 1993-12-28 1995-08-04 Hitachi Ltd Manufacture of semiconductor device and apparatus for manufacture the same, testing of the same and testing apparatus
US5787190A (en) * 1995-06-07 1998-07-28 Advanced Micro Devices, Inc. Method and apparatus for pattern recognition of wafer test bins
US5726920A (en) * 1995-09-29 1998-03-10 Advanced Micro Devices, Inc. Watchdog system having data differentiating means for use in monitoring of semiconductor wafer testing line
US6091846A (en) * 1996-05-31 2000-07-18 Texas Instruments Incorporated Method and system for anomaly detection
US6021380A (en) * 1996-07-09 2000-02-01 Scanis, Inc. Automatic semiconductor wafer sorter/prober with extended optical inspection
JPH10123202A (en) * 1996-10-21 1998-05-15 Nec Ic Microcomput Syst Ltd Semiconductor integrated circuit device
US6072574A (en) * 1997-01-30 2000-06-06 Micron Technology, Inc. Integrated circuit defect review and classification process
US6084420A (en) * 1998-11-25 2000-07-04 Chee; Wan Soo Probe assembly for testing

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5694325A (en) * 1990-08-14 1997-12-02 Kabushiki Kaisha Toshiba Semiconductor production system
US5537325A (en) * 1991-10-29 1996-07-16 Komatsu Electronic Metals Co., Ltd. Apparatus for and method of manufacturing semiconductor wafer
US5862055A (en) * 1997-07-18 1999-01-19 Advanced Micro Devices, Inc. Automatic defect classification individual defect predicate value retention

Also Published As

Publication number Publication date
US6242270B1 (en) 2001-06-05
EP0972300B1 (en) 2006-03-01
DE69930102T2 (en) 2006-08-31
EP0972300A2 (en) 2000-01-19
JP2001522541A (en) 2001-11-13
DE69930102D1 (en) 2006-04-27
WO1999041774A2 (en) 1999-08-19

Similar Documents

Publication Publication Date Title
CA2249088A1 (en) Method and apparatus for high-speed interconnect testing
EP0616364A4 (en) Apparatus for and method of manufacturing semiconductor wafer.
EP1324022A4 (en) Apparatus for inspecting wafer surface, method for inspecting wafer surface, apparatus for judging defective wafer, method for judging defective wafer, and apparatus for processing information on wafer surface
WO1999041774A3 (en) Method of manufacturing integrated circuits in which malfunctioning apparatuses are detected
WO2001097279A3 (en) Method and apparatus for using scatterometry to perform feedback and feed-forward control
WO2003044851A3 (en) Method and apparatus for utilizing integrated metrology data as feed-forward data
TW358997B (en) Method and apparatus for performing operative testing on an IC
WO2003003415A3 (en) Method and apparatus for providing distributed material management and flow control in an integrated circuit factory
US5784484A (en) Device for inspecting printed wiring boards at different resolutions
EP0631304A3 (en) System and method for monitoring and evaluating semiconductor wafer fabrication.
WO2004020704A8 (en) Apparatus and method for deposition of an electrophoretic emulsion
EP0810066A3 (en) Automated wafer lapping system
WO2006012022A3 (en) Methods and apparatus for determining endpoint in a plasma processing system
WO2001098848A3 (en) Method and apparatus for interfacing a statistical process control system with a manufacturing process control framework
AU1072700A (en) An apparatus for integrated monitoring of wafers and for process control in the semiconductor manufacturing and method for use thereof
EP1184895A3 (en) Substrate processing apparatus and substrate inspection method
JPS60254626A (en) Wafer testing method
ID17230A (en) METHOD OF PROCESSING LAYERS DOWN
EP0614089A3 (en) Method and apparatus for in-situ testing of integrated circuit chips.
EP0966026A3 (en) A method for reducing particles from an electrostatic chuck and an equipment for manufacturing a semiconductor
US6165805A (en) Scan tool recipe server
WO2001096835A8 (en) Method for identifying the cause of yield loss in integrated circuit manufacture
WO2002007167A3 (en) Method for selecting an optimal level of redundancy in the design of memories
WO2002029390A3 (en) Method and apparatus to provide for automated process verification and hierarchical substrate examination
US6491451B1 (en) Wafer processing equipment and method for processing wafers

Legal Events

Date Code Title Description
AK Designated states

Kind code of ref document: A2

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A2

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

WWE Wipo information: entry into national phase

Ref document number: 1999900602

Country of ref document: EP

ENP Entry into the national phase

Ref country code: JP

Ref document number: 1999 541245

Kind code of ref document: A

Format of ref document f/p: F

121 Ep: the epo has been informed by wipo that ep was designated in this application
AK Designated states

Kind code of ref document: A3

Designated state(s): JP

AL Designated countries for regional patents

Kind code of ref document: A3

Designated state(s): AT BE CH CY DE DK ES FI FR GB GR IE IT LU MC NL PT SE

WWP Wipo information: published in national office

Ref document number: 1999900602

Country of ref document: EP

WWG Wipo information: grant in national office

Ref document number: 1999900602

Country of ref document: EP