WO1999046860A1 - An asynchronous mode pixel-parallel sigma-delta a/d converter for cmos imagers - Google Patents

Abstract

An asynchronous mode sigma-delta modulator circuit is usable, for example, at each pixel of a CMOS image sensor. The asynchronous sigma-delta modulator includes a comparator circuit (MND0, MND1, MND2, MPD1, MPD2) whose output switches to indicate when an input signal has reached a predetermined reference level, and a latch circuit (MNL1, MPL2, MPL2) that asserts a pulse signal when the comparator output switches. A pulse capture circuit (MPUL, MRST, MBIT) senses the pulse signal and stores it as a logic value until sampled by a clocked output circuit. Regeneration circuitry (MPS1, MNS1, MPS2, MNS2, MRGN) resets the input signal and the latch circuit after the pulse signal is captured by the pulse capture circuit.

Description

TITLE OF THE INVENTION

An Asynchronous Mode Pixel-Parallel Sigma-Delta A/D

Converter for CMOS Imagers

CROSS REFERENCE TO RELATED APPLICATIONS

This application claims priority under 35 U.S.C.

§119 (e) of U.S. provisional patent application no.

60/077,760, filed March 12, 1998, entitled "An Asynchronous

Mode Pixel-Parallel Sigma-Delta A/D Converter for CMOS Imagers . "

STATEMENT REGARDING FEDERALLY SPONSORED RESEARCH OR

DEVELOPMENT Support for research described in this patent was provided in part by the Defense Advanced Research Projects Agency under contract DAAK60-96-K-0204, "3D Computational Image Sensors for Advanced Low Power Visual Processing, " and in part by the National Science Foundation under grant MIP- 9623907.

BACKGROUND OF THE INVENTION On-chip analog-to-digital (A/D) conversion has been recognized as a desirable feature for CMOS image sensors, because it can reduce power and increase system integration. To date several image sensors have been developed with column-parallel A/D conversion, such as a single-slope sensor architecture, a successive approximation architecture, and a second-order current-mode sigma-delta architecture. These designs typically require a significant amount of area and careful layout, because the pitch of the A/D converters must be matched to that of the sensor columns .

In order to build compact, portable low-power devices for real-time image processing, it is useful to provide more -2 -

integration and parallelism for on-chip computations. The architecture which is most appropriate for pixel-parallel A/D conversion is a first-order sigma-delta loop, because it can be implemented in a very small area and computations can be performed on the bit stream output before decimation with simple logic circuits.

A block diagram of a first-order sigma-delta modulator is illustrated in Figure 1. With x_x representing the sampled input data at time t=iT, T being the sampling period, and y_x representing the binary-valued output of the modulator, it can be shown that

y__ = ι-ι + ^βj. - ^βi-i (1)

where e is the quantization error at step i. If the sequence y_x is optimally filtered and decimated down to the Nyquist rate 2f₀ of the input, the remaining in-band noise is given by

n₀(dB) = e + 5.2 - 91og₂N (2)

where N is the oversampling ratio, N = (2foT)^-1, and e is the root mean square quantization error from the loop A/D. This equation implies that one can ideally obtain 1.5 bits of resolution for every doubling of N. Many algorithms have been developed over the last three decades for recovering high resolution (multi-bit) data from sigma-delta output streams. These can be readily implemented on a digital signal processor interfaced to the imager. Pixel-parallel sigma-delta A/D converter designs developed for 2D CMOS imagers are known in the art. One design is described by Boyd Fowler in his 1995 Ph.D. thesis entitled "CMOS Area Image Sensors with Pixel Level A/D -3-

Conversion, " and also in corresponding U.S. Patent No. 5,461,425. Another design is described by Yang et al in "A 128 X 128 Pixel CMOS Area Image Sensor With Multiplexed Pixel Level A/D Conversion," Digest of Technical Papers, Custom Integrated Circuits Conference, 1996. These designs employ a classical synchronous architecture. In particular, these designs are based on a clocked comparator and a switched-capacitor circuit implementing the 1-bit D/A converter in the feedback loop.

BRIEF SUMMARY OF THE INVENTION In accordance with the present invention, an asynchronous sigma-delta modulator is disclosed that oscillates at a rate proportional to an input light value, generating a regular stream of pulses that is sampled at a rate f_s (=1/T) to produce a binary output data stream. The asynchronous architecture requires a minimal number of analog components and thus can be operated at high sampling rates with little signal-to-noise ration (SNR) degradation. The architecture has been demonstrated to operate with measured SNR of 60 dB at an equivalent frame rate of 5000 frames/second (312.5 kHz pixel sampling rate). At moderate rates such as 30 frames/second, a circuit implementation of the architecture is capable of measuring light intensities over more than 120 dB dynamic range. The asynchronous design also minimizes the number of analog components that must be well matched in order to reduce fixed pattern noise, and it allows greater control of the sensitivity and frame rate of the imager. An embodiment of the asynchronous sigma-delta modulator is disclosed that includes a comparator circuit whose output switches to indicate when an input signal has reached a predetermined reference level, and a latch circuit that -4 -

asserts a pulse signal when the comparator output switches. A pulse capture circuit senses the pulse signal and stores it as a logic value until sampled by a clocked output circuit. Regeneration circuitry resets the input signal and the latch circuit after the pulse signal is captured by the pulse capture circuit.

Other aspects, features, and advantages of the present invention are disclosed in the detailed description that follows .

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING Figure 1 is a block diagram of a canonical first-order sigma-delta modulator circuit for sampled data as is known in the prior art; Figure 2 is a waveform diagram illustrating the different output waveforms generated by synchronous and asynchronous modulator circuits;

Figure 3 is a schematic diagram of an asynchronous first-order sigma-delta A/D converter cell in accordance with the present invention;

Figure 4 (consisting of Figures 4a, 4b and 4c) is a timing diagram of several signals in the circuit of Figure 3;

Figure 5 is a plot of the pixel output of the sigma- delta converter cell of Figure 3 as a function of sampling period T for constant illumination; and

Figure 6 is a plot of the output of the sigma-delta converter cell of Figure 3 as a function of illumination at a 5 kHz sampling rate.

DETAILED DESCRIPTION OF THE INVENTION Figure 2 illustrates the outputs of both an asynchronous modulator circuit (solid line) and a -5-

synchronous modulator circuit (dashed line) assuming a constant input value x. These waveforms are based on a continuous-time version of the first order circuit of Figure 1 in which the accumulator is replaced with an integrator and the variables are continuous functions of time. The asynchronous modulator generates a bit stream output that is equivalent to the output of the synchronous modulator. This equivalence was first observed by Candy and Benjamin in a paper entitled "The Structure of Quantization Noise from Sigma-Delta Modulation, " IEEE Transactions on Communications, vol. 29(9), pages 1316-1323 (1981).

With reference to Figure 2, it is assumed that the input x is a negative quantity, so that the integrator output, ω, decreases with time. When the sampled value of ω is less than or equal to the reference level B in the synchronous modulator (dashed line), a '1' is output, and the circuit is reset. As part of the resetting, an impulse of IX_max'TI is added back to the input, where T is the clock period. The comparison between the integrator output and the reference B is synchronized with the clock edge, so that ω typically drops a variable amount below B before the circuit is reset. The high reference level A, which is equal to B + |x_maχ-T|, represents the maximum value of ω.

When the integrator output reaches B in the asynchronous modulator (solid waveform) , the circuit is immediately reset to the fixed level A. At the same time, a pulse is generated that is sampled on the next clock edge to produce the output bit.

The key observation in the waveforms of Figure 2 is that when the synchronous modulator resets, its waveform rejoins that of the free running asynchronous circuit, and hence the bit stream outputs of the two are identical. The - 6-

asynchronous modulator oscillates with period (x_max/x)-T, and thus the average value of the output converges to x/x_max.

The primary advantage of the asynchronous modulator is that it is reset to a fixed level when its output level ω drops to B. This is in contrast to the synchronous modulator, which requires that an accurate analog value be added back to the output upon reset. This feature of the asynchronous modulator eliminates the problem of mismatch in analog components, which is a major source of fixed pattern noise when synchronous cells are implemented in an array.

Figure 3 shows a schematic of an asynchronous modulator cell suitable for use in a CMOS imager with photodiode input. The circuit is composed of four sections:

1. A differential amplifier/comparator formed of transistors MNDO, MNDl, MND2, MPDl, and MPD2. This circuitry continuously tests whether the photodiode voltage DIODE_IN has dropped below an assigned reference level

Vref •

2. A fast path bistable circuit consisting of transistors MNLl, MPL1 and MPL2 along with set and reset transistors MPC, MRGN, and MBLK. This circuit generates a reset pulse RST for transistor MPR that brings the photodiode voltage DIODE_IN back to its initial high level after switching of the comparator has been detected.

3. A slow path regeneration circuit consisting of the pair of common-source amplifiers MPS1-MNS1 and MPS2-MNS2. This circuit controls a transistor MRGN to turn off the reset pulse RST to allow a new integration cycle to proceed.

4. A pulse capture circuit including transistors MPUL, MRST, and MBIT. This circuit senses and stores the reset pulse RST as a signal BIT until it is sampled by a -7 -

clocked output circuit. A transistor MOUT connected to a row select signal SEL gates the cell output onto a column bus used to read the pixel bit stream in a 2D array layout.

The operation of the circuit of Figure 3 is now described with additional reference to the timing diagrams of Figure 4. It should be noted that the time span in Figures 4a and 4b is approximately 200 microseconds, whereas Figure 4c is an expanded view of a 1.6 microsecond interval showing the relationship among several signals involved in reading the pixel value.

During most of each period of oscillation, the reset transistor MPR is turned off, and the diode photocurrent passively reduces the voltage DIODE_IN on the capacitance at the gate of MNDl from a value of approximately 3 volts to a lower voltage V_re__. Before the signal DIODE_IN reaches V_ref, however, it first passes through a value that is a threshold voltage below V_DD. When it does so, the transistor MPS2 is turned on, causing the signal RG1 to rise and the signal RG2 to fall. The signal RG2 reaches a value sufficient to turn off the regeneration transistor MRGN before the signal DIODE_IN reaches the reference level V_ref. As shown in the timing diagrams, in the illustrated embodiment this occurs approximately 20 microseconds before the signal DIODE_IN reaches V_ref. The timing is influenced by various aspects of the circuit including the value of the reference level V_ref, and may be different in alternative embodiments.

Once the signal DIODE_IN reaches V_ref, the comparator output quickly drops below V_DD, turning on transistor MPC and raising its drain voltage BI1 towards V_DD. The positive feedback of the cross-coupled PMOS transistors in the half- latch MPL1-MNL1-MPL2 quickly yanks the voltage BI1 to the positive rail and forces the signal RST at the output of the inverter pair MPL1-MNL1 to ground. This assertion of the signal RST turns on both the reset transistor MPR and the pulse capture transistor MPUL. When MPR is conducting, the diode voltage DIODE_IN and the comparator output are returned to V_DD, and the transistor MPC is turned off. The high diode voltage DIODE_IN also causes the signal RG1 in the two-stage common-source amplifier pair, MPS1-MNS1 and MPS2-MNS2, to switch slowly from V_DD to GND. When the signal RG1 falls to a threshold below V_DD, the output RG2 of the second stage (MPS1-MNS1) switches high rapidly. This in turn causes the regeneration transistor MRGN to conduct, resetting the latch and turning off both transistors MPR and MPUL. The differential pair and the common-source amplifiers are biased in the weak inversion region to reduce power and maximize gain. Because of the low level of current driven by the bias transistors MNSl and MNS2, the common-source amplifiers have a slow fall time and fast rise time. Therefore, the time to propagate a transition from the input to the output of the regeneration circuit is long enough to ensure that the diode voltage DIODE_IN is fully reset to its initial high level before MPR is turned off. Because of the high gain and fast rise of the second stage, the low-to-high transition is very abrupt once the signal RG1 reaches the trip point, roughly V_DD-V_TH. This operation minimizes the time that the input latch might be held at an intermediate level, which would burn static power.

The pulse capture circuit is read and reset once every clock period using the signals PC, SEL and QS . If the oscillator resets during the time between two reads, MPUL turns on and a high value is stored on the gate of MBIT. -9-

During a read operation, the output bus (signal BUS) is first precharged to a high level by precharge circuitry (not shown) responsive to the signal PC. During the next clock cycle, the signal SEL is asserted. The bus is then discharged or not depending on the state of MBIT. After the bit is read, the signal SEL is brought low and the signal QS is brought high to reset the gate of MBIT to GND.

The signal QS is also applied to a blocking transistor MBLK used to prevent a pulse from occurring while the output is being reset by blocking the reset latch. It also serves to refresh the latch input from leakage due to MPC that might otherwise cause premature switching during a long integration time. It should be noted, however, that the blocking transistor is an optional component that may be omitted in alternative embodiments.

In order to build a CMOS imager, the pixels described above are arranged in a regular grid of rows and columns . A row decoder, designed with standard methods, is used to sample one row of the array at a time. Clock signals SEL and QS as described above are gated through the decoder onto the chosen row. The pixels in each column of the array share a single bus line, which is driven by the pixel in the addressed row. At the top of each column a standard circuit is used to precharge the bus line, which the pixel may or may not pull down depending on its state, and to latch the output bit. A multiplexer is used to gate groups of column outputs, stored in the latches, onto output pins. Either or both of the row and column addresses may be supplied externally or generated on-chip using counters or other address-generating circuitry. The data is collected in a high-speed external memory, which is subsequently read into a computer for analysis. Arrays of up to 64 x 64 pixels -10-

have been fabricated, but there are no known technical impediments to realizing larger arrays.

Figures 5 and 6 illustrate some performance aspects of the sigma-delta A/D converter circuit of Figure 3. Figure 5 illustrates the linear response of the pixel to changes in the sampling clock period, T, from 3.2 microseconds to 100 microseconds (corresponding to a range of sampling rates from 312.5 kHz to 10 kHz). Figure 5 shows that the sigma- delta decimated and low-pass-filtered output, expressed as a fraction of saturation, is directly proportional to T, as it should be. Notably, there is no noticeable distortion at sampling rates over 300 kHz. The observed deviations in the measured values from the best line fit are attributed to variations in the light source intensity over the course of the experiment. The measured SNR at 312.5 kHz was greater than 60 dB in mid-range.

Figure 6 shows that the pixel response is also a linear function of incident illumination. The data in Figure 6 were gathered using a sampling rate of 5 kHz and a calibrated monochromatic light source having a wavelength of 600 nm. The slope of the line is related to the conversion gain of the photodiode, the value of the reference level Vr_ef. and the sampling rate. It is estimated that this circuit has the potential for acquiring images with over 120 dB dynamic range with the appropriate combination of these parameters .

It will be apparent to those skilled in the art that modification to and variation of the above-described methods and apparatus are possible without departing from the inventive concepts disclosed herein. Accordingly, the invention should be viewed as limited solely by the scope and spirit of the appended claims.

Claims

-11-CLAIMSWhat is claimed is:

1. A sigma-delta analog-to-digital converter, comprising: an oscillator operative in response to an input analog value to independently oscillate between two signal levels having predetermined separation such that the oscillation frequency has a known relationship with respect to the input analog value; and sampling circuitry operative to sample the oscillator at a known rate above the oscillation frequency to provide a binary output signal from which the analog value can be derived.

2. An asynchronous sigma-delta analog-to-digital converter, comprising: a comparator operative to provide a comparator output signal indicating whether an input signal has reached a predetermined reference level; a latch circuit operative to assert a pulse signal upon assertion of the comparator output signal; a pulse capture circuit operative to sense the pulse signal and store a corresponding logic value until sampled by a clocked output circuit; and regeneration circuitry operative in response to the pulse signal to (i) reset the input signal to an initial level such that the comparator output signal becomes deasserted, and (ii) reset the latch circuit and deassert the pulse signal after sensed by the pulse capture circuit, the regeneration circuitry being further operative to (i) enable an external device to control the value of the input signal in the absence of the pulse signal and (ii) enable -12-

the setting of the latch circuit and assertion of the pulse signal as the input signal approaches the reference level.