WO1999049377A1

WO1999049377A1 - Circuit for controlling and measuring the load current through a load

Info

Publication number: WO1999049377A1
Application number: PCT/DE1999/000310
Authority: WO
Inventors: Rainald Sander; Peter Sommer; Jenö Tihanyi
Original assignee: Infineon Technologies Ag
Priority date: 1998-03-24
Filing date: 1999-02-04
Publication date: 1999-09-30
Also published as: EP1066552A1; DE19812920A1; JP2002508542A; DE19812920C2

Abstract

The invention relates to a circuit for controlling the current flow (IL) through a load (RL) as said current flow (IL) is measured using the current-sense principle. The inventive circuit has a first transistor pair (P1) consisting of a first load and auxiliary transistor (T11, T21) which have a common control terminal (G1) and which each have a first load path terminal (S). The load (RL) is connected to the first load path terminal (S) of the first load transistor (T11). A measuring arrangement (MA) is connected to the first load path terminal (S) of the first load transistor (T11) by a first input terminal (EK1) and to the first load path terminal (S) of the first auxiliary transistor (T12) by a second input terminal (EK2), and has an output terminal (AK) on which a current flow signal (UA) can be tapped. At least one other load transistor (T12, T1n) is connected in parallel with the first load transistor (11), said other load transistor being controlled by another control terminal (G2, Gn) in dependence on the current (IL) flowing through the load.

Description

description

Circuit arrangement for the control and detection of the load current through a load

The present invention relates to a circuit arrangement for controlling and detecting the load current through a load

- A first pair of transistors from a first load transistor and a first auxiliary transistor, which have a common first control connection and each have a load path and a first load path connection, the load being connected in series with the load path of the first load transistor and this series connection between terminals for supply potential and Reference potential is switched;

a current measuring arrangement with a first input terminal connected to the first load path connection of the first load transistor, a second input terminal connected to the first load path connection of the first auxiliary transistor and an output terminal from which a signal dependent on the load current can be tapped;

- A control unit connected to the first control connection.

In such circuit arrangements, the load current through the load is measured according to the so-called “current sense principle”. Here, the load current flowing into the load, possibly very large, via the first load transistor is indirectly measured via a measurement current flowing through the first auxiliary transistor determined, the ratio of load current to measurement current corresponding to the transistor area ratio of the first load transistor to the first auxiliary transistor if the first load transistor and the first auxiliary transistor are in the same Operating point are operated. In order to set the common operating point, the first load transistor and the first auxiliary transistor have a common first control connection and they are connected to an identical supply potential. A control arrangement, which is part of the measuring arrangement, also causes the potential at the first load path connection of the first auxiliary transistor to adjust to the value of the potential of the first load path connection of the first load transistor. The same voltage is thus present between the common control connection and the first load path connections of the two transistors. Likewise, the voltage across the load path of the first load transistor corresponds to the voltage across the load path of the first auxiliary transistor; the two transistors are operated at the same operating point.

The control arrangement for setting the same potential at the first load path connections usually consists of a comparator which is connected on the input side to the load path connections of the two transistors via the input terminals of the measuring arrangement. On the output side, the comparator controls a control transistor, the load path of which is connected in series with the load path of the first auxiliary transistor. If the potentials of the first load path connections of the first load transistor and the first auxiliary transistor differ from one another, the resistance of the load path of the control transistor, or the current flowing over the load path of the control transistor, is readjusted via the comparator connected to the control input of the control transistor until ideally none There is a voltage difference between the potentials of the first load path connections and the first load transistor and the first auxiliary transistor are at the same operating point.

Disadvantageously, comparators, in particular comparators that are manufactured in integrated CMOS technology, have an inevitable voltage offset, which in the present case In this case, readjustment of the control transistor no longer takes place when there is a voltage difference corresponding to the voltage offset between the potentials of the first load path connections of the first load transistor and the first auxiliary transistor. The voltage across the load path of the first auxiliary transistor thus always deviates by the amount of the voltage offset from the voltage across the load path of the first load transistor, ie the first load transistor and the first auxiliary transistor are not exactly at the same operating point.

In the case of large load currents and a correspondingly large voltage drop across the load path of the first load transistor, this deviation of the load path voltage of the first auxiliary transistor by the value of the voltage offset, which is usually in the range of a few millivolts, is of little importance. However, if very small load currents flow, which cause a very small voltage drop across the load path of the first load transistor, which in extreme cases lies in the range of the voltage offset, this voltage offset has a considerable effect on the operating point setting of the first auxiliary transistor. The operating points of the two transistors differ considerably from one another, the measuring current is no longer proportional to the load current; the measurement result is falsified.

The aim of the present invention is therefore to provide a circuit arrangement for controlling and detecting the load current of a load which, even with small load currents or with small voltage drops over the load path of the first load transistor, delivers an exact measurement signal proportional to the load current.

This goal is achieved in the circuit arrangement mentioned at the outset in that at least one second load transistor connected in parallel with the first load transistor is provided, which is connected via a second control terminal through the Control unit can be controlled depending on the load current or depending on a load path voltage occurring across the load path of the load transistors.

The second load transistor, which is also connected to the load with a first load path connection and to supply potential via a second load path connection, can be controlled independently of the first load transistor via the control connection. With large load currents, both the first load transistor and the at least one second load transistor are driven; the load current results from the sum of the current flowing over the load paths of the first and the at least one second load transistor, the load transistors preferably being identical, so that the load current is distributed uniformly over the load transistors. Both the first and the at least one second load transistor and the first auxiliary transistor are operated at the same operating point; the measuring current flowing through the first auxiliary transistor is proportional to the current flowing over the load path of one of the load transistors in accordance with the area ratio of the first auxiliary transistor to the load transistors. When evaluating the measuring current, in addition to this area ratio, the number of controlled load transistors has to be taken into account in order to determine the load current which results from the sum of the currents flowing over the load paths of the load transistors.

A reduction in the load current brings about a reduction in the currents flowing over the load paths of the load transistors and thus a reduction in the voltage drop over the load paths of these transistors. The present invention enables the at least one second load transistor to be switched off when the load current or the load path voltage of the load transistors becomes smaller, as a result of which the remaining load transistor - or possibly the remaining load transistors - take over the current of the switched-off load transistor. This increases the load Line voltage of the remaining load transistors. This ensures that the voltage across the load path of the first load transistor does not drop to a voltage value that is in the range of the voltage offset. The disadvantages described above, according to which there are operating point deviations which falsify the measurement result at small load path voltages, do not exist in the circuit arrangement according to the invention.

The voltage increase across the load path of the remaining load transistor (s) caused by switching off one or more load transistors causes a reduction in the voltage drop across the load and thus a reduction in the load current, but this change is due to the usual supply potential of 15 V and one across the load path of the load transistors falling voltage, which is in the range of a few millivolts to approximately one volt, is negligible.

Advantageous embodiments of the invention are the subject of the dependent claims.

One embodiment of the invention provides for at least one second auxiliary transistor to be connected in parallel with the first auxiliary transistor and to be controllable via the second control connection. The at least one second load transistor and the at least one second auxiliary transistor form a second transistor pair in accordance with the first transistor pair. If further air transistors are provided, further transistor pairs are formed by providing further auxiliary transistors, with each load transistor preferably being supplemented by an auxiliary transistor to form a transistor pair. The second auxiliary transistor, which is also connected to the second input terminal of the measuring arrangement with a first load path connection, maps the load path current flowing through the second load transistor to the measuring current. The load transistors are preferably identical to one another and the auxiliary transistors are identical to one another, so that in this embodiment of the invention the measurement current is always the same fraction of the load current, the ratio of load current to measurement current corresponding to the area ratio between load and auxiliary transistors. When evaluating the measuring current in this embodiment, the number of load transistors controlled to switch on the load does not have to be taken into account separately.

To control the load and auxiliary transistors, a control unit is provided which is connected via output terminals to the control connections of the load or the load and auxiliary transistors, with control of the individual control connections depending on the current flowing through the load or depending on of the voltage across the load path of the load transistors. To determine the current flowing through the load, the control unit is preferably connected with an input terminal to the output terminal of the measuring arrangement or to determine the load path voltage at the nodes common to the load and the first load path connections of the load transistors.

One embodiment of the invention provides that the control unit has an arrangement of switches, in each case one switch being connected to a control connection via an output terminal in order to connect the control connection to an upper or a lower control potential. The upper control potential is selected so that the load transistors always conduct when the control connection is connected to the upper control potential. The upper control potential is therefore preferably selected to be greater than the supply potential. If the control connections are at the lower control potential, the load transistors do not conduct. The lower control potential preferably corresponds to the reference potential or the potential of the first load path connections of the load transistors. A control is required to control the switches 7

Control circuit is provided which, depending on the current flowing through the load or depending on the load path voltage of the load transistors, controls the switches.

The invention is explained in more detail in the exemplary embodiments with reference to figures. Show it:

1: a first embodiment of the circuit arrangement according to the invention;

2: a second embodiment of the circuit arrangement according to the invention;

3: modified circuit arrangement according to FIG. 2.

Unless otherwise stated, the same reference symbols in the figures denote the same parts with the same meaning.

The invention is described below using n-channel FET for the load and auxiliary transistors, the first load path connection corresponding to the source connection, the second load path connection corresponding to the dram connection and the control connection corresponding to the gate connection of the transistors.

Fig. 1 shows a circuit diagram of the circuit arrangement according to the invention according to a first embodiment. The circuit arrangement has a first pair of transistors P1 consisting of a first load transistor TU and a first auxiliary transistor T21, which are connected on the dram side to a supply potential V + and whose gate connections G are connected to one another to form a common first control connection Gl. A variable load R _{L can be} connected between the source terminal S of the load transistor TU and a reference potential M, which is shown in the illustrated embodiment as an ohmic resistor. 8th

The circuit arrangement also has a measuring arrangement MA with a first input terminal EK1, which is connected to the source terminal S of the first load transistor TU, with a second input terminal EK2, which is connected to the source terminal S of the first auxiliary transistor T21, and with an output terminal AK, from which a signal U _{A can be} tapped which is proportional to a load current I _L flowing through the load R _^ .

In parallel to the first load transistor TU, two further load transistors T12, Tln are connected, which are also connected to the supply potential V + on the dram side and to the load R _L and the first input terminal EK1 of the measuring arrangement MA on the source side. The further load transistors T12, Tln can be controlled via further control connections G2, Gn, which are each connected to the gate connections G of the further load transistors T12, Tln.

The task of the circuit arrangement shown is, on the one hand, to switch the load R to the supply potential V + via the load transistors TU, T12, Tln and, on the other hand, to measure the load current I _L flowing through the load R _L. To control the load transistors TU, T12, Tln, which are preferably designed as power FETs, a control unit AE is provided, which is connected to the control connections Gl, G2, Gn of the load transistors TU, T12, Tln via output terminals AI, A2, An. Depending on requirements, there is the possibility, as shown by dots in FIG. 1, to connect further load transistors in parallel to the first load transistor TU and to control them via further outputs of the control unit AE. To control the load transistors TU, T12, Tln, the control connections Gl, G2, Gn are placed separately from one another at an upper or a lower control potential, the upper control potential being selected such that the load transistors TU, T12, Tln conduct when the upper one Control potential is present at the respective control connections Gl, G2, Gn, and can also be kept conductive as long as Load current I _{L flows} through the load R _L. The upper control potential is therefore preferably greater than the supply potential V +. The lower control potential is selected so that the load transistors TU, T12, Tln do not conduct when the lower control potential is applied to the control connections Gl, G2, Gn.

To switch on the load R to supply potential V +, at least one of the load transistors TU, T12, Tln is controlled by the control unit AE. For this purpose, it receives a start signal via a control input EN, for example. In order to enable a measurement of the load current I _L , at least the load transistor TU must be controlled for the present exemplary embodiment in order to connect the load R _L to the supply potential V +. Like many of the other load transistors T12, Tln are required for turning, is by the current flowing through the load R _L load current I _L and depends on the dimensioning of the first transistors TU, T12, Tln, which can be operated without destruction only up to a maximum load path current. The first transistors TU, T12, Tln are preferably dimensioned identically, so that the load current I _{L is} evenly distributed over the driven first transistors TU, T12, Tln. To determine the flowing load current I _L and thus to determine the number of the first transistors TU, T12, Tln to be controlled, the control unit AE is connected with an input terminal EK to the output terminal AK of the measuring arrangement MA, at which a load current I _L flowing to the proportional measurement signal U _A is present.

The load current I _L is measured via the first

Auxiliary transistor T21 and the measuring arrangement MA. The measuring arrangement MA has a comparator K, which on the input side via the first input terminal EK1 to the load R or the source terminal S of the first load transistor TU and via the second input terminal EK2 to the source terminal of the first

Auxiliary transistor T21 is connected. On the output side of the comparator K, a control transistor T3 is connected 1 0

Load path DS is connected in series with the load path DS of the second transistor T21. The load path DS of the control transistor T3 is followed by a current sensing resistor R _s , which is connected to the reference potential M with a terminal.

The principle of current measurement with the illustrated second transistor T21 and the measuring arrangement MA is based on the so-called “current sense principle” and is based on operating the first load transistor TU and the first auxiliary transistor T21 at the same operating point, so that the source current I _s ι of the first auxiliary transistor T21 is proportional to the source current Isn of the first load transistor TU, the source current I _s2 ι of the second auxiliary transistor T21 as measurement current in the current sensing resistor R _s causing a voltage which can be tapped as measurement signal U _A. The ratio of the source currents I _s21 to I _s n corresponds to the ratio of the transistor area of the auxiliary transistor T21 to the transistor area of the load transistor TU when the two transistors TU, T21 are operated at the same operating point The transistor area of the load transistor TU designed as a power FET is a multiple, possibly a multiple by a few powers of ten, the transistor area of the auxiliary transistor T21. In order to set the auxiliary transistor T21 to the same operating point as the first transistor TU, the comparator K compares the source potentials of the load and auxiliary transistors TU, T21 and regulates the source current I _S2 i of the auxiliary transistor T21 via the control transistor T3 until the voltage difference is almost 0 between the source potential of the first load transistor TU and the source potential of the first auxiliary transistor T21.

The control is carried out in such a way that the gate-source capacitance of the control transistor T3, shown in broken lines in the figures, is charged or discharged via the output of the comparator K, depending on the sign of the voltage between the comparator input terminals, by the conductivity of the load path of the control transistor T3 or its load route 11 increase or decrease. The comparator K be ^{¬ has} an inevitable voltage offset V _0FF , which means that no charge or discharge current flows to the gate-source capacitance C _GS even if a voltage corresponding to the voltage offset V _OFF between its input terminal is present. As a result, a deviation of the two source potentials by the value of the voltage offset V _{0FF of} the comparator K is inevitable. This voltage offset V _0FF has an insignificant effect on the measurement result, as long as the voltage U _D sn across the load path DS of the first load transistor TU is substantially greater than the voltage offset V _0FF by which the voltage across the Load path D-S of the auxiliary transistor T21 deviates from the load path voltage U _D sn of the first load transistor TU. The load and auxiliary transistor TU, T21 can then be regarded as being operated at the same operating point.

The advantage of the circuit arrangement according to the invention shown is that the voltage across the load path DS of the load transistor TU can always be kept sufficiently above the value of the voltage offset V _0FF , so that this voltage offset V _{0FF has} only an insignificant effect on the measurement result. When a large load current I _{L flows} , in addition to the first load transistor TU, the control unit AE controls further load transistors T12, Tln, which take over the load current I _L evenly. If the load current I _L now drops, the source currents I _su , I _S i2, Isin of the load transistors TU, T12, Tln decrease, and thus the voltage across the load path DS of the controlled load transistors TU, T12, Tln decreases are operated at the same operating point. If it is assumed for the present exemplary embodiment that initially all three load transistors TU, T12, Tln are activated and the load current drops! __, their source currents I _S n, I _s ι ₂ , Isin and the voltages across them also decrease Load routes DS. If, for example, the load transistor Tln is now switched off, the load current I _{L is distributed} over the two remaining load transistors TU, T12, as a result of which 12 whose source currents I _s _ι, Isι ₂ and the voltages increase across their load paths DS. In this way it can be ensured that the voltage across the load paths DS of the driven load transistors TU, T12 is sufficiently above the value of the voltage offset V _OFF even with small load currents. For safety reasons, in order to prevent the destruction of individual load transistors TU, T12, Tln, all load transistors TU, T12, Tln are first activated to switch on the load path at supply potential V + and then at very low load currents I _L or small load path voltages U _DS n der Load transistors TU, T12, Tln successively switch off individual load transistors TU, T12, Tln until it is ensured that the load path voltage U _D s _ι - of the controlled load transistors TU, T12, Tln is sufficient, preferably by a few factors, above the value of the voltage - Offset V _OFF lies so that an exact measurement result is guaranteed.

In the exemplary embodiment according to Fig. 1 measures the measuring arrangement MA indirectly via the source current I _{s21 of} the auxiliary transistor T21 only the source current I _S n of the first load transistor TU, which, in addition to the other driven, identical load transistors T12, Tln, provides a uniform proportion of the load current! __ . In order to determine the actually flowing load current I _L from the measurement signal U _A, which is proportional to the source current I _S2 ι of the first auxiliary transistor T21, the number of further driven ones is therefore not only the area ratio of the first load transistor TU to the first auxiliary transistor T21 Load transistors T12, Tln to be taken into account. This can be done, for example, by an additional circuit arrangement, not shown in more detail, which is supplied with the measurement signal U _A and an output signal from the control unit AE, which provides information about the number of controlled load transistors TU, T12, Tln.

This disadvantage, the requirement for the additional circuit arrangement, is shown in FIG. 13 form of the circuit arrangement according to the invention. A second auxiliary transistor T2n is assigned to form the second transistor pair Pn, the second auxiliary transistor T2n being connected to the supply potential V + on the drain side and the second input terminal EK2 of the measuring arrangement MA and is connected with its gate terminal G to the gate terminal G of the further load transistor Tln to form a common control terminal Gn. If the further load transistor Tln is driven, the second auxiliary transistor T2n supplies a source current I _s2n to the measuring arrangement MA, which is proportional to the source current I _{sln of} the further load transistor Tln. The ratio of I _s ln to I _s 2n corresponds to the area ratio of the two transistors Tln and T2n, this area ratio preferably being identical to the area ratio of the transistors of the other transistor pairs Pl. The measuring current I _M is then directly proportional to the load current I _L , the proportionality factor increasing the area ratio of load transistors TU, Tln

Auxiliary transistors T21, T2n corresponds. Ideally, all of the load transistors TU, T12 are also identical, and all of the auxiliary transistors T21, T2n are each identical.

FIG. 2 also shows an example of a possible embodiment of the control unit AE, which has a number of switches S1, Sn, which are connected to the outputs AI, at the control unit AE. The control connections Gl, Gn can be applied via these switches to an upper control potential V ++ or to a lower control potential V _s . The switches Sl, Sn are controlled by a control circuit ASS. Whether the load R _{L is to be switched} on via the load transistors TU, Tln depends on a signal applied to a control input EN of the control circuit ASS. If the load R _{L is not to} be connected, the control connections Gl, Gn are switched to via the switches Sl, Sn 14 lower control potential M. If the load R is to be connected, at least one of the control connections Gl, Gn is connected to the upper control potential V ++. The number of load transistors TU, Tln to be controlled depends on the current flowing through the load! ^■ __, the control circuit ASS being connected to the output terminal AK of the measuring arrangement MA for evaluating this current I _L flowing through the load. The upper control potential V ++ is preferably greater than the supply potential V + and can be provided, for example, by a fixed voltage supply or generated from the supply potential V + by means of a charge pump circuit.

FIG. 3 shows the embodiment shown in FIG. 2 in a modified form, the control connections Gl, Gn being able to be connected to the source connections S of the first transistors TU, Tln via the switches S1, Sn, as a result of which the lower supply potential V _s corresponds to the source potential V _{s of} the first transistors TU, Tln. In addition, in the exemplary embodiment shown in FIG. 3, the switches S1, S2, Sn are actuated by the control circuit ASS as a function of the voltage u _DS π occurring across the load path of the controlled load transistors TU, Tln, for which purpose the control circuit ASS is connected to the first load path connections S. of the load transistors TU, Tln is connected, and the potential at the first load path connections in the control circuit ASS is compared with the supply potential V +.

The circuit arrangement according to the invention can be implemented in MOS technology using simple means. Power FETs, such as those used to connect loads, are usually implemented as vertical transistors, the power transistor consisting of a large number of individual transistor cells, their gate, source and drain connections to the gate, source and drain -Connection of the power transistor are interconnected. Now the gate connections will each be a number of these transistor cells 15 combined to form different gate connections, this results in the parallel connection of load transistors shown in the exemplary embodiments with a common drain and source connection but separate gate connections.

Claims

16 claims

1. Circuit arrangement for controlling and detecting the load current (IτJ through a load (R) with

- A first transistor pair (Pl) from a first load transistor (TU) and a first auxiliary transistor (T21), which have a common first control connection (Gl) and each have a load path (DS) and a first load path connection (S), the Load (R _L ) in series to

Load path (D-S) of the first load transistor (TU) is connected and this series circuit is connected between terminals for supply potential (V +) and reference potential (M);

- A current measuring arrangement (MA) with a first input terminal (EK) connected to the first load path connection (S) of the first load transistor (TU), a second input terminal (EK2) connected to the first load path connection (S) of the first auxiliary transistor (T21) and one output terminal (AK) to which a dependent on the load current (I _L) signal (U _a) can be tapped;

- A control unit (AE) connected to the control connection (Gl);

characterized in that at least one second load transistor (T12, Tln) connected in parallel with the first load transistor (TU) is provided, which via a second control connection (G2, Gn) through the control unit (AE) depending on the load current (I _L ) or depending on a load path voltage (Usn) occurring across the load path (DS) of the load transistors (TU, T12, Tln).

2. Circuit arrangement according to claim 1, characterized in that at least one 17 second auxiliary transistor (T2n) connected in parallel to the first auxiliary transistor (T21) is provided to form a second transistor pair (Pn) which can be controlled via the second control connection (Gn).

3. Circuit arrangement according to Claim 2, characterized in that the area ratio of the load transistors (TU, Tln) and auxiliary transistors (Tln, T2n) of all transistor pairs (P2, Pn) is the same.

4. Circuit arrangement according to one of the preceding claims, so that an input terminal (EK) of the control unit (AE) is connected to the output terminal (AK) of the measuring arrangement (MA).

5. Circuit arrangement according to one of the preceding claims, thus ensuring that the input terminal (EK) of the control unit (AE) is connected to the first load path connections (S) of the load transistors (TU, T12, Tln).

6. Circuit arrangement according to one of the preceding claims, characterized in that the control unit (AE) for connection to the control connections (Gl, G2, Gn) output terminals (AI, A2, An) and switches (Sl, connected to the output terminals) S2, Sn), which is controlled by a control circuit (ASS), the output terminals (AI, A2, An) depending on the load current (I) or the load path voltage (UD _SH ) of the first load transistors (TU, T12, Tln) at terminals for Connect an upper or lower control potential (V ++, M; V _s ).

7. Circuit arrangement according to claim 6, so that the identification mark is that the lower control potential (M; V _s ) is the reference potential (M). 18th

8. A circuit arrangement according to claim 7, characterized in that the lower control potential (M; V _Ξ ) is a load path connection potential (V _s ) of the load transistors (TU, T12, Tln).

9. Circuit arrangement according to one of the preceding claims, so that the measuring arrangement (MA) has a comparator (K) connected on the input side to the input terminals (EK1, EK2) and the output side to a control connection (G) of a control transistor (T3) is connected, a current sensing resistor (R _s ) being connected downstream of the control transistor (T3) at a load path connection (D) and a second load path connection (S) of the control transistor (T3) being connected to the second input terminal (EK2) .

10. Circuit arrangement according to one of the preceding claims, that is, that the load path transistors (TU, T12, Tln) and the auxiliary transistors (T21, T2n) as an n-channel FET and the control transistor (T3) as a p - Channel FET are formed.

REPLACEMENT SHEET (RULE 27)