WO1999050889A2 - Printed insulators for active and passive electronic devices - Google Patents

Printed insulators for active and passive electronic devices Download PDF

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Publication number
WO1999050889A2
WO1999050889A2 PCT/US1999/006454 US9906454W WO9950889A2 WO 1999050889 A2 WO1999050889 A2 WO 1999050889A2 US 9906454 W US9906454 W US 9906454W WO 9950889 A2 WO9950889 A2 WO 9950889A2
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Prior art keywords
printing
insulators
printed
insulator
further including
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PCT/US1999/006454
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French (fr)
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WO1999050889A3 (en
Inventor
Sigurd Wagner
Helena Gleskova
Dashen Shen
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Trustees Of Princeton University
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Priority to AU32031/99A priority Critical patent/AU3203199A/en
Publication of WO1999050889A2 publication Critical patent/WO1999050889A2/en
Publication of WO1999050889A3 publication Critical patent/WO1999050889A3/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02282—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating
    • H01L21/02288—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process liquid deposition, e.g. spin-coating, sol-gel techniques, spray coating printing, e.g. ink-jet printing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02118—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer carbon based polymeric organic or inorganic material, e.g. polyimides, poly cyclobutene or PVC
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28158—Making the insulator
    • H01L21/28167—Making the insulator on single crystalline silicon, e.g. using a liquid, i.e. chemical oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/16—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits
    • H01L25/167—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different main groups of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. forming hybrid circuits comprising optoelectronic devices, e.g. LED, photodiodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H01L29/6675—Amorphous silicon or polysilicon transistors
    • H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66083—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by variation of the electric current supplied or the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. two-terminal devices
    • H01L29/66181—Conductor-insulator-semiconductor capacitors, e.g. trench capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Definitions

  • the present invention relates to methods of manufacturing macroelectronic products for the mass market where low cost is essential. Low cost is achieved by (a) using simple fabrication steps, (b) using few steps, and
  • TFT thin-film transistor
  • Printing in many forms has been applied to electronic products. Examples include the printed conductors on wire boards and printed compound semiconductors such as cadmium telluride for solar cells. However, no insulator has yet been printed as part of a transistor.
  • Insulators perform key functions in electrical, electronic and optoelectronic products. In semi-conductor electronics and optoelectronics, insulators may serve in only a passive function to prevent the flow of current, or in an active function as part of field effect devices.
  • the best-known active insulator is the gate dielectric in metal-oxide-silicon (MOS) storage capacitors and in MOS field effect transistors (MOSFETS).
  • MOS metal-oxide-silicon
  • MOSFETS MOS field effect transistors
  • Integrated circuits owe much of their present dominance to the development of the high-quality gate dielectric, which is thermally grown, native, silicon dioxide, and has a high-quality interface with the semiconductor silicon. Alternatives to this thermal silicon oxide have been sought for a variety of reasons.
  • One alternative is deposited silicon dioxide which has been pursued because it requires a smaller thermal budget than thermal silicon dioxide. Another alternative is required as the chip area per bit in dynamic memories keeps shrinking, because the necessary capacitance will have to be achieved by using insulators with higher dielectric constant than that of silicon dioxide.
  • a third alternative is used in amorphous silicon thin-film transistor technology, where thermal oxide is not compatible with the low-temperature processes used. The need for new active and passive insulators is evident in the nascent field of macroelectronics, also called large-area electronics or giant electronics.
  • Macroelectronic products will find their markets by having very low cost per area, rather than per function as is the case for conventional microelectronics.
  • Typical examples of future macroelectronic products include disposable, intelligent shipping/shopping labels, digital wallpaper, and dial-your-pattern dresses. Clearly, all of these must be made at low cost per area.
  • These products still must be inexpensive even when they include transistor electronics, input/output devices such as antennae, optoelectronic functions including photodetectors and light-emitting diodes, and microelectromechanical devices.
  • An analysis of the sources of cost shows that circuit costs can be brought down orders of magnitude below present-day cost if simple, rapid manufacturing techniques are combined with techniques that minimize materials consumption.
  • a process for printing gate dielectrics in thin film transistors is provided.
  • the dielectrics are based on organic polymers, and can be printed by several techniques, including xerographic printing and inkjet printing.
  • the maximum process temperature is approximately 160°C. This is considered a relatively low temperature, i.e. less that 200°C. Of course, the process temperatures are limited by the materials used and could be increased if materials permit.
  • This printing technique is appropriate for thin film transistor electronics and other macroelectronic circuits made on low-temperature substrates.
  • FIG. 1 is a diagram of a pattern for measuring the resistance of printed toner insulator.
  • FIG. 2 is a plot of the current- voltage characteristic of one of the crossovers of FIG. 1.
  • FIG. 3 is a schematic cross section through an MIS capacitor that incorporates a printed gate insulator.
  • FIG. 4 is a plot of the capacitance- voltage curve of the MIS capacitor shown in FIG. 3.
  • FIG. 5 is a schematic cross section through an MIS field effect transistor that incorporates a printed gate dielectric.
  • FIG. 6 is a diagram showing the steps for fabrication of poly-Si thin film transistors with polystyrene gate insulator.
  • FIG. 7 is a plot of drain current against drain voltage for several gate voltages for the device of FIG. 6.
  • the present invention relates to a circuit manufacturing technique whereby materials consumption will be reduced by employing additive printing, i.e., by printing the circuit materials only where they are needed in the final product.
  • additive printing i.e., by printing the circuit materials only where they are needed in the final product.
  • a simple analogy is provided by a color print, which is made by printing ink only where needed in the final picture.
  • This additive printing is in contrast to conventional integrated-circuit (I.C.) fabrication. There, each circuit material is applied over the entire surface, and then the unwanted portions are removed selectively in a complicated photolithographic process. The origin of this costly I.C. fabrication procedure lies in the need to control the material properties and its pattern separately.
  • the present invention is a method for fabricating high-quality insulators which are additively printed over selected areas, and perform both active and the passive functions.
  • the electrical insulator materials have the following characteristics: (a) high volume resistivity and dielectric breakdown field strength; (b) printable and processable at the low temperatures of macroelectronic manufacture;
  • (c) interfaces to the device semiconductor with electrical performance similar to the ones of MOS capacitors and MOSFETS.
  • toner is printed in the configuration of an interlevel insulator and tested in its dielectric breakdown strength.
  • Metal-polystyrene Insulator- Silicon (MIS) capacitors have capacitance-voltage characteristics which are similar to those of the MOS capacitors used in the I.C. industry. The latter is key evidence for the functionality of the insulator as the gate dielectric in MIS field-effect transistors.
  • MIS Metal-polystyrene Insulator- Silicon
  • FIG. 1 shows a printed insulator in a specific pattern that is designed on a computer.
  • toner bars were selectively printed on the Cr lines placed at a 90° angle to the bottom lines.
  • One layer of yellow xerographic toner was printed in Area 1 and Area 2.
  • the top Cr lines also were thermally evaporated.
  • the area of overlap between the top and bottom Cr lines is 1 mm 2 .
  • the electrical resistance of the printed insulator was tested using a HP semiconductor parameter analyzer.
  • FIG. 2 shows the typical I-V characteristic for one crossover.
  • the maximum applied voltage was 100V at which the current was less than 1 pA.
  • the current corresponds to a resistivity of more than 10 14 ⁇ cm, and demonstrates an insulator of high quality.
  • a high-quality insulator can be printed in a desired pattern. It also shows that the insulator can be printed by applying a solid, fusible precursor form of the insulator, and using an electrophotographic technique.
  • an insulator was applied from a solution. Five weight percent polystyrene was dissolved in 95 wt.% toluene and the solution spun onto a pre-cleaned silicon wafer. The spin rate was varied from 1,500 to 4,500 rpm to adjust the thickness of the final film. Evaporation of the toluene solvent at 135°C left behind a film of polystyrene. An electrode of indium was deposited on top of the polystyrene film. The silicon wafer was p- type with a resistivity of 4 to 6 ⁇ cm, and the polystyrene film was 700 nm thick. The area of the indium electrode was 2.5 mm 2 .
  • FIG. 3 is a sketch of a piece of silicon wafer with a back contract, the polystyrene film and the top electrode.
  • the structure of FIG. 3 is that of an MIS capacitor.
  • the capacitance- voltage characteristic of this capacitor was tested with a measurement frequency of 1 MHz and a ramp rate of 1 V s "1 .
  • the resulting capacitance- voltage curve is shown in FIG. 4.
  • This C-V curve was evaluated for the dopant density of the silicon wafer using the well-known depletion approximation, with a relative dielectric constant of polystyrene, of 3.9.
  • An acceptor dopant density of 1.6x10 15 cm "3 was calculated.
  • the capacitance-voltage characteristic of the MIS capacitor is equivalent to that of a metal/silicon dioxide/silicon capacitor, and demonstrates that the polystyrene film can function as the gate dielectric in a MOSFET.
  • a printable insulator material makes device- quality MIS capacitors. It also shows that the insulator can be applied from solution, which suggests application using an inkjet printer.
  • FIG. 5 A schematic cross section through a field effect transistor is shown in FIG. 5.
  • This schematic is identical to that of a conventional MOSFET, except that the silicon dioxide gate insulator of the MOSFET has been replaced by a printed gate insulator, for example, polystyrene or polyethylene.
  • a printed gate insulator for example, polystyrene or polyethylene.
  • FIG. 5 shows a silicon wafer substrate, i.e., the configuration for comparing the quality of the printed insulator against the quality of conventional I.C. MOSFETSs.
  • the printed insulator's application will primarily be in thin film transistors, where the channel semiconductor material may be amorphous silicon, polycrystalline silicon, or organic semiconductors.
  • These thin film semiconductors are deposited on foreign substrates such as glass, steel, or plastic, either rigid plates or flexible foils.
  • substrates such as glass, steel, or plastic
  • rigid plates or flexible foils either rigid plates or flexible foils.
  • the remainder of the structure may be fabricated in many different ways, including printing. If the substrate is a thin foil, it can be run continuously through printing equipment at any process step. If the substrate is rigid, printing techniques appropriate for the printing of plates would be applied.
  • FIG. 6 is a diagram of the steps involved in fabricating poly-Si thin film transistors in accordance with the invention.
  • the poly-Si layer is deposited onto a glass substrate.
  • the n+ layer is deposited onto the poly-Si layer.
  • source/drain metallization a layer of Cr metal is deposited onto the n+ layer.
  • the Cr metal is patterned.
  • the n+ layer is patterned.
  • polystyrene is deposited onto the patterned source/drain by spinning.
  • the gate is formed by gate metallization by shadow mask.
  • polystyrene is the gate insulator. While this material is spun-on, the plot of FIG. 7 demonstrates that polystyrene insulation is effective.

Abstract

A process for printing gate dielectrics in thin film transistors is provided. The dielectrics are based on organic polymers, and can be printed by several techniques, including xerographic printing and inkjet printing. The maximum process temperature is approximately 160 °C. This printing technique is appropriate for thin film transistor electronics and other macroelectronic circuits made on low-temperature substrates.

Description

PRINTED INSULATORS FOR ACTIVE AND PASSIVE ELECTRONIC DEVICES
SPECIFICATION BACKGROUND OF THE INVENTION
FIELD OF THE INVENTION
The present invention relates to methods of manufacturing macroelectronic products for the mass market where low cost is essential. Low cost is achieved by (a) using simple fabrication steps, (b) using few steps, and
(c) using only the material that remains in the product so that there is no waste. When manufacturing macroelectronic thin-film transistor (TFT) circuits, printing techniques and materials are required for fabricating insulators and for interlevel insulation. The invention also relates to a printable gate dielectric used in TFT's.
RELATED ART
Printing in many forms has been applied to electronic products. Examples include the printed conductors on wire boards and printed compound semiconductors such as cadmium telluride for solar cells. However, no insulator has yet been printed as part of a transistor.
Insulators perform key functions in electrical, electronic and optoelectronic products. In semi-conductor electronics and optoelectronics, insulators may serve in only a passive function to prevent the flow of current, or in an active function as part of field effect devices. The best-known active insulator is the gate dielectric in metal-oxide-silicon (MOS) storage capacitors and in MOS field effect transistors (MOSFETS). Integrated circuits owe much of their present dominance to the development of the high-quality gate dielectric, which is thermally grown, native, silicon dioxide, and has a high-quality interface with the semiconductor silicon. Alternatives to this thermal silicon oxide have been sought for a variety of reasons. One alternative is deposited silicon dioxide which has been pursued because it requires a smaller thermal budget than thermal silicon dioxide. Another alternative is required as the chip area per bit in dynamic memories keeps shrinking, because the necessary capacitance will have to be achieved by using insulators with higher dielectric constant than that of silicon dioxide. A third alternative is used in amorphous silicon thin-film transistor technology, where thermal oxide is not compatible with the low-temperature processes used. The need for new active and passive insulators is evident in the nascent field of macroelectronics, also called large-area electronics or giant electronics.
Macroelectronic products will find their markets by having very low cost per area, rather than per function as is the case for conventional microelectronics. Typical examples of future macroelectronic products include disposable, intelligent shipping/shopping labels, digital wallpaper, and dial-your-pattern dresses. Clearly, all of these must be made at low cost per area. These products still must be inexpensive even when they include transistor electronics, input/output devices such as antennae, optoelectronic functions including photodetectors and light-emitting diodes, and microelectromechanical devices. An analysis of the sources of cost shows that circuit costs can be brought down orders of magnitude below present-day cost if simple, rapid manufacturing techniques are combined with techniques that minimize materials consumption.
OBJECTS AND SUMMARY OF THE INVENTION It is an object of this invention to provide a method of manufacturing macroelectronic circuits.
It is a further object of this invention to provide a method of manufacturing macroelectronic circuits, which results in low cost and high yield.
It is yet another object of this invention to provide a method for manufacturing electronic circuits in a continuous process.
It is still a further object of the invention to provide a method of manufacturing electronic circuits where insulators are printed. It is another object of the invention to provide a method of manufacturing thin-film transistor circuits using printable insulators.
It is a still further object of the invention to provide printable insulators for interlevel insulation.
A process for printing gate dielectrics in thin film transistors is provided. The dielectrics are based on organic polymers, and can be printed by several techniques, including xerographic printing and inkjet printing. The maximum process temperature is approximately 160°C. This is considered a relatively low temperature, i.e. less that 200°C. Of course, the process temperatures are limited by the materials used and could be increased if materials permit. This printing technique is appropriate for thin film transistor electronics and other macroelectronic circuits made on low-temperature substrates.
BRIEF DESCRIPTION OF THE FIGURES These, as well as further objects and advantages of the method of the present invention will become apparent to those skilled in the art from a review of the following detailed specification, reference being made to the accompanying drawings.
FIG. 1 is a diagram of a pattern for measuring the resistance of printed toner insulator.
FIG. 2 is a plot of the current- voltage characteristic of one of the crossovers of FIG. 1. FIG. 3 is a schematic cross section through an MIS capacitor that incorporates a printed gate insulator.
FIG. 4 is a plot of the capacitance- voltage curve of the MIS capacitor shown in FIG. 3.
FIG. 5 is a schematic cross section through an MIS field effect transistor that incorporates a printed gate dielectric.
FIG. 6 is a diagram showing the steps for fabrication of poly-Si thin film transistors with polystyrene gate insulator.
FIG. 7 is a plot of drain current against drain voltage for several gate voltages for the device of FIG. 6.
DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a circuit manufacturing technique whereby materials consumption will be reduced by employing additive printing, i.e., by printing the circuit materials only where they are needed in the final product. A simple analogy is provided by a color print, which is made by printing ink only where needed in the final picture. This additive printing is in contrast to conventional integrated-circuit (I.C.) fabrication. There, each circuit material is applied over the entire surface, and then the unwanted portions are removed selectively in a complicated photolithographic process. The origin of this costly I.C. fabrication procedure lies in the need to control the material properties and its pattern separately. In contrast, developing the bulk properties and shape of a given circuit material in a single, additive step is a key objective in the development of the macroelectronic industry, and represents a radical departure from present circuit manufacturing practice. The present invention is a method for fabricating high-quality insulators which are additively printed over selected areas, and perform both active and the passive functions. The electrical insulator materials have the following characteristics: (a) high volume resistivity and dielectric breakdown field strength; (b) printable and processable at the low temperatures of macroelectronic manufacture;
(c) interfaces to the device semiconductor with electrical performance similar to the ones of MOS capacitors and MOSFETS.
Many organic materials meet conditions (a) and (b). Examples are polystyrene and polyethylene. The volume resistivities of these materials lie above 1012 Ωcm, their breakdown strength can reach several Mv/cm, their use as the body of xerographic toner particles shows that they can be made in printable form, and that they can be fused at temperatures near 100°C. The typical fusing procedure in XEROX® and laser printers only makes the toner particles stick to each other and to the paper. In the methods of the present invention involving the use of toner as lithographic etch mask, it has been shown that the toner can be fused to one homogeneous layer at temperatures between 120° and 160°C [Electrophotographic Patterning of Thin-film Silicon on Glass Foil, H. Gleskova, S. Wagner and D.S. Shen, IEEE Electron Device Letters, vol. 16, pp. 418-420 (1995)]. In the present invention, these insulators also meet condition (c), above.
In the invention, toner is printed in the configuration of an interlevel insulator and tested in its dielectric breakdown strength. Metal-polystyrene Insulator- Silicon (MIS) capacitors have capacitance-voltage characteristics which are similar to those of the MOS capacitors used in the I.C. industry. The latter is key evidence for the functionality of the insulator as the gate dielectric in MIS field-effect transistors.
FIG. 1 shows a printed insulator in a specific pattern that is designed on a computer. First, parallel 100-nm-thick Cr. lines were thermally evaporated on a glass substrate. Using a HP Laser Jet printer, toner bars were selectively printed on the Cr lines placed at a 90° angle to the bottom lines. One layer of yellow xerographic toner was printed in Area 1 and Area 2. To raise the breakdown voltage and increase surface smoothness, the toner was post-baked on a hot plate in air for 30 sec. The thickness of the toner layer was 33 μm. The top Cr lines also were thermally evaporated. The area of overlap between the top and bottom Cr lines is 1 mm2. The electrical resistance of the printed insulator was tested using a HP semiconductor parameter analyzer.
FIG. 2 shows the typical I-V characteristic for one crossover. The maximum applied voltage was 100V at which the current was less than 1 pA. The current corresponds to a resistivity of more than 1014 Ωcm, and demonstrates an insulator of high quality.
This demonstrates that a high-quality insulator can be printed in a desired pattern. It also shows that the insulator can be printed by applying a solid, fusible precursor form of the insulator, and using an electrophotographic technique. In the fabrication of an MIS capacitor, an insulator was applied from a solution. Five weight percent polystyrene was dissolved in 95 wt.% toluene and the solution spun onto a pre-cleaned silicon wafer. The spin rate was varied from 1,500 to 4,500 rpm to adjust the thickness of the final film. Evaporation of the toluene solvent at 135°C left behind a film of polystyrene. An electrode of indium was deposited on top of the polystyrene film. The silicon wafer was p- type with a resistivity of 4 to 6 Ωcm, and the polystyrene film was 700 nm thick. The area of the indium electrode was 2.5 mm2.
FIG. 3 is a sketch of a piece of silicon wafer with a back contract, the polystyrene film and the top electrode. The structure of FIG. 3 is that of an MIS capacitor. Using a parameter analyzer, the capacitance- voltage characteristic of this capacitor was tested with a measurement frequency of 1 MHz and a ramp rate of 1 V s"1. The resulting capacitance- voltage curve is shown in FIG. 4. This C-V curve was evaluated for the dopant density of the silicon wafer using the well-known depletion approximation, with a relative dielectric constant of polystyrene, of 3.9. An acceptor dopant density of 1.6x1015 cm"3 was calculated. This value is close to that derived from the wafer resistivity, and again demonstrates the device quality of the polystyrene insulator. Thus, the capacitance-voltage characteristic of the MIS capacitor is equivalent to that of a metal/silicon dioxide/silicon capacitor, and demonstrates that the polystyrene film can function as the gate dielectric in a MOSFET. This demonstrates that a printable insulator material makes device- quality MIS capacitors. It also shows that the insulator can be applied from solution, which suggests application using an inkjet printer.
A schematic cross section through a field effect transistor is shown in FIG. 5. This schematic is identical to that of a conventional MOSFET, except that the silicon dioxide gate insulator of the MOSFET has been replaced by a printed gate insulator, for example, polystyrene or polyethylene. As demonstrated above, such a device can be made by printing the insulator from either a solid or a liquid precursor. FIG. 5 shows a silicon wafer substrate, i.e., the configuration for comparing the quality of the printed insulator against the quality of conventional I.C. MOSFETSs. However, the printed insulator's application will primarily be in thin film transistors, where the channel semiconductor material may be amorphous silicon, polycrystalline silicon, or organic semiconductors. These thin film semiconductors are deposited on foreign substrates such as glass, steel, or plastic, either rigid plates or flexible foils. Thus the remainder of the structure may be fabricated in many different ways, including printing. If the substrate is a thin foil, it can be run continuously through printing equipment at any process step. If the substrate is rigid, printing techniques appropriate for the printing of plates would be applied.
FIG. 6 is a diagram of the steps involved in fabricating poly-Si thin film transistors in accordance with the invention. In the first step, the poly-Si layer is deposited onto a glass substrate. In the second step, the n+ layer is deposited onto the poly-Si layer. In the third step, source/drain metallization, a layer of Cr metal is deposited onto the n+ layer. In the fourth step, the Cr metal is patterned. In the fifth step, the n+ layer is patterned. In the sixth step, polystyrene is deposited onto the patterned source/drain by spinning. In the final step, the gate is formed by gate metallization by shadow mask.
In the method of FIG. 6, polystyrene is the gate insulator. While this material is spun-on, the plot of FIG. 7 demonstrates that polystyrene insulation is effective.
While several advantageous embodiments have been chosen to illustrate the invention, it will be understood by those skilled in the art that various changes and modifications can be made therein without departing from the scope of the invention as defined in the appended claims.

Claims

CLAIMS What is claimed is:
1. A process for manufacturing macroelectronics comprising the steps of: producing thin film electronics; and printing insulators into said thin film electronics as part of said production.
2. The process of claim 1 wherein the step of printing insulators is part of a continuous production process.
3. The process of claim 1 wherein said insulators are formed of a material which has high volume resistivity and dielectric breakdown field strength; are printable; and which interface to the device semiconductor with electrical performance similar to MOS capacitors and MOSFETS.
4. The process of claim 3 wherein the insulators are processable at low temperatures of macroelectronic manufacture.
5. The process of claim 3 wherein said insulator material comprises an organic polymer, or the monomer precursor of an organic polymer.
6. The process of claim 1 wherein said insulators are printed using a solid, fusible precursor form of an insulator material.
7. The process of claim 6 further including the step of printing said insulators by electrophotographic printing
8. The process of claim 3 wherein said insulator material is polystyrene, polyethylene or polyimide or derivatives thereof.
9. The process of claim 1 further including the step of printing said material from solution.
10. The process of claim 9 further including the step of printing said material by ink-jet printing.
11. The process of claim 9 further including the step of printing said material by impact printing.
PCT/US1999/006454 1998-03-27 1999-03-26 Printed insulators for active and passive electronic devices WO1999050889A2 (en)

Priority Applications (1)

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AU32031/99A AU3203199A (en) 1998-03-27 1999-03-26 Printed insulators for active and passive electronic devices

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US7974698P 1998-03-27 1998-03-27
US60/079,746 1998-03-27

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WO1999050889A2 true WO1999050889A2 (en) 1999-10-07
WO1999050889A3 WO1999050889A3 (en) 1999-12-23

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PCT/US1999/006453 WO1999050890A1 (en) 1998-03-27 1999-03-26 Method for making multilayer thin-film electronics
PCT/US1999/006454 WO1999050889A2 (en) 1998-03-27 1999-03-26 Printed insulators for active and passive electronic devices

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WO2003098696A1 (en) * 2002-05-17 2003-11-27 Seiko Epson Corporation Circuit fabrication method
US6686229B2 (en) 2001-03-02 2004-02-03 Koninklijke Philips Electronics N.V. Thin film transistors and method of manufacture
US7906415B2 (en) 2006-07-28 2011-03-15 Xerox Corporation Device having zinc oxide semiconductor and indium/zinc electrode

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EP1684366A1 (en) * 2005-01-25 2006-07-26 Nederlandse Organisatie voor toegepast-natuurwetenschappelijk Onderzoek TNO Electronic device comprising an electronic component and encapsulation members
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US7851336B2 (en) 2008-03-13 2010-12-14 Innovalight, Inc. Method of forming a passivated densified nanoparticle thin film on a substrate
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US6686229B2 (en) 2001-03-02 2004-02-03 Koninklijke Philips Electronics N.V. Thin film transistors and method of manufacture
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WO2003098696A1 (en) * 2002-05-17 2003-11-27 Seiko Epson Corporation Circuit fabrication method
US7198885B2 (en) 2002-05-17 2007-04-03 Seiko Epson Corporation Circuit fabrication method
US7906415B2 (en) 2006-07-28 2011-03-15 Xerox Corporation Device having zinc oxide semiconductor and indium/zinc electrode

Also Published As

Publication number Publication date
AU3203099A (en) 1999-10-18
WO1999050890A1 (en) 1999-10-07
WO1999050889A3 (en) 1999-12-23
AU3203199A (en) 1999-10-18

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