WO1999050903A1

WO1999050903A1 - Semiconductor integrated circuit device and method for manufacturing the same

Info

Publication number: WO1999050903A1
Application number: PCT/JP1998/001434
Authority: WO
Inventors: Shinichi Fukada; Haruo Akahoshi; Kenichi Takeda; Takuya Fukuda
Original assignee: Hitachi, Ltd.
Priority date: 1998-03-30
Filing date: 1998-03-30
Publication date: 1999-10-07

Abstract

A semiconductor integrated circuit device which can operate at a high speed, has a fine wiring pattern, and is improved in reliability. In the circuit device, a semiconductor element is provided in a semiconductor substrate (101), and first wiring (103) made mainly of aluminum is provided on the main surface of the substrate (101) as main surface-side local wiring, and then, second wiring (110) made mainly of copper is provided on the first wiring (103) as global wiring. Via wiring (107) which is brought into contact with the first wiring (103) is made of a conductive material other than Cu.

Description

Description: Semiconductor integrated circuit device and method of manufacturing the same

The present invention relates to the field of semiconductor technology, and more particularly to a semiconductor integrated circuit device capable of operating at high speed and a method of manufacturing the same.

Background art

In system LSI, development of fine wiring technology suitable for high speed and low power consumption is desired.

As for the trend of fine wiring technology, the use of copper-based materials instead of aluminum-based aluminum and aluminum-based alloy materials is increasing. Copper-based interconnects have lower specific resistance, higher electromigration resistance and higher allowable current density in fine patterns than aluminum-based interconnects.

Prior to the study of copper (Cu) -based wiring technology, we investigated known technologies related to the copper-based wiring technology. As a result, the following known technology was discovered.

Japanese Patent Application Laid-Open No. 8-78410 discloses a problem that the Cu wiring is inferior in oxidation resistance, and oxidizes the surface of the Cu wiring so that the Cu wiring is not exposed. , Alsi, Au, Ag or alloys mainly composed of Ag) are disclosed.

Japanese Patent Application Laid-Open No. 9-55429 discloses a method for manufacturing a multilayer wiring structure in which the interlayer insulating film has a low dielectric constant to reduce the capacitance between wirings in a small number of steps. A wiring groove is formed in the interlayer insulating film using a low dielectric constant material such as polyimide, and embedded in the groove. There is disclosed a technology in which only wiring is formed. According to this publication, the underlying wiring is buried in a groove of a silicon oxide film on a semiconductor substrate.

It is disclosed that an A1 wiring is formed, and a first buried wiring and a second buried Cu wiring are formed in an interlayer insulating film (photosensitive polyimide film) groove on the A1 wiring.

JP-A-5-206065 discloses that Cu is selectively deposited only on a desired region by using an electroless deposition process in forming a Cu wiring. More specifically, it discloses that a Cu wiring is formed by electroless Cu plating only on a specific surface using palladium silicide as a catalyst.

Japanese Patent Application Laid-Open No. 6-29246 discloses a Cu wiring technique in which metal is electrolessly plated in a relatively deep and narrow trench in a dielectric substrate.

According to the study by the inventors of the present invention, it is effective to use the A1 wiring for the first layer wiring and the Cu wiring above the second layer from the viewpoint of reliability, cost, etc. in the multilayer wiring using Cu wiring. In addition, they concluded that a plating method that is more advantageous in terms of embedding and cost than the sputtering method and the CVD method will be used as the method for forming the Cu wiring. The details are described below.

In general, the Cu wiring process is more expensive than the A1 wiring process, and it is considered necessary to use the A1 wiring layer and the Cu wiring layer separately for multi-layer wiring depending on the application. Especially multiple semiconductor devices

The first layer wiring (so-called local wiring), which is closest to the (elements) and connects the elements, has a short wiring length and low resistance, and prevents Cu contamination of semiconductor elements. A1 It is considered effective to use Cu wiring for the wiring on the second layer or higher (so-called global wiring).

Known techniques for selectively using the A1 wiring and the Cu wiring include the techniques disclosed in the aforementioned Japanese Patent Application Laid-Open Nos. 8-78410 and 9-55429.

However, the former (Japanese Patent Application Laid-Open No. 8-78410) discloses a technique of providing a wiring such as A1 on a Cu wiring, and there is no idea to apply A1 to a first-layer wiring closest to a semiconductor element. That is, in the invention disclosed in this publication, in order to improve the bonding property with the wire in the pad region, the upper part of the Cu wiring is made of Al, Alsi, Au, Ag or an alloy mainly composed of Ag in addition to AlSiCu. In this way, oxidation of the Cu wiring is suppressed during bonding. That is, the invention disclosed in this publication addresses the problem of the upper surface of the Cu wiring, and there is no idea to apply a wiring material different from Cu as the lower wiring of the Cu wiring.

On the other hand, the latter (JP-A-9-55429) discloses a technique in which a Cu wiring is provided on an A1 wiring. According to the fourth embodiment disclosed in this publication, local wiring is formed by forming a vertical connection hole (through hole) and a wiring groove in a silicon oxide film, forming a film of A1 by a high-temperature sputtering method, and This is achieved by forming vertical connection wiring and embedded A1 wiring by removing the A1 film on the silicon oxide film by chemical mechanical polishing. In addition, the global wiring on the local wiring is formed by forming wiring grooves and vertical connection holes in an interlayer insulating film made of a low dielectric constant resin (specifically, benzocyclobutene). Vertical connection by polishing Cu on low dielectric constant resin film by chemical mechanical polishing method This is achieved by forming wiring and embedded Cii wiring.

The technique disclosed in this publication merely provides a method for forming both the lower layer A1 wiring and the upper Cu wiring including the via wiring by the trench filling wiring technique.

Conventionally, as a specific method of forming a Cu wiring, a Spack method or a CVD method as disclosed in the above-mentioned Japanese Patent Application Laid-Open No. 9-55429 has been considered.

However, in the sputter method, it is difficult to embed in a wiring formation groove having a depth of 400 nm (0.4 μm) or 400 nm or more and a via hole diameter of 0.5 μm or less or a width of 0.35 μm or less. there were. This is because a cavity is formed in the trench due to the overhang of the Cu film. Therefore, there is a limit to miniaturization of wiring. In addition, the CVD method uses an expensive organic compound gas, so it is difficult to reduce the process cost. For the above reasons, it is effective to use the plating method for fine Cu wiring, especially for multilayer wiring.

The method of forming the Cu wiring itself using the plating technique is based on the electroless Cu plating only on a specific surface using a palladium silicide as a catalyst described in JP-A-5-206065. There is a method of forming a wiring, a method of forming a Cu wiring in a deep and narrow wrench by electroless plating, as described in JP-A-6-29246.

However, these publications do not mention any combination with the A1 wiring layer, and the necessity of combining with the A1 wiring layer is not recognized.

The inventors have clarified that there is a problem that has not been assumed in the past when forming a Cu film by the plating method. In other words, if the lower wiring is made of Al (or A1 alloy) and a via wiring is to be formed on the lower wiring by the Cu plating method, the A1 wiring will be corroded.

For forming a Cu film by electroless Cu plating, a strong aqueous solution is used. In addition, when a Cu film is formed by electrolytic plating, it is difficult to fix the pH of the plating solution to around neutral because of controlling the quality of the formed Cu film.

However, A1 is a material that easily corrodes in both acidic and alkaline conditions. Therefore, in the case of Cu plating, A1 corrosion prevention measures are indispensable. However, in practice, it is impossible to completely cover the A 1 surface with a chemically stable conductive film and eliminate the possibility of corrosion at all with fine wiring that allows “missing” . In particular, in order to improve the adhesion between the lower wiring and the Cu plating film, a step of simultaneously performing Cu plating while etching the underlying conductive film is required.

The problem of A1 corrosion due to "missing eyes" will be explained in more detail. When performing Cu plating on the A1 layer or the W layer that constitutes the lower wiring, it is necessary to cover those layers with a material such as TiN, which dissolves slowly in an alkaline atmosphere, to prevent the reaction. However, it is difficult to form a Cu film directly on such a TiN film by electrolytic plating. For this reason, it is necessary to first form a Cu seed layer by electroless plating. However, the electroless plating solution is a strong solution and reacts easily with materials such as A1 used in normal wiring processes to dissolve. And even if it is covered with a material that dissolves slowly in an alkaline atmosphere, such as TiN, and measures are taken to prevent the reaction in the underlying wiring, the effect of preventing the reaction is fully exhibited as the wiring becomes finer. A situation occurs in which it becomes impossible.

That is, the situation occurs in the case of the wiring structure shown in FIG. _{37. c In} FIG. 37, it is attempted to form a Cu electroless plating film in the via hole (127) provided in the insulating film (126). It is sectional drawing which shows wiring connection. In particular, the figure shows a state in which a reaction prevention barrier TiN layer (129) for Cu electroless plating has been formed in the via hole (127) prior to the formation of the Cu electroless plating film.

In FIG. 37, on a semiconductor substrate (121), a TiN film (122), a 0.5% Cu film (123), and a TiN film (124) are stacked via an oxide film (not shown). The layered A1 wiring (125) is formed by dry etching. Then, an insulating film (126) is formed on the A1 wiring (125). In the case of fine wiring, there is not enough space in the via area on the A1 wiring surface, and it is inevitable to allow "missing eyes" where the via hole (127) does not completely overlap the lower wiring. If there is "missing eyes", holes (128 ₎ are easily generated in the wiring side walls due to overetching when forming via holes, and the side walls are exposed. However, no barrier film formation technology has been established to cover these sidewalls with good coverage, leaving a major problem as in the next MECIE.

In other words, when the Cu electroless plating is performed, the plating liquid penetrates into the side wall vacancies, and the A1 wiring is dissolved to cause a defect. This situation does not change even with W wiring. Also, although not as severe as Cu electroless plating, even in the case of sputter or CVD-Cu films, A1 and Cu react through the sidewalls to form high-resistance intermetallic compounds, which may increase wiring resistance. Therefore, there is a problem in the case of A1 wiring. From the above points, when Cu plating on A1 wiring, corrosion can be completely suppressed even if the A1 wiring surface is covered with another conductive film. Absent.

Disclosure of the invention

An object of the present invention is to provide a semiconductor integrated circuit device having a fine wiring pattern capable of operating at high speed and having improved reliability. Another object of the present invention, Tonime ^> ₀ to provide a method of manufacturing a high-speed operable has a fine wiring pattern, and a semiconductor integrated circuit device having improved reliability

Another object of the present invention is to realize a semiconductor integrated circuit device having a fine wiring pattern capable of operating at high speed at low cost.

Another object of the present invention is to provide a semiconductor integrated circuit device having a multilayer wiring structure including a wiring mainly composed of aluminum (A1) and a wiring mainly composed of copper (Cu).

A typical configuration of the present invention has a first wiring on a main surface of a semiconductor substrate, a first interlayer insulating film so as to cover the first wiring, and a first interlayer insulating film formed on the first interlayer insulating film. A first via wiring connected to a part of the first wiring via the provided via hole, a wiring provided in the second interlayer insulating film on the first interlayer insulating film; And a second wiring made of a material different from that of the via wiring and the first wiring, the second wiring being embedded in the groove for use and connected to the first via wiring.

In a more specific configuration of the present invention, a semiconductor element is provided in a semiconductor substrate, and a first wiring mainly composed of aluminum is provided on the main surface of the semiconductor substrate as a local wiring near the main surface of the substrate. A second wiring made of copper as the main material is provided as a global wiring on the first wiring, and the via wiring connected to the first wiring is made of a conductor material different from Cu It is characterized by the following. The via wiring and the third wiring formed on the second wiring are made of a conductive material mainly composed of Cu having a lower specific resistance than A1.

According to the present invention, it is possible to prevent contamination of the semiconductor element with Cu, and the CU wiring (second wiring) in the upper layer is excellent in migration resistance and has a low resistance, so that it can be operated at a high speed because of its small size. A semiconductor integrated circuit device having a wiring pattern and having improved reliability can be obtained.

BRIEF DESCRIPTION OF THE FIGURES

FIG. 1 is a sectional view showing a manufacturing process of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.

FIG. 3 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.

FIG. 4 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.

FIG. 5 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.

FIG. 6 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.

FIG. 7 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.

FIG. 8 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.

FIG. 9 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG. FIG. 10 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.

FIG. 11 is a sectional view showing a manufacturing process of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 12 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.

FIG. 13 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.

FIG. 14 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.

FIG. 15 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.

FIG. 16 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.

FIG. 17 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.

FIG. 18 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.

FIG. 19 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.

FIG. 20 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG.

FIG. 21 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.

FIG. 22 shows a semiconductor integrated circuit device according to a third embodiment of the present invention. FIG. 6 is a cross-sectional view showing a manufacturing process of the second embodiment.

FIG. 23 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.

FIG. 24 is a cross-sectional view showing the manufacturing process of the semiconductor integrated circuit device following FIG. 23.

FIG. 25 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG. 24.

FIG. 26 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG. 25.

FIG. 27 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG.

FIG. 28 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG. 27.

FIG. 29 is a cross-sectional view showing a manufacturing process of the semiconductor integrated circuit device according to the fourth embodiment of the present invention.

FIG. 30 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG. 29.

FIG. 31 is a cross-sectional view showing a manufacturing step of the device following FIG. 30. FIG. 32 is a cross-sectional view showing a manufacturing step of the device following FIG. 31. FIG. 33 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG. 32.

FIG. 34 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG. 33.

FIG. 35 is a cross-sectional view showing a manufacturing step of the semiconductor integrated circuit device following FIG. FIG. 36 is a sectional view showing a semiconductor integrated circuit device according to the fifth embodiment.

FIG. 37 is a sectional view showing a semiconductor integrated circuit device according to a sixth embodiment of the present invention.

FIG. 38 shows a partial cross-sectional view of a multilayer wiring structure which has been a problem of the present inventors.

BEST MODE FOR CARRYING OUT THE INVENTION

Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings. In all the drawings for describing the embodiments, those having the same functions are denoted by the same reference numerals, and their repeated description will be omitted.

First Example>

A method for manufacturing a semiconductor integrated circuit device according to a first embodiment of the present invention will be described with reference to FIGS.

Step (a)

As shown in Fig. 1, first a semiconductor substrate (CZ substrate) (101) consisting of single-crystal Si covered with a CVD-Si02 film or a thermally oxidized Si02 film (102) The wiring (103) is formed. The first wiring (103) is, in order from the bottom, Ti 30nra to improve adhesion to the Si02 film, TiN 70 nm as the barrier layer, Al-0.5 0Cu 300 nm with A1 as the main wiring material, anti-reflection It is composed of laminated wiring in which TiN 50 nm as a layer is sequentially formed by a sputtering method. The first wiring (103) is patterned by a known photolithography technique. In other words, a wiring pattern is formed on the laminated conductor layer deposited on the Si02 film (102) by the sputtering method using a resist (photoresis t lm), transferred to the laminated conductor layer by a dry etching technique, and then transferred to the laminated conductor layer. Then, the first wiring (103) is obtained. This second The first wiring (103) has a shorter wiring length than an upper wiring described later and is a wiring (local wiring) for connecting adjacent elements, for example, about 50 to 60 m.

Although not shown, a pair of a P-channel MISFET (PM〇S) and an N-channel MISFET (NM 0 S) is provided in the main surface of the semiconductor substrate (101) as semiconductor elements constituting a circuit. Multiple CMOS transistors composed of transistors are formed. For example, a plug such as polycrystalline silicon or tungsten is connected to the source / drain region of these CM0S transistors through contact through holes provided in the Si02 film (102). I have. The first wiring (103) is connected to this plug. The semiconductor substrate (101) is a semiconductor substrate in the claims. The semiconductor substrate includes, in addition to the semiconductor substrate (101), a semiconductor substrate having a surface on which an epitaxial layer (for example, a thickness of 1 μm to 4 μm) is formed, that is, a so-called epitaxy wafer.

Step (b)

As shown in FIG. 2, a U02 nm Si02 film (104) is formed on the first wiring (103) by a plasma CVD method. In this state, as shown in the figure, a step (so-called concave portion) is formed on the surface of the Si02 film (104) deposited on the Si02 film (102) where the first wiring is not formed.

Step (c)

The surface of the above-mentioned Si02 film (104) is polished and flattened by chemical mechanical polishing (hereinafter, abbreviated as CMP), and an interconnect having a thickness of 800 on the first wiring (103) is formed. An insulating film, that is, an interlayer insulating film (105) is formed. Then, as shown in Fig. 3, A via hole (106) is formed in the interlayer insulating film (105) by the FI technology. First, a via hole pattern is formed by a resist (not shown) on the interlayer insulating film (105) by a photolithography technique. Then, the via hole pattern is transferred to the interlayer insulating film (105) by a dry etching technique to form a via hole (106), and then the above-mentioned resist is removed. Step (d)

As shown in FIG. 4, a first via wiring (107) is formed in the via hole (106). According to the first embodiment, the connection of the first wiring made of A1 (or A1 alloy) to the via wiring using Cu (or Cu alloy) is avoided from the recognition of the above-described problem. Have been. In other words, Cu should be avoided as a material for via wiring (107) that electrically connects the first wiring (oral wiring) made of A1 and the second wiring (global wiring) made of Cu. And a high melting point metal such as W is applied. The order of forming the via wiring (107) will be described below.

First, Ti 30 nm was formed as an adhesive layer for improving the adhesion to the first wiring and reducing the contact resistance, and TiN 50 nm was formed as a barrier layer for preventing the reaction between the first wiring and the via wiring. Then, a W film is formed to a thickness of 500 nm on the entire surface by CVD. Then, as shown in FIG. 4, the ff film, the TiN film and the Ti film in the flat portion of the interlayer insulating film (105) are polished and removed by a CMP method to form a via wiring (107).

Step (e)

As shown in FIG. 5, a 100 nm SiN film (108) is formed on the entire surface of the interlayer insulating film (105) on which the via wiring (107) is formed by a plasma CVD method, and a Si02 film is formed on the SiN film (108). (109) is deposited to a thickness of 300 nm to form an interlayer insulating film. This inter-wiring insulating film is formed by photolithography technology. A wiring pattern is formed on (108, 109) by a resist (not shown). Next, the Si02 film (109) is etched by dry etching using the resist as a mask. At this time, the lower SiN film (108) acts as an etching stopper. That is, in the dry etching, an etching gas for etching the Si02 film (109) is used. For this reason, the SiN film (108) is not etched by the etching gas for the Si02 film (109). Therefore, the etching of the Si02 film (109) stops at the surface of the SiN film (108). Since the SiN film (108) becomes an etch stop, the lower interlayer insulating film (105) is not etched. Subsequently, by switching the etching gas and etching the SiN film (108), the wiring pattern is transferred to the interlayer insulating film to form a wiring forming groove (wiring groove), and then the above-mentioned resist is removed. .

Step (f)

As shown in FIG. 6, a second wiring (110) is formed in a wiring forming groove (wiring groove) formed in the interlayer insulating film (108, 109).

First, Ti 30 nm and TiN 70 are sequentially formed as an adhesive layer on the main surface of the semiconductor substrate on which the wiring groove is formed, and a Cu film is formed on the TiN by 50 mn by an electroless plating method. Subsequently, a Cu film is further formed to a thickness of 250 nm on the Cu film by an electrolytic plating method. The Cu film and the adhesive layer in the flat portion are polished and removed by the CMP method to form a second wiring (110).

Here, Cu electroless plating is used as a plating solution, 5 mol / l copper sulfate (CuS04) as a copper source, 0.03πιο1 / 1 / formaldehyde (HCH0) as a reducing agent, and 0.1 mol / l as a chelating agent. Using a solution containing ethylenediaminetetraacetic acid (EDTA) 1 and 0.5 mol I 1 of 2,2'-bipyridyl, adjust the viscosity by adding poly (ethylene glycol), pH 13, and liquid temperature 80 ° C. so This is performed by immersing the substrate in this Mek's solution.

The Cu electroplating is performed using a 0.3 mol I 1 copper sulfate (CuS04) solution as a plating solution. The thickness of the formed Cu film is controlled by the plating time. By the above-described two-step mask film formation, a Cu film can be formed with good coverage in the groove pattern.

Process (g)

As shown in Fig. 7, 200nm of SiN film (111) and 600ηπι of Si02 film (112) are deposited on the entire surface of the interlayer insulating film (111, 112) in which the second wiring (110) is embedded by plasma CVD. Then, an interlayer insulating film is formed. By photolithography, a via wiring pattern is formed on this interlayer insulating film by a resist. After processing the Si02 film (112) using the SiN film (111) as the etching stopper by dry etching technology, the via wiring pattern is changed to the interlayer insulating film by switching the etching gas and etching the SiN film (111). Then, via holes (113) are formed, and then the resist is removed.

Process (h)

As shown in FIG. 8, a second via wiring (114) is formed in the via hole (113). First, Ti 30 nm and TiN 70 mn are formed as adhesive layers on the entire surface of the interlayer insulating film (111, 112) in which the via hole (113) is formed, and a 50 nm Cu film is formed on the TiN by electroless plating. On this Cu film, a Cu film is further formed to a thickness of 250 nm by the electrolytic plating method, and the Cu film and the adhesive layer in the flat portion are polished and removed by the CMP method to form a second via wiring (114). The same plating solution as used in the formation of the second wiring (110) is used as the plating solution used for forming the Cu film.

Step (i) As shown in Fig. 9, a 100 nm SiN film (115) and a 300 nm Si02 film (116) are deposited on the entire surface of the interlayer insulating film (111, 112) with via wiring (114) formed by plasma CVD. An insulating film is formed. A wiring pattern is formed on this interlayer insulating film (115, 116) by photolithography using a resist. Next, using the resist as a mask, the Si02 film (116) is etched by dry etching technology. At this time, the lower SiN film (115) acts as an etching stopper. Subsequently, by switching the etching gas and etching the SiN film (115), the wiring pattern is transferred to the interlayer insulating film to form a wiring groove, and then the resist is removed.

Step (j)

As shown in FIG. 10, a third wiring (117) is formed in a wiring groove formed in the interlayer insulating film (115, 116). First, a Ti film of 30 nm and a TiN of 70ηπι are formed on the entire surface of the interlayer insulating film (115, 116) as an adhesive layer, and a Cu film of 50 nm is formed on the TiN by an electroless plating method. On this Cu film, a Cu film is further formed by electrolytic plating, and the flat Cu film and the adhesive layer are polished and removed by a CMP method to form a third wiring (11). Here, as the plating solution used for forming the Cu film, a plating solution similar to the plating solution for forming the second wiring (110) is used.

As described above, the processes (i) and (j) have the same contents as the processes (e) and (.f), respectively. Stack up.

According to the first embodiment, the following operation and effect can be obtained. (1) The second wiring (global wiring: 110, 117), which has a longer wiring length than the first wiring (local wiring: 103), mainly uses copper (Cu). It has a buried wiring structure made of a material, and it is fine and the wiring resistance can be reduced by about 40% compared to A1 wiring, and the CR wiring delay of the second layer or more can be improved. Therefore, _c high-speed operation possible semiconductor integrated circuit device can be obtained

(2) The first wiring (oral wiring) closest to the semiconductor element is mainly made of aluminum (A1), and can prevent Cu contamination of the semiconductor element. Therefore, the reliability of the semiconductor integrated circuit device can be improved. Even if A1 is used, this local wiring has a short wiring length, so it has little effect on high-speed operation.

(3) The second wiring (global wiring), which has a longer wiring length than the first wiring (oral wiring), is mainly made of copper (Cu). Is a material that has better migration resistance than A1, so that the wiring reliability can be improved.

(4) A high melting point metal, which is a different material from the first wiring, is applied to the via wiring connecting the first wiring and the second wiring. Therefore, the problem such as the case of forming the via wiring by the Cu plating process shown in FIG. 38 is solved. That is, corrosion of the first wiring can be avoided, and the reliability of the wiring can be improved. Therefore, "missing" of the first wiring and the via hole provided on the first wiring is allowed, so that the first wiring and the via hole can be miniaturized.

(5) The second wiring made of Cu as the main material, the via wiring on the second wiring, and the third wiring have a buried wiring structure, and they are formed by the plating method. The process cost can be reduced. In other words, the plating method does not require a vacuum device as used in normal semiconductor processes, and is concerned about safety such as high voltage, high temperature, and toxic gas. Nor. The chemicals used are also less expensive than conventional semiconductor process gases. Therefore, even if Cu wiring can be formed by sputtering or CVD, the plating method is overwhelmingly advantageous in terms of cost. (6) The formation of the first wiring made of A1 Normal photolithography-dry etching by technology. In the case of A1 wiring, it is preferable to apply ordinary photolithography technology because of its excellent microfabrication by dry etching technology.

Second embodiment>

A method of manufacturing a semiconductor integrated circuit device according to a second embodiment of the present invention will be described with reference to FIGS.

In the present embodiment, a buried wiring forming technique using CMP is applied to the formation of the first wiring made of A1.

Step (a)

As shown in Fig. 11, an interlayer dielectric having a wiring groove pattern on a semiconductor substrate (10 1) made of single-crystal Si whose main surface is covered with a CVD-Si02 film or a thermally oxidized Si02 film (102) A film (104) is formed. This interlayer insulating film (104) has a thickness of 300 nm, and is made of a silicon oxide film Si02 formed by a plasma CVD method using ortho-ethyl silicate Si (OC ₂ H ₅ ) ₄ as a source gas. Subsequently, a wiring pattern is formed by a resist (not shown) on the inter-layer insulating film (104) by a photolithography technique. Next, the Si02 film (104) is etched by a dry etching technique using the resist as a mask. As a result, the wiring pattern (wiring forming groove) is transferred to the interlayer insulating film. Then, the above-mentioned resist is removed.

Although not shown, the semiconductor substrate is also used in the second embodiment. (101) On the main surface, as a semiconductor element (elements) constituting a circuit, a CM0S transistor composed of a pair of transistors of a P-channel MISFET (PMOS) and an N-channel MISFET (NMOS) is used. A plurality is formed. For example, plugs such as polycrystalline silicon or tungsten are connected to the source / drain regions of these CMOS transistors through contact through holes provided in the Si02 film (102). I have.

Step (b)

As shown in FIG. 12, a conductor layer (103a) is deposited on the interlayer insulating film (104) on which the wiring pattern (wiring forming groove) is formed. This conductor layer

(103a) is a stack of 30 nm of Ti to improve the adhesion to the Si02 film, 70 nm of TiN as a barrier layer, and 300 nm of Al-0.5Cu with Al as the main wiring material, in order from the bottom. Consists of a membrane. Then, the conductor layer is reflowed by annealing at 500 ° C. and buried in the wiring forming groove.

Process)

As shown in FIG. 13, the unnecessary conductor layer on the interlayer insulating film (104) is polished by the CMP method so that the first wiring (103) is formed in the wiring forming groove of the interlayer insulating film (104). Is buried.

Step (d)

As shown in FIG. 14, a via hole (106) is formed in the interlayer insulating film (105) by photolithography. First, an interlayer insulating film (105) having a thickness of 800 nm is formed on the first wiring (103). Similar to the interlayer insulation Enmaku (105) the interlayer insulating film (104), the orthosilicate Echiruesute Le Si (0C ₂ H ₅₎ ₄ as a source gas, is formed by a plasma CVD method Made of silicon oxide film Si02. Subsequently, as in the step (c) of the first embodiment, via holes (106) are formed in the interlayer insulating film (105) by photolithography.

Step (e)

As shown in FIG. 15, via wiring (107) is formed in the via hole (106). The via wiring (107) is formed for the same reason and in the same method as in the step (d) of the first embodiment. That is, the material as the via wiring (10 ends) for electrically connecting the first wiring (oral wiring) made of Cu and the second wiring (global wiring) made of Cu can be avoided. A high melting point metal such as

Process (f)

As shown in FIG. 16, a 100 nm SiN film (108) is formed on the entire surface of the interlayer insulating film (105) on which the via wiring (107) is formed by plasma CVD, and a Si02 film is formed on the SiN film (108). A film (109) is deposited to a thickness of 300 nm to form an interlayer insulating film. A wiring pattern is formed by a resist (not shown) on the interlayer insulating film (108, 109) by a photolithography technique. Next, using the above resist as a mask, dry etching

(109) is etched. In this dry etching, the etching gas is controlled so that the selection ratio between the two is sufficiently large so that the Si02 film is etched and the SiN film is not etched. For this reason, the lower SiN film (108) acts as an etching stopper. That is, the etching of the Si02 film (109) stops at the surface of the SiN film (108). Since the SiN film (108) becomes an etching stopper, the lower interlayer insulating film (105) is not etched. Subsequently, the etching gas is switched and the wiring is formed by etching the SiN film (108). The pattern is transferred to an interlayer insulating film to form a wiring forming groove (wiring groove), and then the above-mentioned resist is removed.

Process (g)

As shown in FIG. 17, a second wiring (109) is formed in a wiring forming groove (wiring groove) formed in the interlayer insulating film (108, 109).

First, 30 nm of Ti and 70 nm of TiN are sequentially formed as an adhesive layer on the main surface of the semiconductor substrate on which the wiring grooves are formed by the Spack method. Subsequently, a Cu film is formed to a thickness of 50 nm on the TiN as a seed film by a sputtering method. Subsequently, a 250 nm thick Cu film is formed on the Cu film by an electrolytic plating method. Then, the Cu film and the adhesive layer in the flat portion are polished and removed by the CMP method to form a second wiring (110).

The Cu electroplating is performed using a 0.3 mol I1 copper sulfate (CuS04) solution as a plating solution, similarly to the step (f) of the first embodiment. The thickness of the formed Cu film is controlled by the masking time.

Process (h)

As shown in FIG. 18, an interlayer insulating film (111, 112) is formed on the interlayer insulating film (108, 109) in which the second wiring (110) is embedded, and the interlayer insulating film (111, 112) is formed. In (), a via hole (113) is formed by ordinary photolithography technology. This step is achieved by a method similar to step (e) of the first embodiment.

Step (i)

As shown in FIG. 19, via wiring (114) is formed in the via hole (113). First, Ti 30 nm and TiN 70 nm are formed as an adhesive layer by a sputtering method on the entire surface of the interlayer insulating film (111, 112) in which the via hole (113) is formed. Next, a Cu film was formed on TiN as a seed film by sputtering. 50 nm is formed. A 250 nm Cu film is further formed on the Cu film by an electrolytic plating method. The thickness of the conductor film (Ti film / TiN film / sputter Cu film / Cu plating film) for forming via wiring is thinner (400M) than the depth (900nm) of the via hole (113). Even if it is, it is buried with a Cu film in the via hole (113) with a small diameter. Subsequently, the Cu film and the adhesive layer in the flat portion are polished and removed by a CMP method to form a via wiring (114). The plating solution used for forming the second film (110) is used as the plating solution used for forming the Cu film. Process (j)

As shown in FIG. 20, an interlayer insulating film (115, 116) is formed on the interlayer insulating film (111, 112) in which the second wiring (114) is embedded, and the interlayer insulating film (115, 116) is formed. At 116), a wiring groove is formed by a normal photolithography technique, and then the resist is removed. This step is achieved by a method similar to step (i) of the first embodiment.

Process (k)

As shown in FIG. 21, a third wiring (117) is formed in a wiring groove formed in the interlayer insulating film (115, 116). This step is achieved by a method similar to step (g) of the second embodiment.

In the second embodiment, when an upper Cu wiring is further stacked on the third wiring (117), the steps (h) to (k) are repeated.

According to the second embodiment, the following operation and effect can be obtained.

(1) The effects (1) to (5) described in the first embodiment can be obtained.

(2) According to the second embodiment, since the first wiring is formed by the embedded wiring forming technique, the first embodiment (the first wiring is usually The formation of a TiN film as an anti-reflection layer, which is required by photolithography, is not required.

However, when A1 is processed by CMP as in the second embodiment, since A1 is softer than Cu, there is a concern that polishing scratches and surface dents (dishing) may occur during CMP.

A method of manufacturing a semiconductor integrated circuit device according to a third embodiment of the present invention will be described with reference to FIGS.

In the third embodiment, the contact resistance between the via wiring and the second wiring connected to the via wiring is reduced.

The method of manufacturing a semiconductor integrated circuit device according to the third embodiment includes the following steps (f) to (1) following the steps (a) to (e) of the second embodiment. Is executed.

Process (f)

After the via wiring (107) made of W shown in FIG. 15 is formed by the CMP method, as shown in FIG. 22, the Si02 film (105) is polished by the CMP method, and the via wiring (107) is formed. 107) is projected. The protrusion of the via wiring (107) is formed at a height of, for example, 50 nm.

Process (g)

Subsequently, as shown in FIG. 23, an interlayer insulating film (108, 109) is formed on the interlayer insulating film (105) according to the step (f) of the second embodiment. Then, a wiring forming groove (wiring groove) having a predetermined pattern is formed in the interlayer insulating film (108, 109).

Process (h)

As shown in FIG. 24, according to the step (g) of the second embodiment, the layer A second wiring (109) is formed in a wiring forming groove (wiring groove) formed in the inter-insulating film (108, 109). The second wiring (109) is formed by a CMP method. Therefore, the surface of the second wiring (109) is flattened, and the protrusion of the via wiring (107) does not appear on the surface of the second wiring (109).

Step (i)

As shown in FIG. 25, according to the step (h) of the second embodiment, the interlayer insulating film (111, 112) is formed on the interlayer insulating film (108, 109) in which the second wiring (110) is embedded. ) Is formed, and a via hole (113) is formed in the interlayer insulating film (111, 112) by ordinary photolithography.

Step (j)

As shown in FIG. 26, a via wiring (114) made of Cu is formed in the via hole (113) according to the step (i) of the second embodiment. Subsequently, the interlayer insulating film (111, 112) is polished by a CMP method to project the via wiring (114). The protrusion of the via wiring (114) is formed at a height of, for example, 10. The Cu that composes the via wiring (114) is softer than W, so it is removed during polishing of the interlayer insulating film (111, 112). For this reason, it is more difficult to make a large protrusion in this via wiring (114) than in the via wiring (107) made of W, but as shown in the figure, the surface of the via wiring (114) has a convex shape of about 10 nm. If so, the purpose of reducing contact resistance will be achieved.

Process (k)

Subsequently, as shown in FIG. 27, an interlayer insulating film (115, 116) is formed on the interlayer insulating film (111, 112) according to the step (j) of the second embodiment. Then, a wiring forming groove (wiring groove) having a predetermined pattern is formed in the interlayer insulating film (115, 116). Process (1)

As shown in FIG. 28, a third wiring (117) is formed in a wiring groove formed in the interlayer insulating film (115, 116) according to the step (k) of the second embodiment.

In the third embodiment, when an upper layer Cu wiring is further stacked on the third wiring (117), the steps (h) to (k) are repeated.

According to the third embodiment, the following operation and effect can be obtained.

(1) The effects (1) to (5) described in the first embodiment can be obtained.

(2) Since the first wiring is formed by the buried wiring forming technique as in the second embodiment, the first wiring is formed by the ordinary photolithography technique. It is not necessary to form a required TiN film as an antireflection layer.

(3) In step (f), after the via wiring (107) is formed by the CMP method, the Si02 film (105) is polished by the CMP method, and the first via wiring (107) is projected. I have. That is, the side surface of the first via wiring (107) is exposed to increase the surface area of the wiring. Therefore, the contact area between the first via wiring (107) and the second wiring (110) is increased as compared with the case of the second embodiment, and the contact resistance can be reduced.

In the step (j), the second via wiring (114) is projected for the same purpose. Therefore, the contact area between the first via wiring (114) and the third wiring (117) is increased as compared with the case of the second embodiment, and the contact resistance can be reduced.

In short, the third embodiment has at least two layers on the semiconductor substrate. A semiconductor integrated circuit device having a multilayer wiring having upper Cu wiring and via wiring connecting between respective wiring layers, wherein at least one Cu wiring (second wiring 110) and lower wiring (first wiring) are provided. 103), the upper surface of the via wiring (107) is above the bottom surface (the contact surface with the inter-layer insulating film 105) of the Cu wiring excluding the connection region with the via wiring. In

A method of manufacturing a semiconductor integrated circuit device according to a fourth embodiment of the present invention will be described with reference to FIGS. 29 to 35.

The fourth embodiment reduces the wiring (plug) resistance by reducing the height of the first via wiring (plug) made of W in particular. In the method of manufacturing the device, following the steps (a) to (e) of the second embodiment, the following steps (f) to (1) are performed.

Step (f)

The via wiring (107) made of W shown in FIG. 15 is excessively polished by the CMP method. Therefore, the main surface of the polished via wiring (107) is lower than the surface of the interlayer insulating film (105) as shown in FIG. The step of the via wiring (107) has, for example, 10 nm.

Process (g)

As shown in FIG. 30, an interlayer insulating film (108, 109) is formed on the interlayer insulating film (105) according to the step (f) of the second embodiment. Then, a wiring forming groove (wiring groove) having a predetermined pattern is formed in the interlayer insulating film (108, 109). P

27 process (h)

As shown in FIG. 31, according to the step (g) of the second embodiment, the second wiring (wiring groove) is formed in the wiring forming groove (wiring groove) formed in the interlayer insulating film (108, 109). 109). The second wiring (109) is formed by a CMP method. Therefore, the surface of the second wiring (109) is flattened, and the recess of the via wiring (107) does not appear on the surface of the second wiring (109).

Step (i)

As shown in FIG. 32, according to the step (h) of the second embodiment, the interlayer insulating film (111, 112) is formed on the interlayer insulating film (108, 109) in which the second wiring (110) is embedded. ) Is formed, and a via hole (113) is formed in the interlayer insulating film (111, 112) by ordinary photolithography.

Step (j)

As shown in FIG. 33, a via wiring (114) made of Cu is formed in the via hole (113) according to the step (i) of the second embodiment. In this step, the via wiring (114) is CMP-processed so that no step is formed between the surface of the interlayer insulating film (111, 112) and the surface of the via wiring (114). Process (k)

As shown in FIG. 34, an interlayer insulating film (115, 116) is formed on the interlayer insulating film (111, 112) according to the step (j) of the second embodiment. Then, a wiring forming groove (wiring groove) having a predetermined pattern is formed in the interlayer insulating film (115, 116).

Process (1)

As shown in FIG. 35, a third wiring (117) is formed in a wiring groove formed in the interlayer insulating film (115, 116) according to the step (k) of the second embodiment. Also in the fourth embodiment, when an upper layer Cu wiring is further stacked on the third wiring (117), the steps (h) to (k) of this embodiment are repeatedly performed.

According to the fourth embodiment, the following operation and effect can be obtained. (1) The effects (1) to (5) described in the first embodiment can be obtained.

(2) As in the second embodiment, the first wiring is formed by a buried wiring forming technique. Therefore, the first wiring is formed (the first wiring is formed by a normal photolithography technique). Thus, the formation of a TiN film as an anti-reflection layer, which is required in the above, becomes unnecessary.

(3) In step (f), the via wiring (107) is excessively polished by the CMP method. Therefore, the main surface of the first via wiring (107) made of polished W is lower than the surface of the interlayer insulating film (105) as shown in FIG. Therefore, by reducing the height of the first via wiring (plug) made of W, the resistance of the wiring (plug) can be reduced.

In short, the fourth embodiment is a semiconductor integrated circuit device having at least two or more Cu wiring layers and a via wiring connecting each wiring layer on a semiconductor substrate, and at least one Cu wiring ( The upper surface of the via wiring (107) connecting the second wiring 110) and the lower wiring (first wiring 103) is formed on the bottom surface of the Cu wiring excluding the connection region with the via wiring (interlayer insulating film 105 and Below the contact surface).

K Fifth Embodiment>

A method of manufacturing a semiconductor integrated circuit device according to a fifth embodiment of the present invention will be described with reference to FIG. The fifth embodiment reduces the connection resistance between the first wiring and the via wiring connected to the first wiring. I have.

In the method of manufacturing a semiconductor integrated circuit device according to the fifth embodiment, a step (d ′) described below is added following the steps (a) to (d) of the second embodiment. .

Step (d ')

After forming the via hole (106) shown in FIG. 15, the first wiring (103) of the A1-0.5% Cu layer exposed in the via hole (106) is dry-etched. A groove is provided. The groove (103) is self-aligned with the via hole (106). The depth of the groove is arbitrary, for example, about 50 mn.

Subsequently, the steps (e) to (k) of the second embodiment are performed, and the semiconductor integrated circuit device shown in FIG. 36 is obtained.

According to the fifth embodiment, the following operation and effect can be obtained.

(1) The effects (1) to (5) described in the first embodiment can be obtained.

(2) As in the second embodiment, the first wiring is formed by a buried wiring forming technique, so that the first wiring (the first wiring is a conventional photolithography technique) It is not necessary to form a TiN film as an anti-reflection layer, which is required in the step.

(3) In the above step (d ′), the first wiring (103) is provided with a groove by dry etching. Therefore, the first via wiring (107) and the second wiring (110) are in contact with the groove bottom surface and the groove side wall surface, and the contact area between them increases as compared with the case of the second embodiment. Therefore, the contact resistance can be reduced.

In short, in the fifth embodiment, in particular, a metal other than Cu is used as a main component. The bottom surface of the first via wiring (107) mainly composed of W that connects the first wiring (103) and the Cu wiring layer thereon is formed by the first wiring (excluding the connection region of this via wiring). 103) is located below the upper surface.

(Sixth embodiment)

FIG. 37 is a cross-sectional view of the semiconductor integrated circuit device showing a state where the semiconductor element (M0S) is formed on the semiconductor base.

As shown in FIG. 37, an element isolation region GI is selectively formed on the main surface of the semiconductor substrate (101). Are formed. Specifically, the element isolation region GI is formed by forming a groove on the substrate surface and burying an insulating film in the groove. This element isolation region GI is also referred to as trench isolation. The MOS transistor (M0S) is composed of a gate electrode having a laminated structure of polycrystalline silicon and a metal formed thereon as a gate electrode, and a side wall spacer is provided on the side wall. Have been. Then, a plug (for example, W) is provided in the interlayer insulating film (102). This plug is connected to a source drain region (not shown) provided in the semiconductor substrate (101). The wiring and the interlayer insulating film on the interlayer insulating film (102) are formed, for example, according to the first embodiment. On the third wiring (117), a third via wiring (118) and a fourth wiring (119) made of Cu are further buried in the interlayer insulating film.

As described above, according to the present invention, a semiconductor integrated circuit device having high speed operation and high reliability can be obtained.

Industrial applicability According to the present invention, it is an effective technique when applied to a semiconductor integrated circuit device having a high-speed logic circuit requiring fine wiring and high speed operation. More specifically, the present invention relates to an LSI in which a memory (DRAM, SRAM, or EEPROM, or a combination thereof) and a high-speed logic circuit are mounted on a single semiconductor substrate. This is effective for realizing an LSI in which high-speed logic circuits are mounted on a single semiconductor substrate.

Claims

The scope of the claims

1. A first wiring is provided on the main surface of the semiconductor substrate, a first interlayer insulating film is provided so as to cover the first wiring, and via a via hole provided in the first interlayer insulating film. A first via wiring connected to a part of the first wiring, and embedded in a wiring groove provided in a second interlayer insulating film on the first interlayer insulating film; A semiconductor integrated circuit device comprising: the via wiring connected to the first via wiring; and a second wiring made of a different material from the first wiring.

2. The first wiring is made of a conductor layer mainly made of aluminum, the via wiring is made of a conductor layer mainly made of tungsten, and the second wiring is made of copper as a main material. 2. The semiconductor integrated circuit device according to claim 1, comprising a conductor layer formed.

3. having a via wiring provided in the second interlayer insulating film, having a third interlayer insulating film on the second interlayer insulating film, and being provided in the third different insulating film; A semiconductor integrated circuit device having a third wiring buried in a wiring groove and connected to the second via wiring.

4. The method according to claim 3, wherein the second via wiring is made of a conductor layer mainly made of copper, and the third wiring is made of a conductor layer mainly made of copper. Semiconductor integrated circuit device.

5. An insulating film on the main surface of the semiconductor substrate, a first wiring patterned on the insulating film by photolithography, and a first wiring so as to cover the first wiring. An interlayer insulating film, having a first via wiring connected to a part of the first wiring via a via hole provided in the first interlayer insulating film, Second interlayer insulation on insulating film A semiconductor integrated circuit device having a second wiring buried in a wiring groove provided in an edge film and connected to the first via wiring.

6. The first wiring is made of a conductor layer mainly made of aluminum, the via wiring is made of a conductor layer mainly made of tungsten, and the second wiring is made of copper as a main material. 6. The semiconductor integrated circuit device according to claim 5, comprising a conductor layer.

7. A semiconductor integrated circuit device, wherein the conductor layer constituting the first wiring is formed by sequentially stacking A1 containing Ti, TiN, and Cu and TiN.

8. forming a first wiring composed mainly of aluminum on the main surface of the semiconductor substrate;

Forming a first interlayer insulating film so as to cover the first wiring; forming a via hole in the first interlayer insulating film such that a part of the first wiring is exposed;

Forming a first via wiring connected to a part of the first wiring via the via hole and made of a conductive material different from the first wiring;

Forming a second interlayer insulating film on the first interlayer insulating film; and providing a wiring groove for exposing the first via wiring in the second interlayer insulating film;

Forming a second wiring made of copper as the main material, which is embedded in the wiring groove and connected to the first via wiring, by a sticking process. Manufacturing method.

9. The method for manufacturing a semiconductor integrated circuit according to claim 8, wherein the via wiring is formed of a high melting point metal.

10. The method of claim 2, wherein the second wiring is formed by a first step of electroless plating and a second step of electrolytic plating following the first step. 10. The method for manufacturing a semiconductor integrated circuit device according to item 8 or 9.

11. A semiconductor element is provided in a semiconductor base, and a first wiring mainly made of aluminum is provided on the main surface of the semiconductor base as a local wiring close to the main surface of the base. A second wiring mainly made of copper is provided as a global wiring on the wiring of the first wiring, and the via wiring to be contacted with the first wiring is made of a conductive material different from Cu, and is made of the conductive material. A semiconductor integrated circuit device, wherein the second wiring is connected to the via wiring.

1 2. An interlayer insulating film is provided on the second wiring, a via wiring and a third wiring are provided on the interlayer insulating film, and the via wiring and the third wiring have a lower specific resistance than A1. 12. The semiconductor integrated circuit device according to claim 11, wherein the semiconductor integrated circuit device is made of a conductive material mainly composed of:

13. Multi-layer wiring structure with at least one layer of A1 wiring provided closest to the main surface of the semiconductor substrate and two or more layers of Cu wiring with an interlayer insulating film interposed on the A1 wiring A method of manufacturing a semiconductor integrated circuit device, wherein the A1 wiring pattern is formed by dry etching a metal film containing A1 formed on the entire surface of the semiconductor substrate main surface, and the Cu wiring pattern is an interlayer. A method for manufacturing a semiconductor integrated circuit device, wherein a metal film containing Cu is buried in a groove pattern formed by dry-etching an insulating film.

14. A Cu wiring pattern is formed by forming the metal film containing Cu by a plating method and polishing the metal film by a chemical mechanical polishing method. 14. The method for manufacturing a semiconductor integrated circuit device according to claim 13, wherein the method comprises a 3δ floor.

15. The manufacturing method of a semiconductor integrated circuit device according to claim 14, wherein the plating method of the metal film containing Cu comprises a step of electroless plating and a step of electrolytic plating. Method.

16. A semiconductor integrated circuit device having a multilayer wiring having at least two or more Cu wiring layers on a semiconductor substrate and a via wiring connecting between each wiring layer, wherein at least one Cu wiring and Wherein the upper surface of the via wiring connecting to the via wiring is above the bottom surface of the Cu wiring excluding the connection region with the via wiring.

17. A semiconductor integrated circuit device having at least two or more Cu wiring layers on a semiconductor substrate and a via wiring for connecting each wiring layer, and connecting at least one Cu wiring and a lower wiring. A semiconductor integrated circuit device, wherein an upper surface of a via wiring is below a bottom surface of the Cu wiring excluding a connection region with the via wiring.

18. Connecting the first wiring mainly composed of metal other than Cu and the Cu wiring layer above it The bottom surface of the first via wiring mainly composed of W excludes the connection area of this via wiring. A semiconductor integrated circuit device located below an upper surface of the first wiring.