WO1999052049A3 - Method of designing a constraint-driven integrated circuit layout - Google Patents

Method of designing a constraint-driven integrated circuit layout Download PDF

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Publication number
WO1999052049A3
WO1999052049A3 PCT/US1999/007303 US9907303W WO9952049A3 WO 1999052049 A3 WO1999052049 A3 WO 1999052049A3 US 9907303 W US9907303 W US 9907303W WO 9952049 A3 WO9952049 A3 WO 9952049A3
Authority
WO
WIPO (PCT)
Prior art keywords
integrated circuit
circuit layout
cells
designing
constraint
Prior art date
Application number
PCT/US1999/007303
Other languages
French (fr)
Other versions
WO1999052049A2 (en
Inventor
Patrick R Groeneveld
Ginneken Lukas P P P Van
Original Assignee
Magma Design Automation Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Magma Design Automation Inc filed Critical Magma Design Automation Inc
Priority to AU37424/99A priority Critical patent/AU3742499A/en
Publication of WO1999052049A2 publication Critical patent/WO1999052049A2/en
Publication of WO1999052049A3 publication Critical patent/WO1999052049A3/en

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Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/392—Floor-planning or layout, e.g. partitioning or placement
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/394—Routing
    • G06F30/3953—Routing detailed

Abstract

An automated method for designing an integrated circuit layout with a computer, based upon an electronic circuit description and upon a selected plurality of cells from a cell library, comprising the steps of (a) assigning each of the cells to one of a plurality of buckets designated on the integrated circuit layout, each of the cells being connected to one of the other cells; (b) performing global routing to connect at least some of the selected cells of step (a) together such that global routes are formed to provide net topology information; (c) performing track routing which sets the position of each of the global routes; (d) performing detailed placement such that the positions of all selected cells are fixed within each of the buckets designated on the integrated circuit layout; and (e) performing detailed routing such that detailed routes are formed to complete the integrated circuit layout.
PCT/US1999/007303 1998-04-02 1999-04-02 Method of designing a constraint-driven integrated circuit layout WO1999052049A2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
AU37424/99A AU3742499A (en) 1998-04-02 1999-04-02 Method of designing a constraint-driven integrated circuit layout

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/054,319 US6230304B1 (en) 1997-12-24 1998-04-02 Method of designing a constraint-driven integrated circuit layout
US09/054,319 1998-04-02

Publications (2)

Publication Number Publication Date
WO1999052049A2 WO1999052049A2 (en) 1999-10-14
WO1999052049A3 true WO1999052049A3 (en) 1999-11-18

Family

ID=21990242

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/US1999/007303 WO1999052049A2 (en) 1998-04-02 1999-04-02 Method of designing a constraint-driven integrated circuit layout

Country Status (3)

Country Link
US (1) US6230304B1 (en)
AU (1) AU3742499A (en)
WO (1) WO1999052049A2 (en)

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